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gerrit.openbmc.org / openbmc / openbmc / 6e60e8b2b2bab889379b380a28a167a0edd9d1d3 / . / import-layers / yocto-poky / meta / recipes-devtools / binutils / binutils / 0013-Add-support-for-Netlogic-XLP.patch
blob: b03e04608dee7417db6b62685a0588f4f7ef16ab [file] [log] [blame]
Brad Bishop6e60e8b2018-02-01 10:27:11 -0500[diff] [blame^]1From fc6fa6a6e6e9e6e5ad7080785af31b4ea68f60c4 Mon Sep 17 00:00:00 2001
2From: Khem Raj <raj.khem@gmail.com>
3Date: Sun, 14 Feb 2016 17:06:19 +0000
4Subject: [PATCH 13/15] Add support for Netlogic XLP
5
6Patch From: Nebu Philips <nphilips@netlogicmicro.com>
7
8Using the mipsisa64r2nlm target, add support for XLP from
9Netlogic. Also, update vendor name to NLM wherever applicable.
10
11Use 0x00000080 for INSN_XLP, the value 0x00000040 has already been
12assigned to INSN_OCTEON3
13
14Signed-off-by: Khem Raj <raj.khem@gmail.com>
15Signed-off-by: Baoshan Pang <baoshan.pang@windriver.com>
16Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
17---
18Upstream-Status: Pending
19
20 bfd/aoutx.h | 1 +
21 bfd/archures.c | 1 +
22 bfd/bfd-in2.h | 1 +
23 bfd/config.bfd | 5 +++++
24 bfd/cpu-mips.c | 6 ++++--
25 bfd/elfxx-mips.c | 8 ++++++++
26 binutils/readelf.c | 1 +
27 gas/config/tc-mips.c | 4 +++-
28 gas/configure | 3 +++
29 include/elf/mips.h | 1 +
30 include/opcode/mips.h | 10 ++++++++--
31 ld/configure.tgt | 2 ++
32 opcodes/mips-dis.c | 12 +++++-------
33 opcodes/mips-opc.c | 33 +++++++++++++++++++++------------
34 14 files changed, 64 insertions(+), 24 deletions(-)
35
36diff --git a/bfd/aoutx.h b/bfd/aoutx.h
37index d30e8b8fbc..913b499744 100644
38--- a/bfd/aoutx.h
39+++ b/bfd/aoutx.h
40@@ -812,6 +812,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
41 case bfd_mach_mipsisa64r6:
42 case bfd_mach_mips_sb1:
43 case bfd_mach_mips_xlr:
44+ case bfd_mach_mips_xlp:
45 /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
46 arch_flags = M_MIPS2;
47 break;
48diff --git a/bfd/archures.c b/bfd/archures.c
49index 6f35a5b2a7..d12cdf609a 100644
50--- a/bfd/archures.c
51+++ b/bfd/archures.c
52@@ -197,6 +197,7 @@ DESCRIPTION
53 .#define bfd_mach_mips_octeon2 6502
54 .#define bfd_mach_mips_octeon3 6503
55 .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
56+.#define bfd_mach_mips_xlp 887680 {* decimal 'XLP' *}
57 .#define bfd_mach_mipsisa32 32
58 .#define bfd_mach_mipsisa32r2 33
59 .#define bfd_mach_mipsisa32r3 34
60diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
61index 6288c3bb4a..e9f9859a7b 100644
62--- a/bfd/bfd-in2.h
63+++ b/bfd/bfd-in2.h
64@@ -2041,6 +2041,7 @@ enum bfd_architecture
65 #define bfd_mach_mips_octeon2 6502
66 #define bfd_mach_mips_octeon3 6503
67 #define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
68+#define bfd_mach_mips_xlp 887680 /* decimal 'XLP' */
69 #define bfd_mach_mipsisa32 32
70 #define bfd_mach_mipsisa32r2 33
71 #define bfd_mach_mipsisa32r3 34
72diff --git a/bfd/config.bfd b/bfd/config.bfd
73index 63596c2ebc..6e923fb0ed 100644
74--- a/bfd/config.bfd
75+++ b/bfd/config.bfd
76@@ -1166,6 +1166,11 @@ case "${targ}" in
77 targ_defvec=mips_elf32_le_vec
78 targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec"
79 ;;
80+ mipsisa64*-*-elf*)
81+ targ_defvec=mips_elf32_trad_be_vec
82+ targ_selvecs="mips_elf32_trad_le_vec mips_elf64_trad_be_vec mips_elf64_trad_le_vec"
83+ want64=true
84+ ;;
85 mips*-*-elf* | mips*-*-rtems* | mips*-*-windiss | mips*-*-none)
86 targ_defvec=mips_elf32_be_vec
87 targ_selvecs="mips_elf32_le_vec mips_elf64_be_vec mips_elf64_le_vec"
88diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
89index b9ecdd6e55..df1bffc25b 100644
90--- a/bfd/cpu-mips.c
91+++ b/bfd/cpu-mips.c
92@@ -104,7 +104,8 @@ enum
93 I_mipsocteon2,
94 I_mipsocteon3,
95 I_xlr,
96- I_micromips
97+ I_micromips,
98+ I_xlp
99 };
100
101 #define NN(index) (&arch_info_struct[(index) + 1])
102@@ -155,7 +156,8 @@ static const bfd_arch_info_type arch_info_struct[] =
103 N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)),
104 N (64, 64, bfd_mach_mips_octeon3, "mips:octeon3", FALSE, NN(I_mipsocteon3)),
105 N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)),
106- N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0)
107+ N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,NN(I_micromips)),
108+ N (64, 64, bfd_mach_mips_xlp, "mips:xlp", FALSE, 0)
109 };
110
111 /* The default architecture is mips:3000, but with a machine number of
112diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
113index 723853f821..7b464211c3 100644
114--- a/bfd/elfxx-mips.c
115+++ b/bfd/elfxx-mips.c
116@@ -6787,6 +6787,9 @@ _bfd_elf_mips_mach (flagword flags)
117 case E_MIPS_MACH_XLR:
118 return bfd_mach_mips_xlr;
119
120+ case E_MIPS_MACH_XLP:
121+ return bfd_mach_mips_xlp;
122+
123 default:
124 switch (flags & EF_MIPS_ARCH)
125 {
126@@ -12106,6 +12109,10 @@ mips_set_isa_flags (bfd *abfd)
127 val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2;
128 break;
129
130+ case bfd_mach_mips_xlp:
131+ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_XLP;
132+ break;
133+
134 case bfd_mach_mipsisa32:
135 val = E_MIPS_ARCH_32;
136 break;
137@@ -14135,6 +14142,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
138 { bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
139 { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
140 { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64r2 },
141+ { bfd_mach_mips_xlp, bfd_mach_mipsisa64r2 },
142
143 /* MIPS64 extensions. */
144 { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
145diff --git a/binutils/readelf.c b/binutils/readelf.c
146index 8dca490226..b5f577f5a1 100644
147--- a/binutils/readelf.c
148+++ b/binutils/readelf.c
149@@ -3261,6 +3261,7 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
150 case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
151 case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
152 case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
153+ case E_MIPS_MACH_XLP: strcat (buf, ", xlp"); break;
154 case 0:
155 /* We simply ignore the field in this case to avoid confusion:
156 MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
157diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
158index e24e84df54..baf84e419d 100644
159--- a/gas/config/tc-mips.c
160+++ b/gas/config/tc-mips.c
161@@ -552,6 +552,7 @@ static int mips_32bitmode = 0;
162 || mips_opts.arch == CPU_RM7000 \
163 || mips_opts.arch == CPU_VR5500 \
164 || mips_opts.micromips \
165+ || mips_opts.arch == CPU_XLP \
166 )
167
168 /* Whether the processor uses hardware interlocks to protect reads
169@@ -581,6 +582,7 @@ static int mips_32bitmode = 0;
170 && mips_opts.isa != ISA_MIPS3) \
171 || mips_opts.arch == CPU_R4300 \
172 || mips_opts.micromips \
173+ || mips_opts.arch == CPU_XLP \
174 )
175
176 /* Whether the processor uses hardware interlocks to protect reads
177@@ -19409,7 +19411,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
178 /* Broadcom XLP.
179 XLP is mostly like XLR, with the prominent exception that it is
180 MIPS64R2 rather than MIPS64. */
181- { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
182+ { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLP },
183
184 /* MIPS 64 Release 6 */
185 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
186diff --git a/gas/configure b/gas/configure
187index a36f1ae161..99f0a94e20 100755
188--- a/gas/configure
189+++ b/gas/configure
190@@ -12989,6 +12989,9 @@ _ACEOF
191 mipsisa64r6 | mipsisa64r6el)
192 mips_cpu=mips64r6
193 ;;
194+ mipsisa64r2nlm | mipsisa64r2nlmel)
195+ mips_cpu=xlp
196+ ;;
197 mipstx39 | mipstx39el)
198 mips_cpu=r3900
199 ;;
200diff --git a/include/elf/mips.h b/include/elf/mips.h
201index 3e27b05122..81ea78a817 100644
202--- a/include/elf/mips.h
203+++ b/include/elf/mips.h
204@@ -290,6 +290,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
205 #define E_MIPS_MACH_SB1 0x008a0000
206 #define E_MIPS_MACH_OCTEON 0x008b0000
207 #define E_MIPS_MACH_XLR 0x008c0000
208+#define E_MIPS_MACH_XLP 0x008f0000
209 #define E_MIPS_MACH_OCTEON2 0x008d0000
210 #define E_MIPS_MACH_OCTEON3 0x008e0000
211 #define E_MIPS_MACH_5400 0x00910000
212diff --git a/include/opcode/mips.h b/include/opcode/mips.h
213index 0d043d9520..450e9c2d67 100644
214--- a/include/opcode/mips.h
215+++ b/include/opcode/mips.h
216@@ -1244,8 +1244,10 @@ static const unsigned int mips_isa_table[] = {
217 #define INSN_LOONGSON_2F 0x80000000
218 /* Loongson 3A. */
219 #define INSN_LOONGSON_3A 0x00000400
220-/* RMI Xlr instruction */
221-#define INSN_XLR 0x00000020
222+/* Netlogic Xlr instruction */
223+#define INSN_XLR 0x00000020
224+/* Netlogic XlP instruction */
225+#define INSN_XLP 0x00000080
226
227 /* DSP ASE */
228 #define ASE_DSP 0x00000001
229@@ -1344,6 +1346,7 @@ static const unsigned int mips_isa_table[] = {
230 #define CPU_OCTEON2 6502
231 #define CPU_OCTEON3 6503
232 #define CPU_XLR 887682 /* decimal 'XLR' */
233+#define CPU_XLP 887680 /* decimal 'XLP' */
234
235 /* Return true if the given CPU is included in INSN_* mask MASK. */
236
237@@ -1421,6 +1424,9 @@ cpu_is_member (int cpu, unsigned int mask)
238 return ((mask & INSN_ISA_MASK) == INSN_ISA32R6)
239 || ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
240
241+ case CPU_XLP:
242+ return (mask & INSN_XLP) != 0;
243+
244 default:
245 return FALSE;
246 }
247diff --git a/ld/configure.tgt b/ld/configure.tgt
248index 4e77383a19..8a81f7ac39 100644
249--- a/ld/configure.tgt
250+++ b/ld/configure.tgt
251@@ -504,6 +504,8 @@ mips*el-sde-elf* | mips*el-mti-elf* | mips*el-img-elf*)
252 mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*)
253 targ_emul=elf32btsmip
254 targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;;
255+mipsisa64*-*-elf*) targ_emul=elf32btsmip
256+ targ_extra_emuls="elf32ltsmip elf64btsmip elf64ltsmip" ;;
257 mips64*el-ps2-elf*) targ_emul=elf32lr5900n32
258 targ_extra_emuls="elf32lr5900"
259 targ_extra_libpath=$targ_extra_emuls ;;
260diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
261index bb9912e462..70ecc51717 100644
262--- a/opcodes/mips-dis.c
263+++ b/opcodes/mips-dis.c
264@@ -648,13 +648,11 @@ const struct mips_arch_choice mips_arch_choices[] =
265 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
266 mips_cp1_names_mips3264, mips_hwr_names_numeric },
267
268- /* XLP is mostly like XLR, with the prominent exception it is being
269- MIPS64R2. */
270- { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR,
271- ISA_MIPS64R2 | INSN_XLR, 0,
272- mips_cp0_names_xlr,
273- mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
274- mips_cp1_names_mips3264, mips_hwr_names_numeric },
275+ { "xlp", 1, bfd_mach_mips_xlp, CPU_XLP,
276+ ISA_MIPS64R2 | INSN_XLP, 0,
277+ mips_cp0_names_mips3264r2,
278+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
279+ mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
280
281 /* This entry, mips16, is here only for ISA/processor selection; do
282 not print its name. */
283diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
284index 5cb8e7365f..f2074856a2 100644
285--- a/opcodes/mips-opc.c
286+++ b/opcodes/mips-opc.c
287@@ -320,7 +320,8 @@ decode_mips_operand (const char *p)
288 #define IOCTP (INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3)
289 #define IOCT2 (INSN_OCTEON2 | INSN_OCTEON3)
290 #define IOCT3 INSN_OCTEON3
291-#define XLR INSN_XLR
292+#define XLR INSN_XLR
293+#define XLP INSN_XLP
294 #define IVIRT ASE_VIRT
295 #define IVIRT64 ASE_VIRT64
296
297@@ -958,6 +959,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
298 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
299 {"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 },
300 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
301+{"crc", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
302 /* ctc0 is at the bottom of the table. */
303 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
304 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
305@@ -990,12 +992,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
306 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 },
307 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
308 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 },
309-{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 },
310+{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR|XLP, 0, 0 },
311 {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 },
312 {"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
313 {"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
314 {"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
315 {"dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
316+{"dcrc", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
317 /* dctr and dctw are used on the r5000. */
318 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
319 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
320@@ -1067,6 +1070,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
321 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 },
322 {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
323 {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
324+{"dmfur", "t,d", 0x7000001e, 0xffe007ff, WR_1, 0, XLP, 0, 0 },
325 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 },
326 {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
327 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE },
328@@ -1082,6 +1086,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
329 /* dmfc3 is at the bottom of the table. */
330 /* dmtc3 is at the bottom of the table. */
331 {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
332+{"dmtur", "t,d", 0x7000001f, 0xffe007ff, RD_1, 0, XLP, 0, 0 },
333+{"dmul", "d,s,t", 0x70000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
334 {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
335 {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 },
336 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 },
337@@ -1235,9 +1241,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
338 {"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 },
339 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 },
340 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 },
341-{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
342-{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
343-{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
344+{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
345+{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
346+{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
347 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
348 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
349 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
350@@ -1402,7 +1408,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
351 {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 },
352 {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 },
353 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 },
354-{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1|RD_2, 0, XLR, 0, 0 },
355+{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR|XLP, 0, 0 },
356 {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 },
357 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
358 {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
359@@ -1447,10 +1453,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
360 /* move is at the top of the table. */
361 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
362 {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 },
363+{"msgsnds", "d,t", 0x4a000001, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 },
364 {"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR, 0, 0 },
365 {"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR, 0, 0 },
366-{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR, 0, 0 },
367-{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR, 0, 0 },
368+{"msglds", "d,t", 0x4a000002, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 },
369+{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR|XLP, 0, 0 },
370+{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR|XLP, 0, 0 },
371+{"msgsync", "", 0x4a000004, 0xffffffff,0, 0, XLP, 0, 0 },
372 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 },
373 {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
374 {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 },
375@@ -1500,7 +1509,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
376 {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 },
377 {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 },
378 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 },
379-{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1|RD_2, 0, XLR, 0, 0 },
380+{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR|XLP, 0, 0 },
381 {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
382 {"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
383 {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
384@@ -1937,9 +1946,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
385 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37},
386 {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 },
387 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 },
388-{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
389-{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
390-{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
391+{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
392+{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
393+{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
394 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
395 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
396 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 },
397--
3982.12.0
399