meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0062-Added-new-MB-64-single-register-arithmetic-instructi.patch

From bb65903ab6293a47d154764a585f6c53b5fcf853 Mon Sep 17 00:00:00 2001
From: Nagaraju <nmekala@xilinx.com>
Date: Fri, 23 Aug 2019 16:16:53 +0530
Subject: [PATCH 62/63] Added new MB-64 single register arithmetic instructions

---
 gcc/config/microblaze/microblaze.md | 56 +++++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
index 3e7c647..4d40cc5 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -654,6 +654,18 @@
    }
 })
 
+(define_insn "adddi3_int"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+  (plus:DI (match_operand:DI 1 "register_operand" "%0")
+                 (match_operand:DI 2 "immediate_operand" "I")))]
+  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
+  "@
+  addlik\t%0,%2"
+  [(set_attr "type"     "darith")
+  (set_attr "mode"      "DI")
+  (set_attr "length"    "4")]
+)
+
 (define_insn "*adddi3_long"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
 	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
@@ -719,6 +731,18 @@
 {
 }")
 
+(define_insn "subdi316imm"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+        (minus:DI (match_operand:DI 1 "register_operand" "d")
+                  (match_operand:DI 2 "arith_operand" "K")))]
+  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767) && (REGNO (operands[0]) == REGNO (operands[1]))"
+  "@
+   addlik\t%0,-%2"
+  [(set_attr "type"     "darith")
+  (set_attr "mode"      "DI")
+  (set_attr "length"    "4")])
+
+
 (define_insn "subsidi3"
   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
 	(minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
@@ -1015,6 +1039,17 @@
 ;; Logical
 ;;----------------------------------------------------------------
 
+(define_insn "anddi3imm16"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+        (and:DI (match_operand:DI 1 "arith_operand" "%0")
+                (match_operand:DI 2 "arith_operand" "K")))]
+  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
+  "@
+   andli\t%0,%2"
+  [(set_attr "type"     "darith")
+  (set_attr "mode"      "DI")
+  (set_attr "length"    "4")])
+
 (define_insn "anddi3"
   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
 	(and:DI (match_operand:DI 1 "arith_operand" "d,d,d")
@@ -1042,6 +1077,16 @@
   (set_attr "mode"	"SI,SI,SI,SI")
   (set_attr "length"	"4,8,8,8")])
 
+(define_insn "iordi3imm16"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+        (ior:DI (match_operand:DI 1 "arith_operand" "%0")
+                (match_operand:DI 2 "arith_operand" "K")))]
+  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
+  "@
+   orli\t%0,%2"
+  [(set_attr "type"     "darith")
+  (set_attr "mode"      "DI")
+  (set_attr "length"    "4")])
 
 (define_insn "iordi3"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -1069,6 +1114,17 @@
   (set_attr "mode"	"SI,SI,SI,SI")
   (set_attr "length"	"4,8,8,8")])
 
+(define_insn "xordi3imm16"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+        (xor:DI (match_operand:DI 1 "arith_operand" "%0")
+                (match_operand:DI 2 "arith_operand" "K")))]
+  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
+  "@
+   xorli\t%0,%2"
+  [(set_attr "type"     "darith")
+  (set_attr "mode"      "DI")
+  (set_attr "length"    "4")])
+
 (define_insn "xordi3"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
 	(xor:DI (match_operand:DI 1 "arith_operand" "%d,d")
-- 
2.7.4