Patrick Williams | 864cc43 | 2023-02-09 14:54:44 -0600 | [diff] [blame^] | 1 | From 2bb9fb8414b8ad35ed5fc6c91a34c21cef285a01 Mon Sep 17 00:00:00 2001 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 2 | From: Rui Miguel Silva <rui.silva@linaro.org> |
| 3 | Date: Wed, 18 Dec 2019 21:52:34 +0000 |
| 4 | Subject: [PATCH 1/2] armv7: adding generic timer access through MMIO |
| 5 | |
| 6 | Upstream-Status: Pending [Not submitted to upstream yet] |
| 7 | Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> |
| 8 | |
| 9 | This driver enables the ARMv7 generic timer. |
| 10 | |
| 11 | The access to the timer registers is through memory mapping (MMIO). |
| 12 | |
| 13 | This driver can be used by u-boot to access to the timer through MMIO |
| 14 | when arch_timer is not available in the core (access using system |
| 15 | instructions not possible), for example, in case of Cortex-A5. |
| 16 | |
| 17 | This driver configures and enables the generic timer at |
| 18 | the u-boot initcall level (timer_init) before u-boot relocation. |
| 19 | |
| 20 | Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> |
| 21 | Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> |
| 22 | |
| 23 | %% original patch: 0001-armv7-adding-generic-timer-access-through-MMIO.patch |
Patrick Williams | 92b42cb | 2022-09-03 06:53:57 -0500 | [diff] [blame] | 24 | |
| 25 | Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 26 | --- |
| 27 | arch/arm/cpu/armv7/Makefile | 1 + |
| 28 | arch/arm/cpu/armv7/mmio_timer.c | 75 +++++++++++++++++++++++++++++++++ |
| 29 | scripts/config_whitelist.txt | 1 + |
| 30 | 3 files changed, 77 insertions(+) |
| 31 | create mode 100644 arch/arm/cpu/armv7/mmio_timer.c |
| 32 | |
| 33 | diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile |
Patrick Williams | 92b42cb | 2022-09-03 06:53:57 -0500 | [diff] [blame] | 34 | index bfbd85ae64ef..1a0a24e53110 100644 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 35 | --- a/arch/arm/cpu/armv7/Makefile |
| 36 | +++ b/arch/arm/cpu/armv7/Makefile |
| 37 | @@ -28,6 +28,7 @@ obj-$(CONFIG_ARMV7_PSCI) += psci.o psci-common.o |
| 38 | obj-$(CONFIG_IPROC) += iproc-common/ |
| 39 | obj-$(CONFIG_KONA) += kona-common/ |
| 40 | obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o |
| 41 | +obj-$(CONFIG_SYS_MMIO_TIMER) += mmio_timer.o |
| 42 | |
| 43 | ifneq (,$(filter s5pc1xx exynos,$(SOC))) |
| 44 | obj-y += s5p-common/ |
| 45 | diff --git a/arch/arm/cpu/armv7/mmio_timer.c b/arch/arm/cpu/armv7/mmio_timer.c |
| 46 | new file mode 100644 |
Patrick Williams | 92b42cb | 2022-09-03 06:53:57 -0500 | [diff] [blame] | 47 | index 000000000000..edd806e06e42 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 48 | --- /dev/null |
| 49 | +++ b/arch/arm/cpu/armv7/mmio_timer.c |
| 50 | @@ -0,0 +1,75 @@ |
| 51 | +// SPDX-License-Identifier: GPL-2.0+ |
| 52 | +/* |
| 53 | + * Copyright (c) 2019, Arm Limited. All rights reserved. |
| 54 | + * |
| 55 | + */ |
| 56 | + |
| 57 | +#include <common.h> |
| 58 | +#include <asm/io.h> |
| 59 | +#include <div64.h> |
| 60 | +#include <bootstage.h> |
| 61 | +#include <asm/global_data.h> |
| 62 | + |
| 63 | +DECLARE_GLOBAL_DATA_PTR; |
| 64 | + |
| 65 | +#define CNTCTLBASE 0x1a020000UL |
| 66 | +#define CNTREADBASE 0x1a030000UL |
| 67 | +#define CNTEN (1 << 0) |
| 68 | +#define CNTFCREQ (1 << 8) |
| 69 | + |
| 70 | +static inline uint32_t mmio_read32(uintptr_t addr) |
| 71 | +{ |
| 72 | + return *(volatile uint32_t*)addr; |
| 73 | +} |
| 74 | + |
| 75 | +static inline void mmio_write32(uintptr_t addr, uint32_t data) |
| 76 | +{ |
| 77 | + *(volatile uint32_t*)addr = data; |
| 78 | +} |
| 79 | + |
| 80 | +int timer_init(void) |
| 81 | +{ |
| 82 | + /* calculate the frequency in ms */ |
| 83 | + gd->arch.timer_rate_hz = COUNTER_FREQUENCY / CONFIG_SYS_HZ; |
| 84 | + |
| 85 | + /* configure CNTFID0 register: set the base frequency */ |
| 86 | + mmio_write32(CNTCTLBASE + 0x20, COUNTER_FREQUENCY); |
| 87 | + |
| 88 | + /* |
| 89 | + * configure CNTCR register: |
| 90 | + * enable the generic counter and; |
| 91 | + * select the first frequency entry |
| 92 | + */ |
| 93 | + mmio_write32(CNTCTLBASE, CNTFCREQ | CNTEN); |
| 94 | + |
| 95 | + return 0; |
| 96 | +} |
| 97 | + |
| 98 | +unsigned long long get_ticks(void) |
| 99 | +{ |
| 100 | + return (((u64)(mmio_read32(CNTREADBASE + 0x4)) << 32) | |
| 101 | + mmio_read32(CNTREADBASE)); |
| 102 | +} |
| 103 | + |
| 104 | +ulong get_timer(ulong base) |
| 105 | +{ |
| 106 | + return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base; |
| 107 | +} |
| 108 | + |
| 109 | +void __udelay(unsigned long usec) |
| 110 | +{ |
| 111 | + unsigned long endtime; |
| 112 | + |
| 113 | + endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz, |
| 114 | + 1000UL); |
| 115 | + |
| 116 | + endtime += get_ticks(); |
| 117 | + |
| 118 | + while (get_ticks() < endtime) |
| 119 | + ; |
| 120 | +} |
| 121 | + |
| 122 | +ulong get_tbclk(void) |
| 123 | +{ |
| 124 | + return gd->arch.timer_rate_hz; |
| 125 | +} |
| 126 | diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt |
Patrick Williams | 864cc43 | 2023-02-09 14:54:44 -0600 | [diff] [blame^] | 127 | index ea71f9d23449..1496d9b88233 100644 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 128 | --- a/scripts/config_whitelist.txt |
| 129 | +++ b/scripts/config_whitelist.txt |
Patrick Williams | 864cc43 | 2023-02-09 14:54:44 -0600 | [diff] [blame^] | 130 | @@ -610,6 +610,7 @@ CONFIG_SYS_MMC_U_BOOT_DST |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 131 | CONFIG_SYS_MMC_U_BOOT_OFFS |
| 132 | CONFIG_SYS_MMC_U_BOOT_SIZE |
| 133 | CONFIG_SYS_MMC_U_BOOT_START |
| 134 | +CONFIG_SYS_MMIO_TIMER |
Patrick Williams | 92b42cb | 2022-09-03 06:53:57 -0500 | [diff] [blame] | 135 | CONFIG_SYS_MOR_VAL |
Patrick Williams | 864cc43 | 2023-02-09 14:54:44 -0600 | [diff] [blame^] | 136 | CONFIG_SYS_MRAM_BASE |
| 137 | CONFIG_SYS_NAND_AMASK |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 138 | -- |
Patrick Williams | 864cc43 | 2023-02-09 14:54:44 -0600 | [diff] [blame^] | 139 | 2.39.1 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 140 | |