Patrick Williams | c124f4f | 2015-09-15 14:41:29 -0500 | [diff] [blame] | 1 | bind: port a patch to fix a build failure |
| 2 | |
| 3 | mips1 does not support ll and sc instructions, and lead to below error, now |
| 4 | we port a patch from debian to fix it |
| 5 | [http://security.debian.org/debian-security/pool/updates/main/b/bind9/bind9_9.8.4.dfsg.P1-6+nmu2+deb7u1.diff.gz] |
| 6 | |
| 7 | | {standard input}: Assembler messages: |
| 8 | | {standard input}:47: Error: Opcode not supported on this processor: mips1 (mips1) `ll $3,0($6)' |
| 9 | | {standard input}:50: Error: Opcode not supported on this processor: mips1 (mips1) `sc $3,0($6)' |
| 10 | |
| 11 | Upstream-Status: Pending |
| 12 | |
| 13 | Signed-off-by: Roy Li <rongqing.li@windriver.com> |
| 14 | |
| 15 | --- bind9-9.8.4.dfsg.P1.orig/lib/isc/mips/include/isc/atomic.h |
| 16 | +++ bind9-9.8.4.dfsg.P1/lib/isc/mips/include/isc/atomic.h |
| 17 | @@ -31,18 +31,20 @@ |
| 18 | isc_atomic_xadd(isc_int32_t *p, int val) { |
| 19 | isc_int32_t orig; |
| 20 | |
| 21 | - /* add is a cheat, since MIPS has no mov instruction */ |
| 22 | - __asm__ volatile ( |
| 23 | - "1:" |
| 24 | - "ll $3, %1\n" |
| 25 | - "add %0, $0, $3\n" |
| 26 | - "add $3, $3, %2\n" |
| 27 | - "sc $3, %1\n" |
| 28 | - "beq $3, 0, 1b" |
| 29 | - : "=&r"(orig) |
| 30 | - : "m"(*p), "r"(val) |
| 31 | - : "memory", "$3" |
| 32 | - ); |
| 33 | + __asm__ __volatile__ ( |
| 34 | + " .set push \n" |
| 35 | + " .set mips2 \n" |
| 36 | + " .set noreorder \n" |
| 37 | + " .set noat \n" |
| 38 | + "1: ll $1, %1 \n" |
| 39 | + " addu %0, $1, %2 \n" |
| 40 | + " sc %0, %1 \n" |
| 41 | + " beqz %0, 1b \n" |
| 42 | + " move %0, $1 \n" |
| 43 | + " .set pop \n" |
| 44 | + : "=&r" (orig), "+R" (*p) |
| 45 | + : "r" (val) |
| 46 | + : "memory"); |
| 47 | |
| 48 | return (orig); |
| 49 | } |
| 50 | @@ -52,16 +54,7 @@ |
| 51 | */ |
| 52 | static inline void |
| 53 | isc_atomic_store(isc_int32_t *p, isc_int32_t val) { |
| 54 | - __asm__ volatile ( |
| 55 | - "1:" |
| 56 | - "ll $3, %0\n" |
| 57 | - "add $3, $0, %1\n" |
| 58 | - "sc $3, %0\n" |
| 59 | - "beq $3, 0, 1b" |
| 60 | - : |
| 61 | - : "m"(*p), "r"(val) |
| 62 | - : "memory", "$3" |
| 63 | - ); |
| 64 | + *p = val; |
| 65 | } |
| 66 | |
| 67 | /* |
| 68 | @@ -72,20 +65,23 @@ |
| 69 | static inline isc_int32_t |
| 70 | isc_atomic_cmpxchg(isc_int32_t *p, int cmpval, int val) { |
| 71 | isc_int32_t orig; |
| 72 | + isc_int32_t tmp; |
| 73 | |
| 74 | - __asm__ volatile( |
| 75 | - "1:" |
| 76 | - "ll $3, %1\n" |
| 77 | - "add %0, $0, $3\n" |
| 78 | - "bne $3, %2, 2f\n" |
| 79 | - "add $3, $0, %3\n" |
| 80 | - "sc $3, %1\n" |
| 81 | - "beq $3, 0, 1b\n" |
| 82 | - "2:" |
| 83 | - : "=&r"(orig) |
| 84 | - : "m"(*p), "r"(cmpval), "r"(val) |
| 85 | - : "memory", "$3" |
| 86 | - ); |
| 87 | + __asm__ __volatile__ ( |
| 88 | + " .set push \n" |
| 89 | + " .set mips2 \n" |
| 90 | + " .set noreorder \n" |
| 91 | + " .set noat \n" |
| 92 | + "1: ll $1, %1 \n" |
| 93 | + " bne $1, %3, 2f \n" |
| 94 | + " move %2, %4 \n" |
| 95 | + " sc %2, %1 \n" |
| 96 | + " beqz %2, 1b \n" |
| 97 | + "2: move %0, $1 \n" |
| 98 | + " .set pop \n" |
| 99 | + : "=&r"(orig), "+R" (*p), "=r" (tmp) |
| 100 | + : "r"(cmpval), "r"(val) |
| 101 | + : "memory"); |
| 102 | |
| 103 | return (orig); |
| 104 | } |