Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame^] | 1 | From a1b8b91a43cfa9dbaa2d907a6d9629da6f93fa3e Mon Sep 17 00:00:00 2001 |
| 2 | From: Emekcan <emekcan.aras@arm.com> |
| 3 | Date: Mon, 12 Sep 2022 15:47:06 +0100 |
| 4 | Subject: [PATCH] Add mhu and rpmsg client to u-boot device tree |
| 5 | |
| 6 | Adds external system controller and mhu driver to u-boot |
| 7 | device tree. This enables communication between host and |
| 8 | the external system. |
| 9 | |
| 10 | Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com> |
| 11 | Upstream-Status: Pending [Not submitted to upstream yet] |
| 12 | --- |
| 13 | arch/arm/dts/corstone1000.dtsi | 50 ++++++++++++++++++++++++++++++++ |
| 14 | 1 file changed, 50 insertions(+) |
| 15 | |
| 16 | diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi |
| 17 | index 19b6e3ea72..61dd6c432c 100644 |
| 18 | --- a/arch/arm/dts/corstone1000.dtsi |
| 19 | +++ b/arch/arm/dts/corstone1000.dtsi |
| 20 | @@ -161,6 +161,56 @@ |
| 21 | status = "disabled"; |
| 22 | }; |
| 23 | |
| 24 | + mbox_es0mhu0_tx: mhu@1b000000 { |
| 25 | + compatible = "arm,mhuv2-tx","arm,primecell"; |
| 26 | + reg = <0x1b000000 0x1000>; |
| 27 | + clocks = <&refclk100mhz>; |
| 28 | + clock-names = "apb_pclk"; |
| 29 | + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| 30 | + #mbox-cells = <2>; |
| 31 | + arm,mhuv2-protocols = <1 1>; |
| 32 | + mbox-name = "arm-es0-mhu0_tx"; |
| 33 | + }; |
| 34 | + |
| 35 | + mbox_es0mhu0_rx: mhu@1b010000 { |
| 36 | + compatible = "arm,mhuv2-rx","arm,primecell"; |
| 37 | + reg = <0x1b010000 0x1000>; |
| 38 | + clocks = <&refclk100mhz>; |
| 39 | + clock-names = "apb_pclk"; |
| 40 | + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| 41 | + #mbox-cells = <2>; |
| 42 | + arm,mhuv2-protocols = <1 1>; |
| 43 | + mbox-name = "arm-es0-mhu0_rx"; |
| 44 | + }; |
| 45 | + |
| 46 | + mbox_es0mhu1_tx: mhu@1b020000 { |
| 47 | + compatible = "arm,mhuv2-tx","arm,primecell"; |
| 48 | + reg = <0x1b020000 0x1000>; |
| 49 | + clocks = <&refclk100mhz>; |
| 50 | + clock-names = "apb_pclk"; |
| 51 | + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| 52 | + #mbox-cells = <2>; |
| 53 | + arm,mhuv2-protocols = <1 1>; |
| 54 | + mbox-name = "arm-es0-mhu1_tx"; |
| 55 | + }; |
| 56 | + |
| 57 | + mbox_es0mhu1_rx: mhu@1b030000 { |
| 58 | + compatible = "arm,mhuv2-rx","arm,primecell"; |
| 59 | + reg = <0x1b030000 0x1000>; |
| 60 | + clocks = <&refclk100mhz>; |
| 61 | + clock-names = "apb_pclk"; |
| 62 | + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
| 63 | + #mbox-cells = <2>; |
| 64 | + arm,mhuv2-protocols = <1 1>; |
| 65 | + mbox-name = "arm-es0-mhu1_rx"; |
| 66 | + }; |
| 67 | + |
| 68 | + client { |
| 69 | + compatible = "arm,client"; |
| 70 | + mboxes = <&mbox_es0mhu0_tx 0 0>, <&mbox_es0mhu1_tx 0 0>, <&mbox_es0mhu0_rx 0 0>, <&mbox_es0mhu1_rx 0 0>; |
| 71 | + mbox-names = "es0mhu0_tx", "es0mhu1_tx", "es0mhu0_rx", "es0mhu1_rx"; |
| 72 | + }; |
| 73 | + |
| 74 | extsys0: extsys@1A010310 { |
| 75 | compatible = "arm,extsys_ctrl"; |
| 76 | reg = <0x1A010310 0x4>, |
| 77 | -- |
| 78 | 2.17.1 |
| 79 | |