Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame^] | 1 | From fa3fd24ffbc987e952a2e5610a7b02556afd2087 Mon Sep 17 00:00:00 2001 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 2 | From: sahil <sahil@arm.com> |
| 3 | Date: Thu, 17 Mar 2022 16:28:05 +0530 |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame^] | 4 | Subject: [PATCH 1/3] Platform/ARM/N1sdp: Add support to parse NT_FW_CONFIG |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 5 | |
| 6 | NT_FW_CONFIG DTB contains platform information passed by |
| 7 | Tf-A boot stage. |
| 8 | This information is used for Virtual memory map generation |
| 9 | during PEI phase and passed on to DXE phase as a HOB, where |
| 10 | it is used in ConfigurationManagerDxe. |
| 11 | |
| 12 | Upstream-Status: Pending |
| 13 | Signed-off-by: Adam Johnston <adam.johnston@arm.com> |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame^] | 14 | Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com> |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 15 | Signed-off-by: sahil <sahil@arm.com> |
| 16 | Change-Id: Ib82571280bf1ca5febe5766e618de09e7b70bb02 |
| 17 | |
| 18 | --- |
| 19 | .../ConfigurationManager.c | 24 ++-- |
| 20 | .../ConfigurationManagerDxe.inf | 3 +- |
| 21 | .../ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 16 +-- |
| 22 | .../Library/PlatformLib/AArch64/Helper.S | 4 +- |
| 23 | .../Library/PlatformLib/PlatformLib.c | 12 +- |
| 24 | .../Library/PlatformLib/PlatformLib.inf | 8 +- |
| 25 | .../Library/PlatformLib/PlatformLibMem.c | 103 +++++++++++++++++- |
| 26 | Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 7 +- |
| 27 | 8 files changed, 152 insertions(+), 25 deletions(-) |
| 28 | |
| 29 | diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame^] | 30 | index f50623ae..e023d47c 100644 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 31 | --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c |
| 32 | +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c |
| 33 | @@ -1,7 +1,7 @@ |
| 34 | /** @file
|
| 35 | Configuration Manager Dxe
|
| 36 |
|
| 37 | - Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
|
| 38 | + Copyright (c) 2021 - 2022, ARM Limited. All rights reserved.<BR>
|
| 39 |
|
| 40 | SPDX-License-Identifier: BSD-2-Clause-Patent
|
| 41 |
|
| 42 | @@ -16,6 +16,7 @@ |
| 43 | #include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
|
| 44 | #include <Library/ArmLib.h>
|
| 45 | #include <Library/DebugLib.h>
|
| 46 | +#include <Library/HobLib.h>
|
| 47 | #include <Library/IoLib.h>
|
| 48 | #include <Library/PcdLib.h>
|
| 49 | #include <Library/UefiBootServicesTableLib.h>
|
| 50 | @@ -28,6 +29,7 @@ |
| 51 | #include "Platform.h"
|
| 52 |
|
| 53 | extern struct EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat;
|
| 54 | +static NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
|
| 55 |
|
| 56 | /** The platform configuration repository information.
|
| 57 | */
|
| 58 | @@ -1242,13 +1244,11 @@ InitializePlatformRepository ( |
| 59 | IN EDKII_PLATFORM_REPOSITORY_INFO * CONST PlatRepoInfo
|
| 60 | )
|
| 61 | {
|
| 62 | - NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
|
| 63 | UINT64 Dram2Size;
|
| 64 | UINT64 RemoteDdrSize;
|
| 65 |
|
| 66 | RemoteDdrSize = 0;
|
| 67 |
|
| 68 | - PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
|
| 69 | Dram2Size = ((PlatInfo->LocalDdrSize - 2) * SIZE_1GB);
|
| 70 |
|
| 71 | PlatRepoInfo->MemAffInfo[LOCAL_DDR_REGION2].Length = Dram2Size;
|
| 72 | @@ -1512,7 +1512,6 @@ GetGicCInfo ( |
| 73 | )
|
| 74 | {
|
| 75 | EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
|
| 76 | - NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
|
| 77 | UINT32 TotalObjCount;
|
| 78 | UINT32 ObjIndex;
|
| 79 |
|
| 80 | @@ -1523,7 +1522,6 @@ GetGicCInfo ( |
| 81 | }
|
| 82 |
|
| 83 | PlatformRepo = This->PlatRepoInfo;
|
| 84 | - PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
|
| 85 |
|
| 86 | if (PlatInfo->MultichipMode == 1) {
|
| 87 | TotalObjCount = PLAT_CPU_COUNT * 2;
|
| 88 | @@ -1623,7 +1621,6 @@ GetStandardNameSpaceObject ( |
| 89 | {
|
| 90 | EFI_STATUS Status;
|
| 91 | EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
|
| 92 | - NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
|
| 93 | UINT32 AcpiTableCount;
|
| 94 |
|
| 95 | if ((This == NULL) || (CmObject == NULL)) {
|
| 96 | @@ -1634,7 +1631,7 @@ GetStandardNameSpaceObject ( |
| 97 |
|
| 98 | Status = EFI_NOT_FOUND;
|
| 99 | PlatformRepo = This->PlatRepoInfo;
|
| 100 | - PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
|
| 101 | +
|
| 102 | AcpiTableCount = ARRAY_SIZE (PlatformRepo->CmAcpiTableList);
|
| 103 | if (PlatInfo->MultichipMode == 0)
|
| 104 | AcpiTableCount -= 1;
|
| 105 | @@ -1697,7 +1694,6 @@ GetArmNameSpaceObject ( |
| 106 | {
|
| 107 | EFI_STATUS Status;
|
| 108 | EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
|
| 109 | - NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
|
| 110 | UINT32 GicRedistCount;
|
| 111 | UINT32 GicCpuCount;
|
| 112 | UINT32 ProcHierarchyInfoCount;
|
| 113 | @@ -1718,8 +1714,6 @@ GetArmNameSpaceObject ( |
| 114 | Status = EFI_NOT_FOUND;
|
| 115 | PlatformRepo = This->PlatRepoInfo;
|
| 116 |
|
| 117 | - // Probe for multi chip information
|
| 118 | - PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
|
| 119 | if (PlatInfo->MultichipMode == 1) {
|
| 120 | GicRedistCount = 2;
|
| 121 | GicCpuCount = PLAT_CPU_COUNT * 2;
|
| 122 | @@ -2162,8 +2156,18 @@ ConfigurationManagerDxeInitialize ( |
| 123 | IN EFI_SYSTEM_TABLE * SystemTable
|
| 124 | )
|
| 125 | {
|
| 126 | + VOID *PlatInfoHob;
|
| 127 | EFI_STATUS Status;
|
| 128 |
|
| 129 | + PlatInfoHob = GetFirstGuidHob (&gArmNeoverseN1SocPlatformInfoDescriptorGuid);
|
| 130 | +
|
| 131 | + if (PlatInfoHob == NULL) {
|
| 132 | + DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n"));
|
| 133 | + return EFI_NOT_FOUND;
|
| 134 | + }
|
| 135 | +
|
| 136 | + PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)GET_GUID_HOB_DATA (PlatInfoHob);
|
| 137 | +
|
| 138 | // Initialize the Platform Configuration Repository before installing the
|
| 139 | // Configuration Manager Protocol
|
| 140 | Status = InitializePlatformRepository (
|
| 141 | diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame^] | 142 | index 4f8e7f13..fb59c295 100644 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 143 | --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf |
| 144 | +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf |
| 145 | @@ -1,7 +1,7 @@ |
| 146 | ## @file
|
| 147 | # Configuration Manager Dxe
|
| 148 | #
|
| 149 | -# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
|
| 150 | +# Copyright (c) 2021 - 2022, ARM Limited. All rights reserved.<BR>
|
| 151 | #
|
| 152 | # SPDX-License-Identifier: BSD-2-Clause-Patent
|
| 153 | #
|
| 154 | @@ -42,6 +42,7 @@ |
| 155 |
|
| 156 | [LibraryClasses]
|
| 157 | ArmPlatformLib
|
| 158 | + HobLib
|
| 159 | PrintLib
|
| 160 | UefiBootServicesTableLib
|
| 161 | UefiDriverEntryPoint
|
| 162 | diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame^] | 163 | index 097160c7..63cebaf0 100644 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 164 | --- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h |
| 165 | +++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h |
| 166 | @@ -1,6 +1,6 @@ |
| 167 | /** @file
|
| 168 | *
|
| 169 | -* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
|
| 170 | +* Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.
|
| 171 | *
|
| 172 | * SPDX-License-Identifier: BSD-2-Clause-Patent
|
| 173 | *
|
| 174 | @@ -41,11 +41,6 @@ |
| 175 | #define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000
|
| 176 | #define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000
|
| 177 |
|
| 178 | -// Base address to a structure of type NEOVERSEN1SOC_PLAT_INFO which is
|
| 179 | -// pre-populated by a earlier boot stage
|
| 180 | -#define NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE (NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + \
|
| 181 | - 0x00008000)
|
| 182 | -
|
| 183 | /*
|
| 184 | * Platform information structure stored in Non-secure SRAM. Platform
|
| 185 | * information are passed from the trusted firmware with the below structure
|
| 186 | @@ -55,12 +50,17 @@ |
| 187 | typedef struct {
|
| 188 | /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */
|
| 189 | UINT8 MultichipMode;
|
| 190 | - /*! Slave count in C2C mode */
|
| 191 | - UINT8 SlaveCount;
|
| 192 | + /*! Secondary chip count in C2C mode */
|
| 193 | + UINT8 SecondaryChipCount;
|
| 194 | /*! Local DDR memory size in GigaBytes */
|
| 195 | UINT8 LocalDdrSize;
|
| 196 | /*! Remote DDR memory size in GigaBytes */
|
| 197 | UINT8 RemoteDdrSize;
|
| 198 | } NEOVERSEN1SOC_PLAT_INFO;
|
| 199 |
|
| 200 | +// NT_FW_CONFIG DT structure
|
| 201 | +typedef struct {
|
| 202 | + UINT64 NtFwConfigDtAddr;
|
| 203 | +} NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI;
|
| 204 | +
|
| 205 | #endif
|
| 206 | diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame^] | 207 | index 8d2069de..88ed640d 100644 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 208 | --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S |
| 209 | +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S |
| 210 | @@ -1,6 +1,6 @@ |
| 211 | /** @file
|
| 212 | *
|
| 213 | -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
|
| 214 | +* Copyright (c) 2019 - 2022, ARM Limited. All rights reserved.
|
| 215 | *
|
| 216 | * SPDX-License-Identifier: BSD-2-Clause-Patent
|
| 217 | *
|
| 218 | @@ -25,6 +25,8 @@ GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) |
| 219 | // the UEFI firmware through the CPU registers.
|
| 220 | //
|
| 221 | ASM_PFX(ArmPlatformPeiBootAction):
|
| 222 | + adr x10, NtFwConfigDtBlob
|
| 223 | + str x0, [x10]
|
| 224 | ret
|
| 225 |
|
| 226 | //
|
| 227 | diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame^] | 228 | index c0effd37..fabe902c 100644 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 229 | --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c |
| 230 | +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c |
| 231 | @@ -1,6 +1,6 @@ |
| 232 | /** @file
|
| 233 |
|
| 234 | - Copyright (c) 2018-2021, ARM Limited. All rights reserved.<BR>
|
| 235 | + Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.<BR>
|
| 236 |
|
| 237 | SPDX-License-Identifier: BSD-2-Clause-Patent
|
| 238 |
|
| 239 | @@ -8,8 +8,12 @@ |
| 240 |
|
| 241 | #include <Library/ArmPlatformLib.h>
|
| 242 | #include <Library/BaseLib.h>
|
| 243 | +#include <NeoverseN1Soc.h>
|
| 244 | #include <Ppi/ArmMpCoreInfo.h>
|
| 245 |
|
| 246 | +UINT64 NtFwConfigDtBlob;
|
| 247 | +STATIC NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI mNtFwConfigDtInfoPpi;
|
| 248 | +
|
| 249 | STATIC ARM_CORE_INFO mCoreInfoTable[] = {
|
| 250 | { 0x0, 0x0 }, // Cluster 0, Core 0
|
| 251 | { 0x0, 0x1 }, // Cluster 0, Core 1
|
| 252 | @@ -46,6 +50,7 @@ ArmPlatformInitialize ( |
| 253 | IN UINTN MpId
|
| 254 | )
|
| 255 | {
|
| 256 | + mNtFwConfigDtInfoPpi.NtFwConfigDtAddr = NtFwConfigDtBlob;
|
| 257 | return RETURN_SUCCESS;
|
| 258 | }
|
| 259 |
|
| 260 | @@ -80,6 +85,11 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { |
| 261 | EFI_PEI_PPI_DESCRIPTOR_PPI,
|
| 262 | &gArmMpCoreInfoPpiGuid,
|
| 263 | &mMpCoreInfoPpi
|
| 264 | + },
|
| 265 | + {
|
| 266 | + EFI_PEI_PPI_DESCRIPTOR_PPI,
|
| 267 | + &gNtFwConfigDtInfoPpiGuid,
|
| 268 | + &mNtFwConfigDtInfoPpi
|
| 269 | }
|
| 270 | };
|
| 271 |
|
| 272 | diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame^] | 273 | index 96e590cd..6f9c9d5a 100644 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 274 | --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf |
| 275 | +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf |
| 276 | @@ -1,7 +1,7 @@ |
| 277 | ## @file
|
| 278 | # Platform Library for N1Sdp.
|
| 279 | #
|
| 280 | -# Copyright (c) 2018-2021, ARM Limited. All rights reserved.<BR>
|
| 281 | +# Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.<BR>
|
| 282 | #
|
| 283 | # SPDX-License-Identifier: BSD-2-Clause-Patent
|
| 284 | #
|
| 285 | @@ -18,10 +18,14 @@ |
| 286 | [Packages]
|
| 287 | ArmPkg/ArmPkg.dec
|
| 288 | ArmPlatformPkg/ArmPlatformPkg.dec
|
| 289 | + EmbeddedPkg/EmbeddedPkg.dec
|
| 290 | MdeModulePkg/MdeModulePkg.dec
|
| 291 | MdePkg/MdePkg.dec
|
| 292 | Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
|
| 293 |
|
| 294 | +[LibraryClasses]
|
| 295 | + FdtLib
|
| 296 | +
|
| 297 | [Sources.common]
|
| 298 | PlatformLibMem.c
|
| 299 | PlatformLib.c
|
| 300 | @@ -59,7 +63,9 @@ |
| 301 | gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
|
| 302 |
|
| 303 | [Guids]
|
| 304 | + gArmNeoverseN1SocPlatformInfoDescriptorGuid
|
| 305 | gEfiHobListGuid ## CONSUMES ## SystemTable
|
| 306 |
|
| 307 | [Ppis]
|
| 308 | gArmMpCoreInfoPpiGuid
|
| 309 | + gNtFwConfigDtInfoPpiGuid
|
| 310 | diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame^] | 311 | index 339fa07b..b58bda4b 100644 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 312 | --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c |
| 313 | +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c |
| 314 | @@ -1,6 +1,6 @@ |
| 315 | /** @file
|
| 316 |
|
| 317 | - Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
|
| 318 | + Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.<BR>
|
| 319 |
|
| 320 | SPDX-License-Identifier: BSD-2-Clause-Patent
|
| 321 |
|
| 322 | @@ -10,11 +10,95 @@ |
| 323 | #include <Library/DebugLib.h>
|
| 324 | #include <Library/HobLib.h>
|
| 325 | #include <Library/MemoryAllocationLib.h>
|
| 326 | +#include <Library/PeiServicesLib.h>
|
| 327 | +#include <libfdt.h>
|
| 328 | #include <NeoverseN1Soc.h>
|
| 329 |
|
| 330 | // The total number of descriptors, including the final "end-of-table" descriptor.
|
| 331 | #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19
|
| 332 |
|
| 333 | +/** A helper function to locate the NtFwConfig PPI and get the base address of
|
| 334 | + NT_FW_CONFIG DT from which values are obtained using FDT helper functions.
|
| 335 | +
|
| 336 | + @param [out] plat_info Pointer to the NeoverseN1Soc PLATFORM_INFO HOB
|
| 337 | +
|
| 338 | + @retval EFI_SUCCESS Success.
|
| 339 | + returns EFI_INVALID_PARAMETER A parameter is invalid.
|
| 340 | +**/
|
| 341 | +EFI_STATUS
|
| 342 | +GetNeoverseN1SocPlatInfo (
|
| 343 | + OUT NEOVERSEN1SOC_PLAT_INFO *plat_info
|
| 344 | + )
|
| 345 | +{
|
| 346 | + CONST UINT32 *Property;
|
| 347 | + INT32 Offset;
|
| 348 | + CONST VOID *NtFwCfgDtBlob;
|
| 349 | + NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI *NtFwConfigInfoPpi;
|
| 350 | + EFI_STATUS Status;
|
| 351 | +
|
| 352 | + Status = PeiServicesLocatePpi (
|
| 353 | + &gNtFwConfigDtInfoPpiGuid,
|
| 354 | + 0,
|
| 355 | + NULL,
|
| 356 | + (VOID **)&NtFwConfigInfoPpi
|
| 357 | + );
|
| 358 | +
|
| 359 | + if (EFI_ERROR (Status)) {
|
| 360 | + DEBUG ((
|
| 361 | + DEBUG_ERROR,
|
| 362 | + "PeiServicesLocatePpi failed with error %r\n",
|
| 363 | + Status
|
| 364 | + ));
|
| 365 | + return EFI_INVALID_PARAMETER;
|
| 366 | + }
|
| 367 | +
|
| 368 | + NtFwCfgDtBlob = (VOID *)(UINTN)NtFwConfigInfoPpi->NtFwConfigDtAddr;
|
| 369 | + if (fdt_check_header (NtFwCfgDtBlob) != 0) {
|
| 370 | + DEBUG ((DEBUG_ERROR, "Invalid DTB file %p passed\n", NtFwCfgDtBlob));
|
| 371 | + return EFI_INVALID_PARAMETER;
|
| 372 | + }
|
| 373 | +
|
| 374 | + Offset = fdt_subnode_offset (NtFwCfgDtBlob, 0, "platform-info");
|
| 375 | + if (Offset == -FDT_ERR_NOTFOUND) {
|
| 376 | + DEBUG ((DEBUG_ERROR, "Invalid DTB : platform-info node not found\n"));
|
| 377 | + return EFI_INVALID_PARAMETER;
|
| 378 | + }
|
| 379 | +
|
| 380 | + Property = fdt_getprop (NtFwCfgDtBlob, Offset, "local-ddr-size", NULL);
|
| 381 | + if (Property == NULL) {
|
| 382 | + DEBUG ((DEBUG_ERROR, "local-ddr-size property not found\n"));
|
| 383 | + return EFI_INVALID_PARAMETER;
|
| 384 | + }
|
| 385 | +
|
| 386 | + plat_info->LocalDdrSize = fdt32_to_cpu (*Property);
|
| 387 | +
|
| 388 | + Property = fdt_getprop (NtFwCfgDtBlob, Offset, "remote-ddr-size", NULL);
|
| 389 | + if (Property == NULL) {
|
| 390 | + DEBUG ((DEBUG_ERROR, "remote-ddr-size property not found\n"));
|
| 391 | + return EFI_INVALID_PARAMETER;
|
| 392 | + }
|
| 393 | +
|
| 394 | + plat_info->RemoteDdrSize = fdt32_to_cpu (*Property);
|
| 395 | +
|
| 396 | + Property = fdt_getprop (NtFwCfgDtBlob, Offset, "secondary-chip-count", NULL);
|
| 397 | + if (Property == NULL) {
|
| 398 | + DEBUG ((DEBUG_ERROR, "secondary-chip-count property not found\n"));
|
| 399 | + return EFI_INVALID_PARAMETER;
|
| 400 | + }
|
| 401 | +
|
| 402 | + plat_info->SecondaryChipCount = fdt32_to_cpu (*Property);
|
| 403 | +
|
| 404 | + Property = fdt_getprop (NtFwCfgDtBlob, Offset, "multichip-mode", NULL);
|
| 405 | + if (Property == NULL) {
|
| 406 | + DEBUG ((DEBUG_ERROR, "multichip-mode property not found\n"));
|
| 407 | + return EFI_INVALID_PARAMETER;
|
| 408 | + }
|
| 409 | +
|
| 410 | + plat_info->MultichipMode = fdt32_to_cpu (*Property);
|
| 411 | +
|
| 412 | + return EFI_SUCCESS;
|
| 413 | +}
|
| 414 | +
|
| 415 | /**
|
| 416 | Returns the Virtual Memory Map of the platform.
|
| 417 |
|
| 418 | @@ -36,9 +120,24 @@ ArmPlatformGetVirtualMemoryMap ( |
| 419 | NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
|
| 420 | UINT64 DramBlock2Size;
|
| 421 | UINT64 RemoteDdrSize;
|
| 422 | + EFI_STATUS Status;
|
| 423 |
|
| 424 | Index = 0;
|
| 425 | - PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
|
| 426 | +
|
| 427 | + // Create platform info HOB
|
| 428 | + PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)BuildGuidHob (
|
| 429 | + &gArmNeoverseN1SocPlatformInfoDescriptorGuid,
|
| 430 | + sizeof (NEOVERSEN1SOC_PLAT_INFO)
|
| 431 | + );
|
| 432 | +
|
| 433 | + if (PlatInfo == NULL) {
|
| 434 | + DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n"));
|
| 435 | + ASSERT (FALSE);
|
| 436 | + return;
|
| 437 | + }
|
| 438 | +
|
| 439 | + Status = GetNeoverseN1SocPlatInfo (PlatInfo);
|
| 440 | + ASSERT (Status == 0);
|
| 441 | DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize -
|
| 442 | NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) *
|
| 443 | (UINT64)SIZE_1GB);
|
| 444 | diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame^] | 445 | index d59f25a5..4dea8fe1 100644 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 446 | --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec |
| 447 | +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec |
| 448 | @@ -1,7 +1,7 @@ |
| 449 | ## @file
|
| 450 | # Describes the entire platform configuration.
|
| 451 | #
|
| 452 | -# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
|
| 453 | +# Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.<BR>
|
| 454 | #
|
| 455 | # SPDX-License-Identifier: BSD-2-Clause-Patent
|
| 456 | #
|
| 457 | @@ -22,6 +22,8 @@ |
| 458 | Include # Root include for the package
|
| 459 |
|
| 460 | [Guids.common]
|
| 461 | + # ARM NeoverseN1Soc Platform Info descriptor
|
| 462 | + gArmNeoverseN1SocPlatformInfoDescriptorGuid = { 0x095cb024, 0x1e00, 0x4d6f, { 0xaa, 0x34, 0x4a, 0xf8, 0xaf, 0x0e, 0xad, 0x99 } }
|
| 463 | gArmNeoverseN1SocTokenSpaceGuid = { 0xab93eb78, 0x60d7, 0x4099, { 0xac, 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } }
|
| 464 |
|
| 465 | [PcdsFixedAtBuild]
|
| 466 | @@ -83,3 +85,6 @@ |
| 467 | gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004F
|
| 468 | gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x00000050
|
| 469 | gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00000051
|
| 470 | +
|
| 471 | +[Ppis]
|
| 472 | + gNtFwConfigDtInfoPpiGuid = { 0xb50dee0e, 0x577f, 0x47fb, { 0x83, 0xd0, 0x41, 0x78, 0x61, 0x8b, 0x33, 0x8a } }
|
| 473 | -- |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame^] | 474 | 2.37.2 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 475 | |