| Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame^] | 1 | From adc66d99663f71ec97313c40b0d00a908f292c30 Mon Sep 17 00:00:00 2001 |
| 2 | From: Himanshu Sharma <Himanshu.Sharma@arm.com> |
| 3 | Date: Mon, 30 May 2022 10:53:30 +0000 |
| 4 | Subject: [PATCH 3/3] Platform/ARM/N1Sdp: Modify the IRQ ID of Debug UART and |
| 5 | routing it to IOFPGA UART1 |
| 6 | |
| 7 | In DBG2 table, IRQ ID was set as 0 for the UART. This overwrote the |
| 8 | IPI0 trigger method to "level", which prevented SGI0 to be enabled |
| 9 | again after a CPU offline/online cycle. |
| 10 | |
| 11 | This patch fixes the above issue by assigning a reserved IRQ ID |
| 12 | for the Debug UART, other than 0 and also routing it to use IOFPGA |
| 13 | UART1 by unsharing it from currently using serial terminal. |
| 14 | |
| 15 | Upstream-Status: Pending |
| 16 | Signed-off-by: Adam Johnston <adam.johnston@arm.com> |
| 17 | Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com> |
| 18 | Signed-off-by: Himanshu Sharma <Himanshu.Sharma@arm.com> |
| 19 | Change-Id: I6640c3c8f77afd233304ce9cb06dcf80a8659c16 |
| 20 | |
| 21 | --- |
| 22 | .../ConfigurationManagerDxe/ConfigurationManager.c | 2 +- |
| 23 | Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 8 ++++---- |
| 24 | 2 files changed, 5 insertions(+), 5 deletions(-) |
| 25 | |
| 26 | diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c |
| 27 | index 36b5fc9e..e8873200 100644 |
| 28 | --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c |
| 29 | +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c |
| 30 | @@ -320,7 +320,7 @@ EDKII_PLATFORM_REPOSITORY_INFO N1sdpRepositoryInfo = { |
| 31 | // Debug Serial Port
|
| 32 | {
|
| 33 | FixedPcdGet64 (PcdSerialDbgRegisterBase), // BaseAddress
|
| 34 | - 0, // Interrupt -unused
|
| 35 | + 250, // Interrupt (reserved)
|
| 36 | FixedPcdGet64 (PcdSerialDbgUartBaudRate), // BaudRate
|
| 37 | FixedPcdGet32 (PcdSerialDbgUartClkInHz), // Clock
|
| 38 | EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART // Port subtype
|
| 39 | diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc |
| 40 | index 865dd04d..878c8f2f 100644 |
| 41 | --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc |
| 42 | +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc |
| 43 | @@ -4,7 +4,7 @@ |
| 44 | # This provides platform specific component descriptions and libraries that
|
| 45 | # conform to EFI/Framework standards.
|
| 46 | #
|
| 47 | -# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
|
| 48 | +# Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.<BR>
|
| 49 | #
|
| 50 | # SPDX-License-Identifier: BSD-2-Clause-Patent
|
| 51 | #
|
| 52 | @@ -136,9 +136,9 @@ |
| 53 | gArmPlatformTokenSpaceGuid.PL011UartInterrupt|95
|
| 54 |
|
| 55 | # PL011 Serial Debug UART (DBG2)
|
| 56 | - gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
|
| 57 | - gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
|
| 58 | - gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|50000000
|
| 59 | + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x1C0A0000
|
| 60 | + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|115200
|
| 61 | + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|24000000
|
| 62 |
|
| 63 | # SBSA Watchdog
|
| 64 | gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93
|
| 65 | -- |
| 66 | 2.37.2 |
| 67 | |