Patrick Williams | 92b42cb | 2022-09-03 06:53:57 -0500 | [diff] [blame^] | 1 | From 8abb9c6a342d750a3a3a66e674c3be6597fc9f66 Mon Sep 17 00:00:00 2001 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 2 | From: Rui Miguel Silva <rui.silva@linaro.org> |
| 3 | Date: Mon, 28 Jun 2021 23:31:25 +0100 |
Patrick Williams | 92b42cb | 2022-09-03 06:53:57 -0500 | [diff] [blame^] | 4 | Subject: [PATCH 04/24] usb: add isp1760 family driver |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 5 | |
| 6 | ISP1760/61/63 are a family of usb controllers, blah, blah, more info |
| 7 | here. |
| 8 | |
| 9 | Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> |
| 10 | --- |
| 11 | Makefile | 1 + |
| 12 | drivers/usb/Kconfig | 2 + |
| 13 | drivers/usb/common/Makefile | 1 + |
| 14 | drivers/usb/isp1760/Kconfig | 12 + |
| 15 | drivers/usb/isp1760/Makefile | 6 + |
| 16 | drivers/usb/isp1760/isp1760-core.c | 378 ++++ |
| 17 | drivers/usb/isp1760/isp1760-core.h | 96 + |
| 18 | drivers/usb/isp1760/isp1760-hcd.c | 2574 +++++++++++++++++++++++++++ |
| 19 | drivers/usb/isp1760/isp1760-hcd.h | 82 + |
| 20 | drivers/usb/isp1760/isp1760-if.c | 127 ++ |
| 21 | drivers/usb/isp1760/isp1760-regs.h | 292 +++ |
| 22 | drivers/usb/isp1760/isp1760-uboot.c | 76 + |
| 23 | drivers/usb/isp1760/isp1760-uboot.h | 27 + |
| 24 | 13 files changed, 3674 insertions(+) |
| 25 | create mode 100644 drivers/usb/isp1760/Kconfig |
| 26 | create mode 100644 drivers/usb/isp1760/Makefile |
| 27 | create mode 100644 drivers/usb/isp1760/isp1760-core.c |
| 28 | create mode 100644 drivers/usb/isp1760/isp1760-core.h |
| 29 | create mode 100644 drivers/usb/isp1760/isp1760-hcd.c |
| 30 | create mode 100644 drivers/usb/isp1760/isp1760-hcd.h |
| 31 | create mode 100644 drivers/usb/isp1760/isp1760-if.c |
| 32 | create mode 100644 drivers/usb/isp1760/isp1760-regs.h |
| 33 | create mode 100644 drivers/usb/isp1760/isp1760-uboot.c |
| 34 | create mode 100644 drivers/usb/isp1760/isp1760-uboot.h |
| 35 | |
| 36 | diff --git a/Makefile b/Makefile |
Patrick Williams | 92b42cb | 2022-09-03 06:53:57 -0500 | [diff] [blame^] | 37 | index 98867fbe06b4..67851020f5c1 100644 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 38 | --- a/Makefile |
| 39 | +++ b/Makefile |
Patrick Williams | 92b42cb | 2022-09-03 06:53:57 -0500 | [diff] [blame^] | 40 | @@ -841,6 +841,7 @@ libs-y += drivers/usb/host/ |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 41 | libs-y += drivers/usb/mtu3/ |
| 42 | libs-y += drivers/usb/musb/ |
| 43 | libs-y += drivers/usb/musb-new/ |
| 44 | +libs-y += drivers/usb/isp1760/ |
| 45 | libs-y += drivers/usb/phy/ |
| 46 | libs-y += drivers/usb/ulpi/ |
| 47 | ifdef CONFIG_POST |
| 48 | diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig |
| 49 | index ab1d061bd0d5..bbe07be02cab 100644 |
| 50 | --- a/drivers/usb/Kconfig |
| 51 | +++ b/drivers/usb/Kconfig |
| 52 | @@ -78,6 +78,8 @@ source "drivers/usb/musb/Kconfig" |
| 53 | |
| 54 | source "drivers/usb/musb-new/Kconfig" |
| 55 | |
| 56 | +source "drivers/usb/isp1760/Kconfig" |
| 57 | + |
| 58 | source "drivers/usb/emul/Kconfig" |
| 59 | |
| 60 | source "drivers/usb/phy/Kconfig" |
| 61 | diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile |
| 62 | index dc05cb0a5077..f08b064d2493 100644 |
| 63 | --- a/drivers/usb/common/Makefile |
| 64 | +++ b/drivers/usb/common/Makefile |
| 65 | @@ -4,6 +4,7 @@ |
| 66 | # |
| 67 | |
| 68 | obj-$(CONFIG_$(SPL_)DM_USB) += common.o |
| 69 | +obj-$(CONFIG_USB_ISP1760) += usb_urb.o |
| 70 | obj-$(CONFIG_USB_MUSB_HCD) += usb_urb.o |
| 71 | obj-$(CONFIG_USB_MUSB_UDC) += usb_urb.o |
| 72 | obj-$(CONFIG_USB_EHCI_FSL) += fsl-dt-fixup.o fsl-errata.o |
| 73 | diff --git a/drivers/usb/isp1760/Kconfig b/drivers/usb/isp1760/Kconfig |
| 74 | new file mode 100644 |
| 75 | index 000000000000..993d71e74cd2 |
| 76 | --- /dev/null |
| 77 | +++ b/drivers/usb/isp1760/Kconfig |
| 78 | @@ -0,0 +1,12 @@ |
| 79 | +# SPDX-License-Identifier: GPL-2.0 |
| 80 | + |
| 81 | +config USB_ISP1760 |
| 82 | + tristate "NXP ISP 1760/1761/1763 support" |
| 83 | + select DM_USB |
| 84 | + select USB_HOST |
| 85 | + help |
| 86 | + Say Y or M here if your system as an ISP1760/1761/1763 USB host |
| 87 | + controller. |
| 88 | + |
| 89 | + This USB controller is usually attached to a non-DMA-Master |
| 90 | + capable bus. |
| 91 | diff --git a/drivers/usb/isp1760/Makefile b/drivers/usb/isp1760/Makefile |
| 92 | new file mode 100644 |
| 93 | index 000000000000..2c809c01b118 |
| 94 | --- /dev/null |
| 95 | +++ b/drivers/usb/isp1760/Makefile |
| 96 | @@ -0,0 +1,6 @@ |
| 97 | +# SPDX-License-Identifier: GPL-2.0 |
| 98 | +isp1760-y := isp1760-core.o isp1760-if.o isp1760-uboot.o isp1760-hcd.o |
| 99 | + |
| 100 | +#isp1760-hcd.o |
| 101 | + |
| 102 | +obj-$(CONFIG_USB_ISP1760) += isp1760.o |
| 103 | diff --git a/drivers/usb/isp1760/isp1760-core.c b/drivers/usb/isp1760/isp1760-core.c |
| 104 | new file mode 100644 |
| 105 | index 000000000000..3080595549c5 |
| 106 | --- /dev/null |
| 107 | +++ b/drivers/usb/isp1760/isp1760-core.c |
| 108 | @@ -0,0 +1,378 @@ |
| 109 | +// SPDX-License-Identifier: GPL-2.0 |
| 110 | +/* |
| 111 | + * Driver for the NXP ISP1760 chip |
| 112 | + * |
| 113 | + * Copyright 2021 Linaro, Rui Miguel Silva <rui.silva@linaro.org> |
| 114 | + * |
| 115 | + * This is based on linux kernel driver, original developed: |
| 116 | + * Copyright 2014 Laurent Pinchart |
| 117 | + * Copyright 2007 Sebastian Siewior |
| 118 | + * |
| 119 | + */ |
| 120 | + |
| 121 | +#include <dm.h> |
| 122 | +#include <dm/device-internal.h> |
| 123 | +#include <dm/device_compat.h> |
| 124 | +#include <dm/devres.h> |
| 125 | +#include <linux/compat.h> |
| 126 | +#include <linux/delay.h> |
| 127 | +#include <linux/io.h> |
| 128 | +#include <linux/kernel.h> |
| 129 | +#include <regmap.h> |
| 130 | +#include <usb.h> |
| 131 | + |
| 132 | +#include "isp1760-core.h" |
| 133 | +#include "isp1760-hcd.h" |
| 134 | +#include "isp1760-regs.h" |
| 135 | + |
| 136 | +#define msleep(a) udelay(a * 1000) |
| 137 | + |
| 138 | +static int isp1760_init_core(struct isp1760_device *isp) |
| 139 | +{ |
| 140 | + struct isp1760_hcd *hcd = &isp->hcd; |
| 141 | + |
| 142 | + /* |
| 143 | + * Reset the host controller, including the CPU interface |
| 144 | + * configuration. |
| 145 | + */ |
| 146 | + isp1760_field_set(hcd->fields, SW_RESET_RESET_ALL); |
| 147 | + msleep(100); |
| 148 | + |
| 149 | + /* Setup HW Mode Control: This assumes a level active-low interrupt */ |
| 150 | + if ((isp->devflags & ISP1760_FLAG_ANALOG_OC) && hcd->is_isp1763) |
| 151 | + return -EINVAL; |
| 152 | + |
| 153 | + if (isp->devflags & ISP1760_FLAG_BUS_WIDTH_16) |
| 154 | + isp1760_field_clear(hcd->fields, HW_DATA_BUS_WIDTH); |
| 155 | + if (isp->devflags & ISP1760_FLAG_BUS_WIDTH_8) |
| 156 | + isp1760_field_set(hcd->fields, HW_DATA_BUS_WIDTH); |
| 157 | + if (isp->devflags & ISP1760_FLAG_ANALOG_OC) |
| 158 | + isp1760_field_set(hcd->fields, HW_ANA_DIGI_OC); |
| 159 | + if (isp->devflags & ISP1760_FLAG_DACK_POL_HIGH) |
| 160 | + isp1760_field_set(hcd->fields, HW_DACK_POL_HIGH); |
| 161 | + if (isp->devflags & ISP1760_FLAG_DREQ_POL_HIGH) |
| 162 | + isp1760_field_set(hcd->fields, HW_DREQ_POL_HIGH); |
| 163 | + if (isp->devflags & ISP1760_FLAG_INTR_POL_HIGH) |
| 164 | + isp1760_field_set(hcd->fields, HW_INTR_HIGH_ACT); |
| 165 | + if (isp->devflags & ISP1760_FLAG_INTR_EDGE_TRIG) |
| 166 | + isp1760_field_set(hcd->fields, HW_INTR_EDGE_TRIG); |
| 167 | + |
| 168 | + /* |
| 169 | + * The ISP1761 has a dedicated DC IRQ line but supports sharing the HC |
| 170 | + * IRQ line for both the host and device controllers. Hardcode IRQ |
| 171 | + * sharing for now and disable the DC interrupts globally to avoid |
| 172 | + * spurious interrupts during HCD registration. |
| 173 | + */ |
| 174 | + if (isp->devflags & ISP1760_FLAG_ISP1761) { |
| 175 | + isp1760_reg_write(hcd->regs, ISP176x_DC_MODE, 0); |
| 176 | + isp1760_field_set(hcd->fields, HW_COMN_IRQ); |
| 177 | + } |
| 178 | + |
| 179 | + /* |
| 180 | + * PORT 1 Control register of the ISP1760 is the OTG control register |
| 181 | + * on ISP1761. |
| 182 | + * |
| 183 | + * TODO: Really support OTG. For now we configure port 1 in device mode |
| 184 | + */ |
| 185 | + if (((isp->devflags & ISP1760_FLAG_ISP1761) || |
| 186 | + (isp->devflags & ISP1760_FLAG_ISP1763)) && |
| 187 | + (isp->devflags & ISP1760_FLAG_PERIPHERAL_EN)) { |
| 188 | + isp1760_field_set(hcd->fields, HW_DM_PULLDOWN); |
| 189 | + isp1760_field_set(hcd->fields, HW_DP_PULLDOWN); |
| 190 | + isp1760_field_set(hcd->fields, HW_OTG_DISABLE); |
| 191 | + } else { |
| 192 | + isp1760_field_set(hcd->fields, HW_SW_SEL_HC_DC); |
| 193 | + isp1760_field_set(hcd->fields, HW_VBUS_DRV); |
| 194 | + isp1760_field_set(hcd->fields, HW_SEL_CP_EXT); |
| 195 | + } |
| 196 | + |
| 197 | + printf( "%s bus width: %u, oc: %s\n", |
| 198 | + hcd->is_isp1763 ? "isp1763" : "isp1760", |
| 199 | + isp->devflags & ISP1760_FLAG_BUS_WIDTH_8 ? 8 : |
| 200 | + isp->devflags & ISP1760_FLAG_BUS_WIDTH_16 ? 16 : 32, |
| 201 | + hcd->is_isp1763 ? "not available" : |
| 202 | + isp->devflags & ISP1760_FLAG_ANALOG_OC ? "analog" : "digital"); |
| 203 | + |
| 204 | + return 0; |
| 205 | +} |
| 206 | + |
| 207 | +void isp1760_set_pullup(struct isp1760_device *isp, bool enable) |
| 208 | +{ |
| 209 | + struct isp1760_hcd *hcd = &isp->hcd; |
| 210 | + |
| 211 | + if (enable) |
| 212 | + isp1760_field_set(hcd->fields, HW_DP_PULLUP); |
| 213 | + else |
| 214 | + isp1760_field_set(hcd->fields, HW_DP_PULLUP_CLEAR); |
| 215 | +} |
| 216 | + |
| 217 | +/* |
| 218 | + * ISP1760/61: |
| 219 | + * |
| 220 | + * 60kb divided in: |
| 221 | + * - 32 blocks @ 256 bytes |
| 222 | + * - 20 blocks @ 1024 bytes |
| 223 | + * - 4 blocks @ 8192 bytes |
| 224 | + */ |
| 225 | +static const struct isp1760_memory_layout isp176x_memory_conf = { |
| 226 | + .blocks[0] = 32, |
| 227 | + .blocks_size[0] = 256, |
| 228 | + .blocks[1] = 20, |
| 229 | + .blocks_size[1] = 1024, |
| 230 | + .blocks[2] = 4, |
| 231 | + .blocks_size[2] = 8192, |
| 232 | + |
| 233 | + .slot_num = 32, |
| 234 | + .payload_blocks = 32 + 20 + 4, |
| 235 | + .payload_area_size = 0xf000, |
| 236 | +}; |
| 237 | + |
| 238 | +/* |
| 239 | + * ISP1763: |
| 240 | + * |
| 241 | + * 20kb divided in: |
| 242 | + * - 8 blocks @ 256 bytes |
| 243 | + * - 2 blocks @ 1024 bytes |
| 244 | + * - 4 blocks @ 4096 bytes |
| 245 | + */ |
| 246 | +static const struct isp1760_memory_layout isp1763_memory_conf = { |
| 247 | + .blocks[0] = 8, |
| 248 | + .blocks_size[0] = 256, |
| 249 | + .blocks[1] = 2, |
| 250 | + .blocks_size[1] = 1024, |
| 251 | + .blocks[2] = 4, |
| 252 | + .blocks_size[2] = 4096, |
| 253 | + |
| 254 | + .slot_num = 16, |
| 255 | + .payload_blocks = 8 + 2 + 4, |
| 256 | + .payload_area_size = 0x5000, |
| 257 | +}; |
| 258 | + |
| 259 | +static const struct regmap_config isp1760_hc_regmap_conf = { |
| 260 | + .width = REGMAP_SIZE_16, |
| 261 | +}; |
| 262 | + |
| 263 | +static const struct reg_field isp1760_hc_reg_fields[] = { |
| 264 | + [HCS_PPC] = REG_FIELD(ISP176x_HC_HCSPARAMS, 4, 4), |
| 265 | + [HCS_N_PORTS] = REG_FIELD(ISP176x_HC_HCSPARAMS, 0, 3), |
| 266 | + [HCC_ISOC_CACHE] = REG_FIELD(ISP176x_HC_HCCPARAMS, 7, 7), |
| 267 | + [HCC_ISOC_THRES] = REG_FIELD(ISP176x_HC_HCCPARAMS, 4, 6), |
| 268 | + [CMD_LRESET] = REG_FIELD(ISP176x_HC_USBCMD, 7, 7), |
| 269 | + [CMD_RESET] = REG_FIELD(ISP176x_HC_USBCMD, 1, 1), |
| 270 | + [CMD_RUN] = REG_FIELD(ISP176x_HC_USBCMD, 0, 0), |
| 271 | + [STS_PCD] = REG_FIELD(ISP176x_HC_USBSTS, 2, 2), |
| 272 | + [HC_FRINDEX] = REG_FIELD(ISP176x_HC_FRINDEX, 0, 13), |
| 273 | + [FLAG_CF] = REG_FIELD(ISP176x_HC_CONFIGFLAG, 0, 0), |
| 274 | + [HC_ISO_PTD_DONEMAP] = REG_FIELD(ISP176x_HC_ISO_PTD_DONEMAP, 0, 31), |
| 275 | + [HC_ISO_PTD_SKIPMAP] = REG_FIELD(ISP176x_HC_ISO_PTD_SKIPMAP, 0, 31), |
| 276 | + [HC_ISO_PTD_LASTPTD] = REG_FIELD(ISP176x_HC_ISO_PTD_LASTPTD, 0, 31), |
| 277 | + [HC_INT_PTD_DONEMAP] = REG_FIELD(ISP176x_HC_INT_PTD_DONEMAP, 0, 31), |
| 278 | + [HC_INT_PTD_SKIPMAP] = REG_FIELD(ISP176x_HC_INT_PTD_SKIPMAP, 0, 31), |
| 279 | + [HC_INT_PTD_LASTPTD] = REG_FIELD(ISP176x_HC_INT_PTD_LASTPTD, 0, 31), |
| 280 | + [HC_ATL_PTD_DONEMAP] = REG_FIELD(ISP176x_HC_ATL_PTD_DONEMAP, 0, 31), |
| 281 | + [HC_ATL_PTD_SKIPMAP] = REG_FIELD(ISP176x_HC_ATL_PTD_SKIPMAP, 0, 31), |
| 282 | + [HC_ATL_PTD_LASTPTD] = REG_FIELD(ISP176x_HC_ATL_PTD_LASTPTD, 0, 31), |
| 283 | + [PORT_OWNER] = REG_FIELD(ISP176x_HC_PORTSC1, 13, 13), |
| 284 | + [PORT_POWER] = REG_FIELD(ISP176x_HC_PORTSC1, 12, 12), |
| 285 | + [PORT_LSTATUS] = REG_FIELD(ISP176x_HC_PORTSC1, 10, 11), |
| 286 | + [PORT_RESET] = REG_FIELD(ISP176x_HC_PORTSC1, 8, 8), |
| 287 | + [PORT_SUSPEND] = REG_FIELD(ISP176x_HC_PORTSC1, 7, 7), |
| 288 | + [PORT_RESUME] = REG_FIELD(ISP176x_HC_PORTSC1, 6, 6), |
| 289 | + [PORT_PE] = REG_FIELD(ISP176x_HC_PORTSC1, 2, 2), |
| 290 | + [PORT_CSC] = REG_FIELD(ISP176x_HC_PORTSC1, 1, 1), |
| 291 | + [PORT_CONNECT] = REG_FIELD(ISP176x_HC_PORTSC1, 0, 0), |
| 292 | + [ALL_ATX_RESET] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 31, 31), |
| 293 | + [HW_ANA_DIGI_OC] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 15, 15), |
| 294 | + [HW_COMN_IRQ] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 10, 10), |
| 295 | + [HW_DATA_BUS_WIDTH] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 8, 8), |
| 296 | + [HW_DACK_POL_HIGH] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 6, 6), |
| 297 | + [HW_DREQ_POL_HIGH] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 5, 5), |
| 298 | + [HW_INTR_HIGH_ACT] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 2, 2), |
| 299 | + [HW_INTR_EDGE_TRIG] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 1, 1), |
| 300 | + [HW_GLOBAL_INTR_EN] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 0, 0), |
| 301 | + [HC_CHIP_REV] = REG_FIELD(ISP176x_HC_CHIP_ID, 16, 31), |
| 302 | + [HC_CHIP_ID_HIGH] = REG_FIELD(ISP176x_HC_CHIP_ID, 8, 15), |
| 303 | + [HC_CHIP_ID_LOW] = REG_FIELD(ISP176x_HC_CHIP_ID, 0, 7), |
| 304 | + [HC_SCRATCH] = REG_FIELD(ISP176x_HC_SCRATCH, 0, 31), |
| 305 | + [SW_RESET_RESET_ALL] = REG_FIELD(ISP176x_HC_RESET, 0, 0), |
| 306 | + [ISO_BUF_FILL] = REG_FIELD(ISP176x_HC_BUFFER_STATUS, 2, 2), |
| 307 | + [INT_BUF_FILL] = REG_FIELD(ISP176x_HC_BUFFER_STATUS, 1, 1), |
| 308 | + [ATL_BUF_FILL] = REG_FIELD(ISP176x_HC_BUFFER_STATUS, 0, 0), |
| 309 | + [MEM_BANK_SEL] = REG_FIELD(ISP176x_HC_MEMORY, 16, 17), |
| 310 | + [MEM_START_ADDR] = REG_FIELD(ISP176x_HC_MEMORY, 0, 15), |
| 311 | + [HC_INTERRUPT] = REG_FIELD(ISP176x_HC_INTERRUPT, 0, 9), |
| 312 | + [HC_ATL_IRQ_ENABLE] = REG_FIELD(ISP176x_HC_INTERRUPT_ENABLE, 8, 8), |
| 313 | + [HC_INT_IRQ_ENABLE] = REG_FIELD(ISP176x_HC_INTERRUPT_ENABLE, 7, 7), |
| 314 | + [HC_ISO_IRQ_MASK_OR] = REG_FIELD(ISP176x_HC_ISO_IRQ_MASK_OR, 0, 31), |
| 315 | + [HC_INT_IRQ_MASK_OR] = REG_FIELD(ISP176x_HC_INT_IRQ_MASK_OR, 0, 31), |
| 316 | + [HC_ATL_IRQ_MASK_OR] = REG_FIELD(ISP176x_HC_ATL_IRQ_MASK_OR, 0, 31), |
| 317 | + [HC_ISO_IRQ_MASK_AND] = REG_FIELD(ISP176x_HC_ISO_IRQ_MASK_AND, 0, 31), |
| 318 | + [HC_INT_IRQ_MASK_AND] = REG_FIELD(ISP176x_HC_INT_IRQ_MASK_AND, 0, 31), |
| 319 | + [HC_ATL_IRQ_MASK_AND] = REG_FIELD(ISP176x_HC_ATL_IRQ_MASK_AND, 0, 31), |
| 320 | + [HW_OTG_DISABLE] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 10, 10), |
| 321 | + [HW_SW_SEL_HC_DC] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 7, 7), |
| 322 | + [HW_VBUS_DRV] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 4, 4), |
| 323 | + [HW_SEL_CP_EXT] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 3, 3), |
| 324 | + [HW_DM_PULLDOWN] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 2, 2), |
| 325 | + [HW_DP_PULLDOWN] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 1, 1), |
| 326 | + [HW_DP_PULLUP] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 0, 0), |
| 327 | + [HW_OTG_DISABLE_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 10, 10), |
| 328 | + [HW_SW_SEL_HC_DC_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 7, 7), |
| 329 | + [HW_VBUS_DRV_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 4, 4), |
| 330 | + [HW_SEL_CP_EXT_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 3, 3), |
| 331 | + [HW_DM_PULLDOWN_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 2, 2), |
| 332 | + [HW_DP_PULLDOWN_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 1, 1), |
| 333 | + [HW_DP_PULLUP_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 0, 0), |
| 334 | +}; |
| 335 | + |
| 336 | +static const struct regmap_config isp1763_hc_regmap_conf = { |
| 337 | + .width = REGMAP_SIZE_16, |
| 338 | +}; |
| 339 | + |
| 340 | +static const struct reg_field isp1763_hc_reg_fields[] = { |
| 341 | + [CMD_LRESET] = REG_FIELD(ISP1763_HC_USBCMD, 7, 7), |
| 342 | + [CMD_RESET] = REG_FIELD(ISP1763_HC_USBCMD, 1, 1), |
| 343 | + [CMD_RUN] = REG_FIELD(ISP1763_HC_USBCMD, 0, 0), |
| 344 | + [STS_PCD] = REG_FIELD(ISP1763_HC_USBSTS, 2, 2), |
| 345 | + [HC_FRINDEX] = REG_FIELD(ISP1763_HC_FRINDEX, 0, 13), |
| 346 | + [FLAG_CF] = REG_FIELD(ISP1763_HC_CONFIGFLAG, 0, 0), |
| 347 | + [HC_ISO_PTD_DONEMAP] = REG_FIELD(ISP1763_HC_ISO_PTD_DONEMAP, 0, 15), |
| 348 | + [HC_ISO_PTD_SKIPMAP] = REG_FIELD(ISP1763_HC_ISO_PTD_SKIPMAP, 0, 15), |
| 349 | + [HC_ISO_PTD_LASTPTD] = REG_FIELD(ISP1763_HC_ISO_PTD_LASTPTD, 0, 15), |
| 350 | + [HC_INT_PTD_DONEMAP] = REG_FIELD(ISP1763_HC_INT_PTD_DONEMAP, 0, 15), |
| 351 | + [HC_INT_PTD_SKIPMAP] = REG_FIELD(ISP1763_HC_INT_PTD_SKIPMAP, 0, 15), |
| 352 | + [HC_INT_PTD_LASTPTD] = REG_FIELD(ISP1763_HC_INT_PTD_LASTPTD, 0, 15), |
| 353 | + [HC_ATL_PTD_DONEMAP] = REG_FIELD(ISP1763_HC_ATL_PTD_DONEMAP, 0, 15), |
| 354 | + [HC_ATL_PTD_SKIPMAP] = REG_FIELD(ISP1763_HC_ATL_PTD_SKIPMAP, 0, 15), |
| 355 | + [HC_ATL_PTD_LASTPTD] = REG_FIELD(ISP1763_HC_ATL_PTD_LASTPTD, 0, 15), |
| 356 | + [PORT_OWNER] = REG_FIELD(ISP1763_HC_PORTSC1, 13, 13), |
| 357 | + [PORT_POWER] = REG_FIELD(ISP1763_HC_PORTSC1, 12, 12), |
| 358 | + [PORT_LSTATUS] = REG_FIELD(ISP1763_HC_PORTSC1, 10, 11), |
| 359 | + [PORT_RESET] = REG_FIELD(ISP1763_HC_PORTSC1, 8, 8), |
| 360 | + [PORT_SUSPEND] = REG_FIELD(ISP1763_HC_PORTSC1, 7, 7), |
| 361 | + [PORT_RESUME] = REG_FIELD(ISP1763_HC_PORTSC1, 6, 6), |
| 362 | + [PORT_PE] = REG_FIELD(ISP1763_HC_PORTSC1, 2, 2), |
| 363 | + [PORT_CSC] = REG_FIELD(ISP1763_HC_PORTSC1, 1, 1), |
| 364 | + [PORT_CONNECT] = REG_FIELD(ISP1763_HC_PORTSC1, 0, 0), |
| 365 | + [HW_DATA_BUS_WIDTH] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 4, 4), |
| 366 | + [HW_DACK_POL_HIGH] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 6, 6), |
| 367 | + [HW_DREQ_POL_HIGH] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 5, 5), |
| 368 | + [HW_INTF_LOCK] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 3, 3), |
| 369 | + [HW_INTR_HIGH_ACT] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 2, 2), |
| 370 | + [HW_INTR_EDGE_TRIG] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 1, 1), |
| 371 | + [HW_GLOBAL_INTR_EN] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 0, 0), |
| 372 | + [SW_RESET_RESET_ATX] = REG_FIELD(ISP1763_HC_RESET, 3, 3), |
| 373 | + [SW_RESET_RESET_ALL] = REG_FIELD(ISP1763_HC_RESET, 0, 0), |
| 374 | + [HC_CHIP_ID_HIGH] = REG_FIELD(ISP1763_HC_CHIP_ID, 0, 15), |
| 375 | + [HC_CHIP_ID_LOW] = REG_FIELD(ISP1763_HC_CHIP_REV, 8, 15), |
| 376 | + [HC_CHIP_REV] = REG_FIELD(ISP1763_HC_CHIP_REV, 0, 7), |
| 377 | + [HC_SCRATCH] = REG_FIELD(ISP1763_HC_SCRATCH, 0, 15), |
| 378 | + [ISO_BUF_FILL] = REG_FIELD(ISP1763_HC_BUFFER_STATUS, 2, 2), |
| 379 | + [INT_BUF_FILL] = REG_FIELD(ISP1763_HC_BUFFER_STATUS, 1, 1), |
| 380 | + [ATL_BUF_FILL] = REG_FIELD(ISP1763_HC_BUFFER_STATUS, 0, 0), |
| 381 | + [MEM_START_ADDR] = REG_FIELD(ISP1763_HC_MEMORY, 0, 15), |
| 382 | + [HC_DATA] = REG_FIELD(ISP1763_HC_DATA, 0, 15), |
| 383 | + [HC_INTERRUPT] = REG_FIELD(ISP1763_HC_INTERRUPT, 0, 10), |
| 384 | + [HC_ATL_IRQ_ENABLE] = REG_FIELD(ISP1763_HC_INTERRUPT_ENABLE, 8, 8), |
| 385 | + [HC_INT_IRQ_ENABLE] = REG_FIELD(ISP1763_HC_INTERRUPT_ENABLE, 7, 7), |
| 386 | + [HC_ISO_IRQ_MASK_OR] = REG_FIELD(ISP1763_HC_ISO_IRQ_MASK_OR, 0, 15), |
| 387 | + [HC_INT_IRQ_MASK_OR] = REG_FIELD(ISP1763_HC_INT_IRQ_MASK_OR, 0, 15), |
| 388 | + [HC_ATL_IRQ_MASK_OR] = REG_FIELD(ISP1763_HC_ATL_IRQ_MASK_OR, 0, 15), |
| 389 | + [HC_ISO_IRQ_MASK_AND] = REG_FIELD(ISP1763_HC_ISO_IRQ_MASK_AND, 0, 15), |
| 390 | + [HC_INT_IRQ_MASK_AND] = REG_FIELD(ISP1763_HC_INT_IRQ_MASK_AND, 0, 15), |
| 391 | + [HC_ATL_IRQ_MASK_AND] = REG_FIELD(ISP1763_HC_ATL_IRQ_MASK_AND, 0, 15), |
| 392 | + [HW_HC_2_DIS] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 15, 15), |
| 393 | + [HW_OTG_DISABLE] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 10, 10), |
| 394 | + [HW_SW_SEL_HC_DC] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 7, 7), |
| 395 | + [HW_VBUS_DRV] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 4, 4), |
| 396 | + [HW_SEL_CP_EXT] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 3, 3), |
| 397 | + [HW_DM_PULLDOWN] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 2, 2), |
| 398 | + [HW_DP_PULLDOWN] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 1, 1), |
| 399 | + [HW_DP_PULLUP] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 0, 0), |
| 400 | + [HW_HC_2_DIS_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 15, 15), |
| 401 | + [HW_OTG_DISABLE_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 10, 10), |
| 402 | + [HW_SW_SEL_HC_DC_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 7, 7), |
| 403 | + [HW_VBUS_DRV_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 4, 4), |
| 404 | + [HW_SEL_CP_EXT_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 3, 3), |
| 405 | + [HW_DM_PULLDOWN_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 2, 2), |
| 406 | + [HW_DP_PULLDOWN_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 1, 1), |
| 407 | + [HW_DP_PULLUP_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 0, 0), |
| 408 | +}; |
| 409 | + |
| 410 | +int isp1760_register(struct isp1760_device *isp, struct resource *mem, int irq, |
| 411 | + unsigned long irqflags) |
| 412 | +{ |
| 413 | + const struct regmap_config *hc_regmap; |
| 414 | + const struct reg_field *hc_reg_fields; |
| 415 | + struct isp1760_hcd *hcd; |
| 416 | + struct regmap_field *f; |
| 417 | + unsigned int devflags; |
| 418 | + struct udevice *dev; |
| 419 | + int ret; |
| 420 | + int i; |
| 421 | + |
| 422 | + hcd = &isp->hcd; |
| 423 | + devflags = isp->devflags; |
| 424 | + dev = isp->dev; |
| 425 | + |
| 426 | + hcd->is_isp1763 = !!(devflags & ISP1760_FLAG_ISP1763); |
| 427 | + |
| 428 | + if (!hcd->is_isp1763 && (devflags & ISP1760_FLAG_BUS_WIDTH_8)) { |
| 429 | + dev_err(dev, "isp1760/61 do not support data width 8\n"); |
| 430 | + return -EINVAL; |
| 431 | + } |
| 432 | + |
| 433 | + if (hcd->is_isp1763) { |
| 434 | + hc_regmap = &isp1763_hc_regmap_conf; |
| 435 | + hc_reg_fields = &isp1763_hc_reg_fields[0]; |
| 436 | + } else { |
| 437 | + hc_regmap = &isp1760_hc_regmap_conf; |
| 438 | + hc_reg_fields = &isp1760_hc_reg_fields[0]; |
| 439 | + } |
| 440 | + |
| 441 | + hcd->base = devm_ioremap(dev, mem->start, resource_size(mem)); |
| 442 | + if (IS_ERR(hcd->base)) |
| 443 | + return PTR_ERR(hcd->base); |
| 444 | + |
| 445 | + hcd->regs = devm_regmap_init(dev, NULL, NULL, hc_regmap); |
| 446 | + if (IS_ERR(hcd->regs)) |
| 447 | + return PTR_ERR(hcd->regs); |
| 448 | + |
| 449 | + for (i = 0; i < HC_FIELD_MAX; i++) { |
| 450 | + f = devm_regmap_field_alloc(dev, hcd->regs, hc_reg_fields[i]); |
| 451 | + if (IS_ERR(f)) |
| 452 | + return PTR_ERR(f); |
| 453 | + |
| 454 | + hcd->fields[i] = f; |
| 455 | + } |
| 456 | + |
| 457 | + if (hcd->is_isp1763) |
| 458 | + hcd->memory_layout = &isp1763_memory_conf; |
| 459 | + else |
| 460 | + hcd->memory_layout = &isp176x_memory_conf; |
| 461 | + |
| 462 | + ret = isp1760_init_core(isp); |
| 463 | + if (ret < 0) |
| 464 | + return ret; |
| 465 | + |
| 466 | + hcd->dev = dev; |
| 467 | + |
| 468 | + ret = isp1760_hcd_register(hcd, mem, irq, irqflags, dev); |
| 469 | + if (ret < 0) |
| 470 | + return ret; |
| 471 | + |
| 472 | + ret = isp1760_hcd_lowlevel_init(hcd); |
| 473 | + if (ret < 0) |
| 474 | + return ret; |
| 475 | + |
| 476 | + dev_set_drvdata(dev, isp); |
| 477 | + |
| 478 | + return 0; |
| 479 | +} |
| 480 | + |
| 481 | +void isp1760_unregister(struct isp1760_device *isp) |
| 482 | +{ |
| 483 | + isp1760_hcd_unregister(&isp->hcd); |
| 484 | + |
| 485 | + return; |
| 486 | +} |
| 487 | diff --git a/drivers/usb/isp1760/isp1760-core.h b/drivers/usb/isp1760/isp1760-core.h |
| 488 | new file mode 100644 |
| 489 | index 000000000000..0a60e30b5fe7 |
| 490 | --- /dev/null |
| 491 | +++ b/drivers/usb/isp1760/isp1760-core.h |
| 492 | @@ -0,0 +1,96 @@ |
| 493 | +/* SPDX-License-Identifier: GPL-2.0 */ |
| 494 | +/* |
| 495 | + * Driver for the NXP ISP1760 chip |
| 496 | + * |
| 497 | + * Copyright 2021 Linaro, Rui Miguel Silva |
| 498 | + * Copyright 2014 Laurent Pinchart |
| 499 | + * Copyright 2007 Sebastian Siewior |
| 500 | + * |
| 501 | + * Contacts: |
| 502 | + * Sebastian Siewior <bigeasy@linutronix.de> |
| 503 | + * Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
| 504 | + * Rui Miguel Silva <rui.silva@linaro.org> |
| 505 | + */ |
| 506 | + |
| 507 | +#ifndef _ISP1760_CORE_H_ |
| 508 | +#define _ISP1760_CORE_H_ |
| 509 | + |
| 510 | +#include <linux/compat.h> |
| 511 | +#include <linux/ioport.h> |
| 512 | +#include <regmap.h> |
| 513 | + |
| 514 | +#include "isp1760-hcd.h" |
| 515 | + |
| 516 | +struct device; |
| 517 | +struct gpio_desc; |
| 518 | + |
| 519 | +/* |
| 520 | + * Device flags that can vary from board to board. All of these |
| 521 | + * indicate the most "atypical" case, so that a devflags of 0 is |
| 522 | + * a sane default configuration. |
| 523 | + */ |
| 524 | +#define ISP1760_FLAG_BUS_WIDTH_16 0x00000002 /* 16-bit data bus width */ |
| 525 | +#define ISP1760_FLAG_PERIPHERAL_EN 0x00000004 /* Port 1 supports Peripheral mode*/ |
| 526 | +#define ISP1760_FLAG_ANALOG_OC 0x00000008 /* Analog overcurrent */ |
| 527 | +#define ISP1760_FLAG_DACK_POL_HIGH 0x00000010 /* DACK active high */ |
| 528 | +#define ISP1760_FLAG_DREQ_POL_HIGH 0x00000020 /* DREQ active high */ |
| 529 | +#define ISP1760_FLAG_ISP1761 0x00000040 /* Chip is ISP1761 */ |
| 530 | +#define ISP1760_FLAG_INTR_POL_HIGH 0x00000080 /* Interrupt polarity active high */ |
| 531 | +#define ISP1760_FLAG_INTR_EDGE_TRIG 0x00000100 /* Interrupt edge triggered */ |
| 532 | +#define ISP1760_FLAG_ISP1763 0x00000200 /* Chip is ISP1763 */ |
| 533 | +#define ISP1760_FLAG_BUS_WIDTH_8 0x00000400 /* 8-bit data bus width */ |
| 534 | + |
| 535 | +struct isp1760_device { |
| 536 | + struct udevice *dev; |
| 537 | + |
| 538 | + unsigned int devflags; |
| 539 | + struct gpio_desc *rst_gpio; |
| 540 | + |
| 541 | + struct isp1760_hcd hcd; |
| 542 | +}; |
| 543 | + |
| 544 | +int isp1760_register(struct isp1760_device *isp, struct resource *mem, int irq, |
| 545 | + unsigned long irqflags); |
| 546 | +void isp1760_unregister(struct isp1760_device *isp); |
| 547 | + |
| 548 | +void isp1760_set_pullup(struct isp1760_device *isp, bool enable); |
| 549 | + |
| 550 | +static inline u32 isp1760_field_read(struct regmap_field **fields, u32 field) |
| 551 | +{ |
| 552 | + unsigned int val; |
| 553 | + |
| 554 | + regmap_field_read(fields[field], &val); |
| 555 | + |
| 556 | + return val; |
| 557 | +} |
| 558 | + |
| 559 | +static inline void isp1760_field_write(struct regmap_field **fields, u32 field, |
| 560 | + u32 val) |
| 561 | +{ |
| 562 | + regmap_field_write(fields[field], val); |
| 563 | +} |
| 564 | + |
| 565 | +static inline void isp1760_field_set(struct regmap_field **fields, u32 field) |
| 566 | +{ |
| 567 | + isp1760_field_write(fields, field, 0xFFFFFFFF); |
| 568 | +} |
| 569 | + |
| 570 | +static inline void isp1760_field_clear(struct regmap_field **fields, u32 field) |
| 571 | +{ |
| 572 | + isp1760_field_write(fields, field, 0); |
| 573 | +} |
| 574 | + |
| 575 | +static inline u32 isp1760_reg_read(struct regmap *regs, u32 reg) |
| 576 | +{ |
| 577 | + unsigned int val; |
| 578 | + |
| 579 | + regmap_read(regs, reg, &val); |
| 580 | + |
| 581 | + return val; |
| 582 | +} |
| 583 | + |
| 584 | +static inline void isp1760_reg_write(struct regmap *regs, u32 reg, u32 val) |
| 585 | +{ |
| 586 | + regmap_write(regs, reg, val); |
| 587 | +} |
| 588 | +#endif |
| 589 | diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c |
| 590 | new file mode 100644 |
| 591 | index 000000000000..b1d86dd69b94 |
| 592 | --- /dev/null |
| 593 | +++ b/drivers/usb/isp1760/isp1760-hcd.c |
| 594 | @@ -0,0 +1,2574 @@ |
| 595 | +// SPDX-License-Identifier: GPL-2.0 |
| 596 | +/* |
| 597 | + * Driver for the NXP ISP1760 chip |
| 598 | + * |
| 599 | + * Copyright 2021 Linaro, Rui Miguel Silva <rui.silva@linaro.org> |
| 600 | + * |
| 601 | + */ |
| 602 | + |
| 603 | +#include <hexdump.h> |
| 604 | +#include <common.h> |
| 605 | +#include <asm/cache.h> |
| 606 | +#include <cpu_func.h> |
| 607 | +#include <dm.h> |
| 608 | +#include <dm/device-internal.h> |
| 609 | +#include <dm/device_compat.h> |
| 610 | +#include <linux/bug.h> |
| 611 | +#include <linux/kernel.h> |
| 612 | +#include <linux/list.h> |
| 613 | +#include <linux/usb/usb_urb_compat.h> |
| 614 | +#include <usb.h> |
| 615 | +#include <linux/io.h> |
| 616 | +#include <linux/iopoll.h> |
| 617 | +#include <asm/unaligned.h> |
| 618 | + |
| 619 | +#include "isp1760-core.h" |
| 620 | +#include "isp1760-hcd.h" |
| 621 | +#include "isp1760-regs.h" |
| 622 | +#include "isp1760-uboot.h" |
| 623 | + |
| 624 | +static struct kmem_cache *qtd_cachep; |
| 625 | +static struct kmem_cache *qh_cachep; |
| 626 | +static struct kmem_cache *urb_listitem_cachep; |
| 627 | + |
| 628 | +typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh, |
| 629 | + struct isp1760_qtd *qtd); |
| 630 | + |
| 631 | +static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) |
| 632 | +{ |
| 633 | + return hcd->hcd_priv; |
| 634 | +} |
| 635 | + |
| 636 | +#define dw_to_le32(x) (cpu_to_le32((__force u32)x)) |
| 637 | +#define le32_to_dw(x) ((__force __dw)(le32_to_cpu(x))) |
| 638 | + |
| 639 | +/* urb state*/ |
| 640 | +#define DELETE_URB (0x0008) |
| 641 | +#define NO_TRANSFER_ACTIVE (0xffffffff) |
| 642 | + |
| 643 | +/* Philips Proprietary Transfer Descriptor (PTD) */ |
| 644 | +typedef __u32 __bitwise __dw; |
| 645 | +struct ptd { |
| 646 | + __dw dw0; |
| 647 | + __dw dw1; |
| 648 | + __dw dw2; |
| 649 | + __dw dw3; |
| 650 | + __dw dw4; |
| 651 | + __dw dw5; |
| 652 | + __dw dw6; |
| 653 | + __dw dw7; |
| 654 | +}; |
| 655 | + |
| 656 | +struct ptd_le32 { |
| 657 | + __le32 dw0; |
| 658 | + __le32 dw1; |
| 659 | + __le32 dw2; |
| 660 | + __le32 dw3; |
| 661 | + __le32 dw4; |
| 662 | + __le32 dw5; |
| 663 | + __le32 dw6; |
| 664 | + __le32 dw7; |
| 665 | +}; |
| 666 | + |
| 667 | +#define PTD_OFFSET 0x0400 |
| 668 | +#define ISO_PTD_OFFSET 0x0400 |
| 669 | +#define INT_PTD_OFFSET 0x0800 |
| 670 | +#define ATL_PTD_OFFSET 0x0c00 |
| 671 | +#define PAYLOAD_OFFSET 0x1000 |
| 672 | + |
| 673 | +#define ISP_BANK_0 0x00 |
| 674 | +#define ISP_BANK_1 0x01 |
| 675 | +#define ISP_BANK_2 0x02 |
| 676 | +#define ISP_BANK_3 0x03 |
| 677 | + |
| 678 | +#define TO_DW(x) ((__force __dw)x) |
| 679 | +#define TO_U32(x) ((__force u32)x) |
| 680 | + |
| 681 | + /* ATL */ |
| 682 | + /* DW0 */ |
| 683 | +#define DW0_VALID_BIT TO_DW(1) |
| 684 | +#define FROM_DW0_VALID(x) (TO_U32(x) & 0x01) |
| 685 | +#define TO_DW0_LENGTH(x) TO_DW((((u32)x) << 3)) |
| 686 | +#define TO_DW0_MAXPACKET(x) TO_DW((((u32)x) << 18)) |
| 687 | +#define TO_DW0_MULTI(x) TO_DW((((u32)x) << 29)) |
| 688 | +#define TO_DW0_ENDPOINT(x) TO_DW((((u32)x) << 31)) |
| 689 | +/* DW1 */ |
| 690 | +#define TO_DW1_DEVICE_ADDR(x) TO_DW((((u32)x) << 3)) |
| 691 | +#define TO_DW1_PID_TOKEN(x) TO_DW((((u32)x) << 10)) |
| 692 | +#define DW1_TRANS_BULK TO_DW(((u32)2 << 12)) |
| 693 | +#define DW1_TRANS_INT TO_DW(((u32)3 << 12)) |
| 694 | +#define DW1_TRANS_SPLIT TO_DW(((u32)1 << 14)) |
| 695 | +#define DW1_SE_USB_LOSPEED TO_DW(((u32)2 << 16)) |
| 696 | +#define TO_DW1_PORT_NUM(x) TO_DW((((u32)x) << 18)) |
| 697 | +#define TO_DW1_HUB_NUM(x) TO_DW((((u32)x) << 25)) |
| 698 | +/* DW2 */ |
| 699 | +#define TO_DW2_DATA_START_ADDR(x) TO_DW((((u32)x) << 8)) |
| 700 | +#define TO_DW2_RL(x) TO_DW(((x) << 25)) |
| 701 | +#define FROM_DW2_RL(x) ((TO_U32(x) >> 25) & 0xf) |
| 702 | +/* DW3 */ |
| 703 | +#define FROM_DW3_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x3fff) |
| 704 | +#define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x07ff) |
| 705 | +#define TO_DW3_NAKCOUNT(x) TO_DW(((x) << 19)) |
| 706 | +#define FROM_DW3_NAKCOUNT(x) ((TO_U32(x) >> 19) & 0xf) |
| 707 | +#define TO_DW3_CERR(x) TO_DW(((x) << 23)) |
| 708 | +#define FROM_DW3_CERR(x) ((TO_U32(x) >> 23) & 0x3) |
| 709 | +#define TO_DW3_DATA_TOGGLE(x) TO_DW(((x) << 25)) |
| 710 | +#define FROM_DW3_DATA_TOGGLE(x) ((TO_U32(x) >> 25) & 0x1) |
| 711 | +#define TO_DW3_PING(x) TO_DW(((x) << 26)) |
| 712 | +#define FROM_DW3_PING(x) ((TO_U32(x) >> 26) & 0x1) |
| 713 | +#define DW3_ERROR_BIT TO_DW((1 << 28)) |
| 714 | +#define DW3_BABBLE_BIT TO_DW((1 << 29)) |
| 715 | +#define DW3_HALT_BIT TO_DW((1 << 30)) |
| 716 | +#define DW3_ACTIVE_BIT TO_DW((1 << 31)) |
| 717 | +#define FROM_DW3_ACTIVE(x) ((TO_U32(x) >> 31) & 0x01) |
| 718 | + |
| 719 | +#define INT_UNDERRUN (1 << 2) |
| 720 | +#define INT_BABBLE (1 << 1) |
| 721 | +#define INT_EXACT (1 << 0) |
| 722 | + |
| 723 | +#define SETUP_PID (2) |
| 724 | +#define IN_PID (1) |
| 725 | +#define OUT_PID (0) |
| 726 | + |
| 727 | +/* Errata 1 */ |
| 728 | +#define RL_COUNTER (0) |
| 729 | +#define NAK_COUNTER (0) |
| 730 | +#define ERR_COUNTER (3) |
| 731 | + |
| 732 | +struct isp1760_qtd { |
| 733 | + u8 packet_type; |
| 734 | + void *data_buffer; |
| 735 | + u32 payload_addr; |
| 736 | + |
| 737 | + /* the rest is HCD-private */ |
| 738 | + struct list_head qtd_list; |
| 739 | + struct urb *urb; |
| 740 | + size_t length; |
| 741 | + size_t actual_length; |
| 742 | + |
| 743 | + /* QTD_ENQUEUED: waiting for transfer (inactive) */ |
| 744 | + /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */ |
| 745 | + /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only |
| 746 | + interrupt handler may touch this qtd! */ |
| 747 | + /* QTD_XFER_COMPLETE: payload has been transferred successfully */ |
| 748 | + /* QTD_RETIRE: transfer error/abort qtd */ |
| 749 | +#define QTD_ENQUEUED 0 |
| 750 | +#define QTD_PAYLOAD_ALLOC 1 |
| 751 | +#define QTD_XFER_STARTED 2 |
| 752 | +#define QTD_XFER_COMPLETE 3 |
| 753 | +#define QTD_RETIRE 4 |
| 754 | + u32 status; |
| 755 | +}; |
| 756 | + |
| 757 | +/* Queue head, one for each active endpoint */ |
| 758 | +struct isp1760_qh { |
| 759 | + struct list_head qh_list; |
| 760 | + struct list_head qtd_list; |
| 761 | + int epnum; |
| 762 | + u32 toggle; |
| 763 | + u32 ping; |
| 764 | + int slot; |
| 765 | + int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */ |
| 766 | +}; |
| 767 | + |
| 768 | +struct urb_listitem { |
| 769 | + struct list_head urb_list; |
| 770 | + struct urb *urb; |
| 771 | +}; |
| 772 | + |
| 773 | +static const u32 isp1763_hc_portsc1_fields[] = { |
| 774 | + [PORT_OWNER] = BIT(13), |
| 775 | + [PORT_POWER] = BIT(12), |
| 776 | + [PORT_LSTATUS] = BIT(10), |
| 777 | + [PORT_RESET] = BIT(8), |
| 778 | + [PORT_SUSPEND] = BIT(7), |
| 779 | + [PORT_RESUME] = BIT(6), |
| 780 | + [PORT_PE] = BIT(2), |
| 781 | + [PORT_CSC] = BIT(1), |
| 782 | + [PORT_CONNECT] = BIT(0), |
| 783 | +}; |
| 784 | + |
| 785 | +static struct descriptor { |
| 786 | + struct usb_device_descriptor device; |
| 787 | + struct usb_config_descriptor config; |
| 788 | + struct usb_interface_descriptor interface; |
| 789 | + struct usb_endpoint_descriptor endpoint; |
| 790 | +} __packed rh_descriptor = { |
| 791 | + { |
| 792 | + /* usb 2.0 root hub device descriptor */ |
| 793 | + 0x12, /* __u8 bLength; */ |
| 794 | + USB_DT_DEVICE, /* __u8 bDescriptorType; Device */ |
| 795 | + 0x0002, /* __le16 bcdUSB; v2.0 */ |
| 796 | + |
| 797 | + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ |
| 798 | + 0x00, /* __u8 bDeviceSubClass; */ |
| 799 | + 0x00, /* __u8 bDeviceProtocol; [ usb 2.0 no TT ] */ |
| 800 | + 0x40, /* __u8 bMaxPacketSize0; 64 Bytes */ |
| 801 | + |
| 802 | + 0x6b1d, /* __le16 idVendor; Linux Foundation 0x1d6b */ |
| 803 | + 0x0200, /* __le16 idProduct; device 0x0002 */ |
| 804 | + 0x0001, /* __le16 bcdDevice */ |
| 805 | + |
| 806 | + 0x03, /* __u8 iManufacturer; */ |
| 807 | + 0x02, /* __u8 iProduct; */ |
| 808 | + 0x01, /* __u8 iSerialNumber; */ |
| 809 | + 0x01 /* __u8 bNumConfigurations; */ |
| 810 | + }, { |
| 811 | + /* one configuration */ |
| 812 | + 0x09, /* __u8 bLength; */ |
| 813 | + USB_DT_CONFIG, /* __u8 bDescriptorType; Configuration */ |
| 814 | + 0x1900, /* __le16 wTotalLength; */ |
| 815 | + 0x01, /* __u8 bNumInterfaces; (1) */ |
| 816 | + 0x01, /* __u8 bConfigurationValue; */ |
| 817 | + 0x00, /* __u8 iConfiguration; */ |
| 818 | + 0xc0, /* __u8 bmAttributes; |
| 819 | + Bit 7: must be set, |
| 820 | + 6: Self-powered, |
| 821 | + 5: Remote wakeup, |
| 822 | + 4..0: resvd */ |
| 823 | + 0x00, /* __u8 MaxPower; */ |
| 824 | + }, { |
| 825 | + /* one interface */ |
| 826 | + 0x09, /* __u8 if_bLength; */ |
| 827 | + USB_DT_INTERFACE, /* __u8 if_bDescriptorType; Interface */ |
| 828 | + 0x00, /* __u8 if_bInterfaceNumber; */ |
| 829 | + 0x00, /* __u8 if_bAlternateSetting; */ |
| 830 | + 0x01, /* __u8 if_bNumEndpoints; */ |
| 831 | + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ |
| 832 | + 0x00, /* __u8 if_bInterfaceSubClass; */ |
| 833 | + 0x00, /* __u8 if_bInterfaceProtocol; [usb1.1 or single tt] */ |
| 834 | + 0x00, /* __u8 if_iInterface; */ |
| 835 | + }, { |
| 836 | + /* one endpoint (status change endpoint) */ |
| 837 | + 0x07, /* __u8 ep_bLength; */ |
| 838 | + USB_DT_ENDPOINT, /* __u8 ep_bDescriptorType; Endpoint */ |
| 839 | + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ |
| 840 | + 0x03, /* __u8 ep_bmAttributes; Interrupt */ |
| 841 | + /* __le16 ep_wMaxPacketSize; 1 + (MAX_ROOT_PORTS / 8) |
| 842 | + * see hub.c:hub_configure() for details. */ |
| 843 | + (USB_MAXCHILDREN + 1 + 7) / 8, 0x00, |
| 844 | + 0x0c /* __u8 ep_bInterval; (256ms -- usb 2.0 spec) */ |
| 845 | + }, |
| 846 | +}; |
| 847 | + |
| 848 | +/* |
| 849 | + * Access functions for isp176x registers regmap fields |
| 850 | + */ |
| 851 | +static u32 isp1760_hcd_read(struct usb_hcd *hcd, u32 field) |
| 852 | +{ |
| 853 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 854 | + |
| 855 | + return isp1760_field_read(priv->fields, field); |
| 856 | +} |
| 857 | + |
| 858 | +/* |
| 859 | + * We need, in isp1763, to write directly the values to the portsc1 |
| 860 | + * register so it will make the other values to trigger. |
| 861 | + */ |
| 862 | +static void isp1760_hcd_portsc1_set_clear(struct isp1760_hcd *priv, u32 field, |
| 863 | + u32 val) |
| 864 | +{ |
| 865 | + u32 bit = isp1763_hc_portsc1_fields[field]; |
| 866 | + u32 port_status = readl(priv->base + ISP1763_HC_PORTSC1); |
| 867 | + |
| 868 | + if (val) |
| 869 | + writel(port_status | bit, priv->base + ISP1763_HC_PORTSC1); |
| 870 | + else |
| 871 | + writel(port_status & ~bit, priv->base + ISP1763_HC_PORTSC1); |
| 872 | +} |
| 873 | + |
| 874 | +static void isp1760_hcd_write(struct usb_hcd *hcd, u32 field, u32 val) |
| 875 | +{ |
| 876 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 877 | + |
| 878 | + if (unlikely(priv->is_isp1763 && |
| 879 | + (field >= PORT_OWNER && field <= PORT_CONNECT))) |
| 880 | + return isp1760_hcd_portsc1_set_clear(priv, field, val); |
| 881 | + |
| 882 | + isp1760_field_write(priv->fields, field, val); |
| 883 | +} |
| 884 | + |
| 885 | +static void isp1760_hcd_set(struct usb_hcd *hcd, u32 field) |
| 886 | +{ |
| 887 | + isp1760_hcd_write(hcd, field, 0xFFFFFFFF); |
| 888 | +} |
| 889 | + |
| 890 | +static void isp1760_hcd_clear(struct usb_hcd *hcd, u32 field) |
| 891 | +{ |
| 892 | + isp1760_hcd_write(hcd, field, 0); |
| 893 | +} |
| 894 | + |
| 895 | +static int isp1760_hcd_set_and_wait(struct usb_hcd *hcd, u32 field, |
| 896 | + u32 timeout_us) |
| 897 | +{ |
| 898 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 899 | + u32 val; |
| 900 | + |
| 901 | + isp1760_hcd_set(hcd, field); |
| 902 | + |
| 903 | + return regmap_field_read_poll_timeout(priv->fields[field], val, |
| 904 | + val, 10, timeout_us); |
| 905 | +} |
| 906 | + |
| 907 | +static int isp1760_hcd_set_and_wait_swap(struct usb_hcd *hcd, u32 field, |
| 908 | + u32 timeout_us) |
| 909 | +{ |
| 910 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 911 | + u32 val; |
| 912 | + |
| 913 | + isp1760_hcd_set(hcd, field); |
| 914 | + |
| 915 | + return regmap_field_read_poll_timeout(priv->fields[field], val, |
| 916 | + !val, 10, timeout_us); |
| 917 | +} |
| 918 | + |
| 919 | +static int isp1760_hcd_clear_and_wait(struct usb_hcd *hcd, u32 field, |
| 920 | + u32 timeout_us) |
| 921 | +{ |
| 922 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 923 | + u32 val; |
| 924 | + |
| 925 | + isp1760_hcd_clear(hcd, field); |
| 926 | + |
| 927 | + return regmap_field_read_poll_timeout(priv->fields[field], val, |
| 928 | + !val, 10, timeout_us); |
| 929 | +} |
| 930 | + |
| 931 | +static bool isp1760_hcd_is_set(struct usb_hcd *hcd, u32 field) |
| 932 | +{ |
| 933 | + return !!isp1760_hcd_read(hcd, field); |
| 934 | +} |
| 935 | + |
| 936 | +static bool isp1760_hcd_ppc_is_set(struct usb_hcd *hcd) |
| 937 | +{ |
| 938 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 939 | + |
| 940 | + if (priv->is_isp1763) |
| 941 | + return true; |
| 942 | + |
| 943 | + return isp1760_hcd_is_set(hcd, HCS_PPC); |
| 944 | +} |
| 945 | + |
| 946 | +static u32 isp1760_hcd_n_ports(struct usb_hcd *hcd) |
| 947 | +{ |
| 948 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 949 | + |
| 950 | + if (priv->is_isp1763) |
| 951 | + return 1; |
| 952 | + |
| 953 | + return isp1760_hcd_read(hcd, HCS_N_PORTS); |
| 954 | +} |
| 955 | + |
| 956 | +/* |
| 957 | + * Access functions for isp176x memory (offset >= 0x0400). |
| 958 | + * |
| 959 | + * bank_reads8() reads memory locations prefetched by an earlier write to |
| 960 | + * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi- |
| 961 | + * bank optimizations, you should use the more generic mem_read() below. |
| 962 | + * |
| 963 | + * For access to ptd memory, use the specialized ptd_read() and ptd_write() |
| 964 | + * below. |
| 965 | + * |
| 966 | + * These functions copy via MMIO data to/from the device. memcpy_{to|from}io() |
| 967 | + * doesn't quite work because some people have to enforce 32-bit access |
| 968 | + */ |
| 969 | +static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, |
| 970 | + __u32 *dst, u32 bytes) |
| 971 | +{ |
| 972 | + __u32 __iomem *src; |
| 973 | + u32 val; |
| 974 | + __u8 *src_byteptr; |
| 975 | + __u8 *dst_byteptr; |
| 976 | + |
| 977 | + src = src_base + (bank_addr | src_offset); |
| 978 | + |
| 979 | + if (src_offset < PAYLOAD_OFFSET) { |
| 980 | + while (bytes >= 4) { |
| 981 | + *dst = readl_relaxed(src); |
| 982 | + bytes -= 4; |
| 983 | + src++; |
| 984 | + dst++; |
| 985 | + } |
| 986 | + } else { |
| 987 | + while (bytes >= 4) { |
| 988 | + *dst = __raw_readl(src); |
| 989 | + bytes -= 4; |
| 990 | + src++; |
| 991 | + dst++; |
| 992 | + } |
| 993 | + } |
| 994 | + |
| 995 | + if (!bytes) |
| 996 | + return; |
| 997 | + |
| 998 | + /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully |
| 999 | + * allocated. |
| 1000 | + */ |
| 1001 | + if (src_offset < PAYLOAD_OFFSET) |
| 1002 | + val = readl_relaxed(src); |
| 1003 | + else |
| 1004 | + val = __raw_readl(src); |
| 1005 | + |
| 1006 | + dst_byteptr = (void *) dst; |
| 1007 | + src_byteptr = (void *) &val; |
| 1008 | + while (bytes > 0) { |
| 1009 | + *dst_byteptr = *src_byteptr; |
| 1010 | + dst_byteptr++; |
| 1011 | + src_byteptr++; |
| 1012 | + bytes--; |
| 1013 | + } |
| 1014 | +} |
| 1015 | + |
| 1016 | +static void isp1760_mem_read(struct usb_hcd *hcd, u32 src_offset, void *dst, |
| 1017 | + u32 bytes) |
| 1018 | +{ |
| 1019 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1020 | + |
| 1021 | + isp1760_hcd_write(hcd, MEM_BANK_SEL, ISP_BANK_0); |
| 1022 | + isp1760_hcd_write(hcd, MEM_START_ADDR, src_offset); |
| 1023 | + ndelay(100); |
| 1024 | + |
| 1025 | + bank_reads8(priv->base, src_offset, ISP_BANK_0, dst, bytes); |
| 1026 | +} |
| 1027 | + |
| 1028 | +/* |
| 1029 | + * ISP1763 does not have the banks direct host controller memory access, |
| 1030 | + * needs to use the HC_DATA register. Add data read/write according to this, |
| 1031 | + * and also adjust 16bit access. |
| 1032 | + */ |
| 1033 | +static void isp1763_mem_read(struct usb_hcd *hcd, u16 srcaddr, |
| 1034 | + u16 *dstptr, u32 bytes) |
| 1035 | +{ |
| 1036 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1037 | + |
| 1038 | + |
| 1039 | + /* Write the starting device address to the hcd memory register */ |
| 1040 | + isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, srcaddr); |
| 1041 | + ndelay(100); /* Delay between consecutive access */ |
| 1042 | + |
| 1043 | + /* As long there are at least 16-bit to read ... */ |
| 1044 | + while (bytes >= 2) { |
| 1045 | + *dstptr = __raw_readw(priv->base + ISP1763_HC_DATA); |
| 1046 | + bytes -= 2; |
| 1047 | + dstptr++; |
| 1048 | + } |
| 1049 | + |
| 1050 | + /* If there are no more bytes to read, return */ |
| 1051 | + if (bytes <= 0) |
| 1052 | + return; |
| 1053 | + |
| 1054 | + *((u8 *)dstptr) = (u8)(readw(priv->base + ISP1763_HC_DATA) & 0xFF); |
| 1055 | +} |
| 1056 | + |
| 1057 | +static void mem_read(struct usb_hcd *hcd, u32 src_offset, __u32 *dst, |
| 1058 | + u32 bytes) |
| 1059 | +{ |
| 1060 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1061 | + |
| 1062 | + if (!priv->is_isp1763) |
| 1063 | + return isp1760_mem_read(hcd, src_offset, (u16 *)dst, bytes); |
| 1064 | + |
| 1065 | + isp1763_mem_read(hcd, (u16)src_offset, (u16 *)dst, bytes); |
| 1066 | +} |
| 1067 | + |
| 1068 | +static void isp1760_mem_write(void __iomem *dst_base, u32 dst_offset, |
| 1069 | + __u32 const *src, u32 bytes) |
| 1070 | +{ |
| 1071 | + __u32 __iomem *dst; |
| 1072 | + |
| 1073 | + dst = dst_base + dst_offset; |
| 1074 | + |
| 1075 | + if (dst_offset < PAYLOAD_OFFSET) { |
| 1076 | + while (bytes >= 4) { |
| 1077 | + writel_relaxed(*src, dst); |
| 1078 | + bytes -= 4; |
| 1079 | + src++; |
| 1080 | + dst++; |
| 1081 | + } |
| 1082 | + } else { |
| 1083 | + while (bytes >= 4) { |
| 1084 | + __raw_writel(*src, dst); |
| 1085 | + bytes -= 4; |
| 1086 | + src++; |
| 1087 | + dst++; |
| 1088 | + } |
| 1089 | + } |
| 1090 | + |
| 1091 | + if (!bytes) |
| 1092 | + return; |
| 1093 | + /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the |
| 1094 | + * extra bytes should not be read by the HW. |
| 1095 | + */ |
| 1096 | + |
| 1097 | + if (dst_offset < PAYLOAD_OFFSET) |
| 1098 | + writel_relaxed(*src, dst); |
| 1099 | + else |
| 1100 | + __raw_writel(*src, dst); |
| 1101 | +} |
| 1102 | + |
| 1103 | +static void isp1763_mem_write(struct usb_hcd *hcd, u16 dstaddr, u16 *src, |
| 1104 | + u32 bytes) |
| 1105 | +{ |
| 1106 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1107 | + |
| 1108 | + /* Write the starting device address to the hcd memory register */ |
| 1109 | + isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, dstaddr); |
| 1110 | + ndelay(100); /* Delay between consecutive access */ |
| 1111 | + |
| 1112 | + while (bytes >= 2) { |
| 1113 | + /* Get and write the data; then adjust the data ptr and len */ |
| 1114 | + __raw_writew(*src, priv->base + ISP1763_HC_DATA); |
| 1115 | + bytes -= 2; |
| 1116 | + src++; |
| 1117 | + } |
| 1118 | + |
| 1119 | + /* If there are no more bytes to process, return */ |
| 1120 | + if (bytes <= 0) |
| 1121 | + return; |
| 1122 | + |
| 1123 | + /* |
| 1124 | + * The only way to get here is if there is a single byte left, |
| 1125 | + * get it and write it to the data reg; |
| 1126 | + */ |
| 1127 | + writew(*((u8 *)src), priv->base + ISP1763_HC_DATA); |
| 1128 | +} |
| 1129 | + |
| 1130 | +static void mem_write(struct usb_hcd *hcd, u32 dst_offset, __u32 *src, |
| 1131 | + u32 bytes) |
| 1132 | +{ |
| 1133 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1134 | + |
| 1135 | + if (!priv->is_isp1763) |
| 1136 | + return isp1760_mem_write(priv->base, dst_offset, src, bytes); |
| 1137 | + |
| 1138 | + isp1763_mem_write(hcd, dst_offset, (u16 *)src, bytes); |
| 1139 | +} |
| 1140 | + |
| 1141 | +/* |
| 1142 | + * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET, |
| 1143 | + * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32. |
| 1144 | + */ |
| 1145 | +static void isp1760_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, |
| 1146 | + struct ptd *ptd) |
| 1147 | +{ |
| 1148 | + u16 src_offset = ptd_offset + slot * sizeof(*ptd); |
| 1149 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1150 | + |
| 1151 | + isp1760_hcd_write(hcd, MEM_BANK_SEL, ISP_BANK_0); |
| 1152 | + isp1760_hcd_write(hcd, MEM_START_ADDR, src_offset); |
| 1153 | + ndelay(90); |
| 1154 | + |
| 1155 | + bank_reads8(priv->base, src_offset, ISP_BANK_0, (void *)ptd, |
| 1156 | + sizeof(*ptd)); |
| 1157 | +} |
| 1158 | + |
| 1159 | +static void isp1763_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, |
| 1160 | + struct ptd *ptd) |
| 1161 | +{ |
| 1162 | + u16 src_offset = ptd_offset + slot * sizeof(*ptd); |
| 1163 | + struct ptd_le32 le32_ptd; |
| 1164 | + |
| 1165 | + isp1763_mem_read(hcd, src_offset, (u16 *)&le32_ptd, sizeof(le32_ptd)); |
| 1166 | + /* Normalize the data obtained */ |
| 1167 | + ptd->dw0 = le32_to_dw(le32_ptd.dw0); |
| 1168 | + ptd->dw1 = le32_to_dw(le32_ptd.dw1); |
| 1169 | + ptd->dw2 = le32_to_dw(le32_ptd.dw2); |
| 1170 | + ptd->dw3 = le32_to_dw(le32_ptd.dw3); |
| 1171 | + ptd->dw4 = le32_to_dw(le32_ptd.dw4); |
| 1172 | + ptd->dw5 = le32_to_dw(le32_ptd.dw5); |
| 1173 | + ptd->dw6 = le32_to_dw(le32_ptd.dw6); |
| 1174 | + ptd->dw7 = le32_to_dw(le32_ptd.dw7); |
| 1175 | +} |
| 1176 | + |
| 1177 | +static void ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, |
| 1178 | + struct ptd *ptd) |
| 1179 | +{ |
| 1180 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1181 | + |
| 1182 | + if (!priv->is_isp1763) |
| 1183 | + return isp1760_ptd_read(hcd, ptd_offset, slot, ptd); |
| 1184 | + |
| 1185 | + isp1763_ptd_read(hcd, ptd_offset, slot, ptd); |
| 1186 | +} |
| 1187 | + |
| 1188 | +static void isp1763_ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, |
| 1189 | + struct ptd *cpu_ptd) |
| 1190 | +{ |
| 1191 | + u16 dst_offset = ptd_offset + slot * sizeof(*cpu_ptd); |
| 1192 | + struct ptd_le32 ptd; |
| 1193 | + |
| 1194 | + ptd.dw0 = dw_to_le32(cpu_ptd->dw0); |
| 1195 | + ptd.dw1 = dw_to_le32(cpu_ptd->dw1); |
| 1196 | + ptd.dw2 = dw_to_le32(cpu_ptd->dw2); |
| 1197 | + ptd.dw3 = dw_to_le32(cpu_ptd->dw3); |
| 1198 | + ptd.dw4 = dw_to_le32(cpu_ptd->dw4); |
| 1199 | + ptd.dw5 = dw_to_le32(cpu_ptd->dw5); |
| 1200 | + ptd.dw6 = dw_to_le32(cpu_ptd->dw6); |
| 1201 | + ptd.dw7 = dw_to_le32(cpu_ptd->dw7); |
| 1202 | + |
| 1203 | + isp1763_mem_write(hcd, dst_offset, (u16 *)&ptd.dw0, |
| 1204 | + 8 * sizeof(ptd.dw0)); |
| 1205 | +} |
| 1206 | + |
| 1207 | +static void isp1760_ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, |
| 1208 | + struct ptd *ptd) |
| 1209 | +{ |
| 1210 | + u32 dst_offset = ptd_offset + slot * sizeof(*ptd); |
| 1211 | + |
| 1212 | + /* |
| 1213 | + * Make sure dw0 gets written last (after other dw's and after payload) |
| 1214 | + * since it contains the enable bit |
| 1215 | + */ |
| 1216 | + isp1760_mem_write(base, dst_offset + sizeof(ptd->dw0), |
| 1217 | + (__force u32 *)&ptd->dw1, 7 * sizeof(ptd->dw1)); |
| 1218 | + wmb(); |
| 1219 | + isp1760_mem_write(base, dst_offset, (__force u32 *)&ptd->dw0, |
| 1220 | + sizeof(ptd->dw0)); |
| 1221 | +} |
| 1222 | + |
| 1223 | +static void ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, |
| 1224 | + struct ptd *ptd) |
| 1225 | +{ |
| 1226 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1227 | + |
| 1228 | + if (!priv->is_isp1763) |
| 1229 | + return isp1760_ptd_write(priv->base, ptd_offset, slot, ptd); |
| 1230 | + |
| 1231 | + isp1763_ptd_write(hcd, ptd_offset, slot, ptd); |
| 1232 | +} |
| 1233 | + |
| 1234 | +/* memory management of the 60kb on the chip from 0x1000 to 0xffff */ |
| 1235 | +static void init_memory(struct isp1760_hcd *priv) |
| 1236 | +{ |
| 1237 | + const struct isp1760_memory_layout *mem = priv->memory_layout; |
| 1238 | + int i, j, curr; |
| 1239 | + u32 payload_addr; |
| 1240 | + |
| 1241 | + payload_addr = PAYLOAD_OFFSET; |
| 1242 | + |
| 1243 | + for (i = 0, curr = 0; i < ARRAY_SIZE(mem->blocks); i++) { |
| 1244 | + for (j = 0; j < mem->blocks[i]; j++, curr++) { |
| 1245 | + priv->memory_pool[curr + j].start = payload_addr; |
| 1246 | + priv->memory_pool[curr + j].size = mem->blocks_size[i]; |
| 1247 | + priv->memory_pool[curr + j].free = 1; |
| 1248 | + payload_addr += priv->memory_pool[curr + j].size; |
| 1249 | + } |
| 1250 | + } |
| 1251 | + |
| 1252 | + WARN_ON(payload_addr - priv->memory_pool[0].start > |
| 1253 | + mem->payload_area_size); |
| 1254 | +} |
| 1255 | + |
| 1256 | +static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) |
| 1257 | +{ |
| 1258 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1259 | + const struct isp1760_memory_layout *mem = priv->memory_layout; |
| 1260 | + int i; |
| 1261 | + |
| 1262 | + WARN_ON(qtd->payload_addr); |
| 1263 | + |
| 1264 | + if (!qtd->length) |
| 1265 | + return; |
| 1266 | + |
| 1267 | + for (i = 0; i < mem->payload_blocks; i++) { |
| 1268 | + if (priv->memory_pool[i].size >= qtd->length && |
| 1269 | + priv->memory_pool[i].free) { |
| 1270 | + priv->memory_pool[i].free = 0; |
| 1271 | + qtd->payload_addr = priv->memory_pool[i].start; |
| 1272 | + return; |
| 1273 | + } |
| 1274 | + } |
| 1275 | +} |
| 1276 | + |
| 1277 | +static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) |
| 1278 | +{ |
| 1279 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1280 | + const struct isp1760_memory_layout *mem = priv->memory_layout; |
| 1281 | + int i; |
| 1282 | + |
| 1283 | + if (!qtd->payload_addr) |
| 1284 | + return; |
| 1285 | + |
| 1286 | + for (i = 0; i < mem->payload_blocks; i++) { |
| 1287 | + if (priv->memory_pool[i].start == qtd->payload_addr) { |
| 1288 | + WARN_ON(priv->memory_pool[i].free); |
| 1289 | + priv->memory_pool[i].free = 1; |
| 1290 | + qtd->payload_addr = 0; |
| 1291 | + return; |
| 1292 | + } |
| 1293 | + } |
| 1294 | + |
| 1295 | + WARN_ON(1); |
| 1296 | + qtd->payload_addr = 0; |
| 1297 | +} |
| 1298 | + |
| 1299 | +/* reset a non-running (STS_HALT == 1) controller */ |
| 1300 | +static int ehci_reset(struct usb_hcd *hcd) |
| 1301 | +{ |
| 1302 | + return isp1760_hcd_set_and_wait_swap(hcd, CMD_RESET, 250 * 1000); |
| 1303 | +} |
| 1304 | + |
| 1305 | +static struct isp1760_qh *qh_alloc(gfp_t flags) |
| 1306 | +{ |
| 1307 | + struct isp1760_qh *qh; |
| 1308 | + |
| 1309 | + qh = kmem_cache_alloc(qh_cachep, flags); |
| 1310 | + if (!qh) |
| 1311 | + return NULL; |
| 1312 | + |
| 1313 | + memset(qh, '\0', qh_cachep->sz); |
| 1314 | + INIT_LIST_HEAD(&qh->qh_list); |
| 1315 | + INIT_LIST_HEAD(&qh->qtd_list); |
| 1316 | + qh->slot = -1; |
| 1317 | + |
| 1318 | + return qh; |
| 1319 | +} |
| 1320 | + |
| 1321 | +static void qh_free(struct isp1760_qh *qh) |
| 1322 | +{ |
| 1323 | + WARN_ON(!list_empty(&qh->qtd_list)); |
| 1324 | + WARN_ON(qh->slot > -1); |
| 1325 | + kmem_cache_free(qh_cachep, qh); |
| 1326 | +} |
| 1327 | + |
| 1328 | +/* one-time init, only for memory state */ |
| 1329 | +static int priv_init(struct usb_hcd *hcd) |
| 1330 | +{ |
| 1331 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1332 | + u32 isoc_cache; |
| 1333 | + u32 isoc_thres; |
| 1334 | + int i; |
| 1335 | + |
| 1336 | + spin_lock_init(&priv->lock); |
| 1337 | + |
| 1338 | + for (i = 0; i < QH_END; i++) |
| 1339 | + INIT_LIST_HEAD(&priv->qh_list[i]); |
| 1340 | + |
| 1341 | + /* |
| 1342 | + * hw default: 1K periodic list heads, one per frame. |
| 1343 | + * periodic_size can shrink by USBCMD update if hcc_params allows. |
| 1344 | + */ |
| 1345 | + priv->periodic_size = DEFAULT_I_TDPS; |
| 1346 | + |
| 1347 | + if (priv->is_isp1763) { |
| 1348 | + priv->i_thresh = 2; |
| 1349 | + return 0; |
| 1350 | + } |
| 1351 | + |
| 1352 | + /* controllers may cache some of the periodic schedule ... */ |
| 1353 | + isoc_cache = isp1760_hcd_read(hcd, HCC_ISOC_CACHE); |
| 1354 | + isoc_thres = isp1760_hcd_read(hcd, HCC_ISOC_THRES); |
| 1355 | + |
| 1356 | + /* full frame cache */ |
| 1357 | + if (isoc_cache) |
| 1358 | + priv->i_thresh = 8; |
| 1359 | + else /* N microframes cached */ |
| 1360 | + priv->i_thresh = 2 + isoc_thres; |
| 1361 | + |
| 1362 | + return 0; |
| 1363 | +} |
| 1364 | + |
| 1365 | +static int isp1760_hc_setup(struct usb_hcd *hcd) |
| 1366 | +{ |
| 1367 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1368 | + u32 atx_reset; |
| 1369 | + int result; |
| 1370 | + u32 scratch; |
| 1371 | + u32 pattern; |
| 1372 | + |
| 1373 | + if (priv->is_isp1763) |
| 1374 | + pattern = 0xcafe; |
| 1375 | + else |
| 1376 | + pattern = 0xdeadcafe; |
| 1377 | + |
| 1378 | + isp1760_hcd_write(hcd, HC_SCRATCH, pattern); |
| 1379 | + |
| 1380 | + /* Change bus pattern */ |
| 1381 | + scratch = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); |
| 1382 | + scratch = isp1760_hcd_read(hcd, HC_SCRATCH); |
| 1383 | + if (scratch != pattern) { |
| 1384 | + printf("Scratch test failed. 0x%08x\n", scratch); |
| 1385 | + return -ENODEV; |
| 1386 | + } |
| 1387 | + |
| 1388 | + /* |
| 1389 | + * The RESET_HC bit in the SW_RESET register is supposed to reset the |
| 1390 | + * host controller without touching the CPU interface registers, but at |
| 1391 | + * least on the ISP1761 it seems to behave as the RESET_ALL bit and |
| 1392 | + * reset the whole device. We thus can't use it here, so let's reset |
| 1393 | + * the host controller through the EHCI USB Command register. The device |
| 1394 | + * has been reset in core code anyway, so this shouldn't matter. |
| 1395 | + */ |
| 1396 | + isp1760_hcd_clear(hcd, ISO_BUF_FILL); |
| 1397 | + isp1760_hcd_clear(hcd, INT_BUF_FILL); |
| 1398 | + isp1760_hcd_clear(hcd, ATL_BUF_FILL); |
| 1399 | + |
| 1400 | + isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); |
| 1401 | + isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); |
| 1402 | + isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); |
| 1403 | + |
| 1404 | + result = ehci_reset(hcd); |
| 1405 | + if (result) |
| 1406 | + return result; |
| 1407 | + |
| 1408 | + /* Step 11 passed */ |
| 1409 | + |
| 1410 | + /* ATL reset */ |
| 1411 | + if (priv->is_isp1763) |
| 1412 | + atx_reset = SW_RESET_RESET_ATX; |
| 1413 | + else |
| 1414 | + atx_reset = ALL_ATX_RESET; |
| 1415 | + |
| 1416 | + isp1760_hcd_set(hcd, atx_reset); |
| 1417 | + mdelay(10); |
| 1418 | + isp1760_hcd_clear(hcd, atx_reset); |
| 1419 | + |
| 1420 | + if (priv->is_isp1763) { |
| 1421 | + isp1760_hcd_set(hcd, HW_OTG_DISABLE); |
| 1422 | + isp1760_hcd_set(hcd, HW_SW_SEL_HC_DC_CLEAR); |
| 1423 | + isp1760_hcd_set(hcd, HW_HC_2_DIS_CLEAR); |
| 1424 | + isp1760_hcd_set(hcd, HW_DM_PULLDOWN); |
| 1425 | + isp1760_hcd_set(hcd, HW_DP_PULLDOWN); |
| 1426 | + mdelay(10); |
| 1427 | + |
| 1428 | + isp1760_hcd_set(hcd, HW_INTF_LOCK); |
| 1429 | + } |
| 1430 | + |
| 1431 | + isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE); |
| 1432 | + isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE); |
| 1433 | + |
| 1434 | + return priv_init(hcd); |
| 1435 | +} |
| 1436 | + |
| 1437 | +static u32 base_to_chip(u32 base) |
| 1438 | +{ |
| 1439 | + return ((base - 0x400) >> 3); |
| 1440 | +} |
| 1441 | + |
| 1442 | +static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh) |
| 1443 | +{ |
| 1444 | + struct urb *urb; |
| 1445 | + |
| 1446 | + if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) |
| 1447 | + return 1; |
| 1448 | + |
| 1449 | + urb = qtd->urb; |
| 1450 | + qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list); |
| 1451 | + |
| 1452 | + return (qtd->urb != urb); |
| 1453 | +} |
| 1454 | + |
| 1455 | +/* magic numbers that can affect system performance */ |
| 1456 | +#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ |
| 1457 | +#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ |
| 1458 | +#define EHCI_TUNE_RL_TT 0 |
| 1459 | +#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ |
| 1460 | +#define EHCI_TUNE_MULT_TT 1 |
| 1461 | +#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ |
| 1462 | + |
| 1463 | +static void create_ptd_atl(struct isp1760_qh *qh, struct isp1760_qtd *qtd, |
| 1464 | + struct ptd *ptd) |
| 1465 | +{ |
| 1466 | + u32 maxpacket; |
| 1467 | + u32 multi; |
| 1468 | + u32 rl = RL_COUNTER; |
| 1469 | + u32 nak = NAK_COUNTER; |
| 1470 | + u8 portnr; |
| 1471 | + u8 hubaddr; |
| 1472 | + |
| 1473 | + memset(ptd, 0, sizeof(*ptd)); |
| 1474 | + |
| 1475 | + /* according to 3.6.2, max packet len can not be > 0x400 */ |
| 1476 | + maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe); |
| 1477 | + multi = 1 + ((maxpacket >> 11) & 0x3); |
| 1478 | + maxpacket &= 0x7ff; |
| 1479 | + |
| 1480 | + /* DW0 */ |
| 1481 | + ptd->dw0 = DW0_VALID_BIT; |
| 1482 | + ptd->dw0 |= TO_DW0_LENGTH(qtd->length); |
| 1483 | + ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket); |
| 1484 | + ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe)); |
| 1485 | + |
| 1486 | + /* DW1 */ |
| 1487 | + ptd->dw1 = TO_DW((usb_pipeendpoint(qtd->urb->pipe) >> 1)); |
| 1488 | + ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe)); |
| 1489 | + ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type); |
| 1490 | + |
| 1491 | + if (usb_pipebulk(qtd->urb->pipe)) |
| 1492 | + ptd->dw1 |= DW1_TRANS_BULK; |
| 1493 | + else if (usb_pipeint(qtd->urb->pipe)) |
| 1494 | + ptd->dw1 |= DW1_TRANS_INT; |
| 1495 | + |
| 1496 | + if (qtd->urb->dev->speed != USB_SPEED_HIGH) { |
| 1497 | + /* split transaction */ |
| 1498 | + |
| 1499 | + ptd->dw1 |= DW1_TRANS_SPLIT; |
| 1500 | + if (qtd->urb->dev->speed == USB_SPEED_LOW) |
| 1501 | + ptd->dw1 |= DW1_SE_USB_LOSPEED; |
| 1502 | + |
| 1503 | + if (!qtd->urb->dev->dev->parent_priv_) { |
| 1504 | + portnr = qtd->urb->dev->portnr; |
| 1505 | + hubaddr = qtd->urb->dev->devnum; |
| 1506 | + } else { |
| 1507 | + usb_find_usb2_hub_address_port(qtd->urb->dev, &hubaddr, |
| 1508 | + &portnr); |
| 1509 | + } |
| 1510 | + |
| 1511 | + ptd->dw1 |= TO_DW1_PORT_NUM(portnr); |
| 1512 | + ptd->dw1 |= TO_DW1_HUB_NUM(hubaddr); |
| 1513 | + |
| 1514 | + /* SE bit for Split INT transfers */ |
| 1515 | + if (usb_pipeint(qtd->urb->pipe) && |
| 1516 | + (qtd->urb->dev->speed == USB_SPEED_LOW)) |
| 1517 | + ptd->dw1 |= DW1_SE_USB_LOSPEED; |
| 1518 | + |
| 1519 | + rl = 0; |
| 1520 | + nak = 0; |
| 1521 | + } else { |
| 1522 | + ptd->dw0 |= TO_DW0_MULTI(multi); |
| 1523 | + if (usb_pipecontrol(qtd->urb->pipe) || |
| 1524 | + usb_pipebulk(qtd->urb->pipe)) |
| 1525 | + ptd->dw3 |= TO_DW3_PING(qh->ping); |
| 1526 | + } |
| 1527 | + /* DW2 */ |
| 1528 | + ptd->dw2 = 0; |
| 1529 | + ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr)); |
| 1530 | + ptd->dw2 |= TO_DW2_RL(rl); |
| 1531 | + |
| 1532 | + /* DW3 */ |
| 1533 | + ptd->dw3 |= TO_DW3_NAKCOUNT(nak); |
| 1534 | + ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle); |
| 1535 | + |
| 1536 | + if (usb_pipecontrol(qtd->urb->pipe)) { |
| 1537 | + if (qtd->data_buffer == qtd->urb->setup_packet) { |
| 1538 | + ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1); |
| 1539 | + } else if (last_qtd_of_urb(qtd, qh)) { |
| 1540 | + ptd->dw3 |= TO_DW3_DATA_TOGGLE(1); |
| 1541 | + } |
| 1542 | + } |
| 1543 | + |
| 1544 | + ptd->dw3 |= DW3_ACTIVE_BIT; |
| 1545 | + /* Cerr */ |
| 1546 | + ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER); |
| 1547 | +} |
| 1548 | + |
| 1549 | +static void transform_add_int(struct isp1760_qh *qh, struct isp1760_qtd *qtd, |
| 1550 | + struct ptd *ptd) |
| 1551 | +{ |
| 1552 | + struct usb_host_endpoint *hep = qtd->urb->ep; |
| 1553 | + struct usb_endpoint_descriptor *epd = &hep->desc; |
| 1554 | + u32 usof; |
| 1555 | + u32 period; |
| 1556 | + |
| 1557 | + /* |
| 1558 | + * Most of this is guessing. ISP1761 datasheet is quite unclear, and |
| 1559 | + * the algorithm from the original Philips driver code, which was |
| 1560 | + * pretty much used in this driver before as well, is quite horrendous |
| 1561 | + * and, i believe, incorrect. The code below follows the datasheet and |
| 1562 | + * USB2.0 spec as far as I can tell, and plug/unplug seems to be much |
| 1563 | + * more reliable this way (fingers crossed...). |
| 1564 | + */ |
| 1565 | + |
| 1566 | + if (qtd->urb->dev->speed == USB_SPEED_HIGH) { |
| 1567 | + /* urb->interval is in units of microframes (1/8 ms) */ |
| 1568 | + period = epd->bInterval >> 3; |
| 1569 | + |
| 1570 | + if (epd->bInterval > 4) |
| 1571 | + usof = 0x01; /* One bit set => |
| 1572 | + interval 1 ms * uFrame-match */ |
| 1573 | + else if (epd->bInterval > 2) |
| 1574 | + usof = 0x22; /* Two bits set => interval 1/2 ms */ |
| 1575 | + else if (epd->bInterval > 1) |
| 1576 | + usof = 0x55; /* Four bits set => interval 1/4 ms */ |
| 1577 | + else |
| 1578 | + usof = 0xff; /* All bits set => interval 1/8 ms */ |
| 1579 | + } else { |
| 1580 | + /* urb->interval is in units of frames (1 ms) */ |
| 1581 | + period = epd->bInterval; |
| 1582 | + usof = 0x0f; /* Execute Start Split on any of the |
| 1583 | + four first uFrames */ |
| 1584 | + |
| 1585 | + /* |
| 1586 | + * First 8 bits in dw5 is uSCS and "specifies which uSOF the |
| 1587 | + * complete split needs to be sent. Valid only for IN." Also, |
| 1588 | + * "All bits can be set to one for every transfer." (p 82, |
| 1589 | + * ISP1761 data sheet.) 0x1c is from Philips driver. Where did |
| 1590 | + * that number come from? 0xff seems to work fine... |
| 1591 | + */ |
| 1592 | + /* ptd->dw5 = 0x1c; */ |
| 1593 | + ptd->dw5 = TO_DW(0xff); /* Execute Complete Split on any uFrame */ |
| 1594 | + } |
| 1595 | + |
| 1596 | + period = period >> 1;/* Ensure equal or shorter period than requested */ |
| 1597 | + period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */ |
| 1598 | + |
| 1599 | + ptd->dw2 |= TO_DW(period); |
| 1600 | + ptd->dw4 = TO_DW(usof); |
| 1601 | +} |
| 1602 | + |
| 1603 | +static void create_ptd_int(struct isp1760_qh *qh, struct isp1760_qtd *qtd, |
| 1604 | + struct ptd *ptd) |
| 1605 | +{ |
| 1606 | + create_ptd_atl(qh, qtd, ptd); |
| 1607 | + transform_add_int(qh, qtd, ptd); |
| 1608 | +} |
| 1609 | + |
| 1610 | +static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb) |
| 1611 | +{ |
| 1612 | + if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { |
| 1613 | + void *ptr; |
| 1614 | + for (ptr = urb->transfer_buffer; |
| 1615 | + ptr < urb->transfer_buffer + urb->transfer_buffer_length; |
| 1616 | + ptr += PAGE_SIZE) |
| 1617 | + flush_dcache_range((unsigned long)ptr, |
| 1618 | + (unsigned long)ptr + PAGE_SIZE); |
| 1619 | + } |
| 1620 | + |
| 1621 | + /* complete() can reenter this HCD */ |
| 1622 | + usb_hcd_unlink_urb_from_ep(hcd, urb); |
| 1623 | + usb_hcd_giveback_urb(hcd, urb, urb->status); |
| 1624 | +} |
| 1625 | + |
| 1626 | +static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb, |
| 1627 | + u8 packet_type) |
| 1628 | +{ |
| 1629 | + struct isp1760_qtd *qtd; |
| 1630 | + |
| 1631 | + qtd = kmem_cache_alloc(qtd_cachep, flags); |
| 1632 | + if (!qtd) |
| 1633 | + return NULL; |
| 1634 | + |
| 1635 | + memset(qtd, '\0', sizeof(*qtd)); |
| 1636 | + INIT_LIST_HEAD(&qtd->qtd_list); |
| 1637 | + qtd->urb = urb; |
| 1638 | + qtd->packet_type = packet_type; |
| 1639 | + qtd->status = QTD_ENQUEUED; |
| 1640 | + qtd->actual_length = 0; |
| 1641 | + |
| 1642 | + return qtd; |
| 1643 | +} |
| 1644 | + |
| 1645 | +static void qtd_free(struct isp1760_qtd *qtd) |
| 1646 | +{ |
| 1647 | + WARN_ON(qtd->payload_addr); |
| 1648 | + kmem_cache_free(qtd_cachep, qtd); |
| 1649 | +} |
| 1650 | + |
| 1651 | +static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot, |
| 1652 | + struct isp1760_slotinfo *slots, |
| 1653 | + struct isp1760_qtd *qtd, struct isp1760_qh *qh, |
| 1654 | + struct ptd *ptd) |
| 1655 | +{ |
| 1656 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1657 | + const struct isp1760_memory_layout *mem = priv->memory_layout; |
| 1658 | + int skip_map; |
| 1659 | + |
| 1660 | + WARN_ON((slot < 0) || (slot > mem->slot_num - 1)); |
| 1661 | + WARN_ON(qtd->length && !qtd->payload_addr); |
| 1662 | + WARN_ON(slots[slot].qtd); |
| 1663 | + WARN_ON(slots[slot].qh); |
| 1664 | + WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC); |
| 1665 | + |
| 1666 | + if (priv->is_isp1763) |
| 1667 | + ndelay(100); |
| 1668 | + |
| 1669 | + /* Make sure done map has not triggered from some unlinked transfer */ |
| 1670 | + if (ptd_offset == ATL_PTD_OFFSET) { |
| 1671 | + skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); |
| 1672 | + isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, |
| 1673 | + skip_map | (1 << slot)); |
| 1674 | + priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP); |
| 1675 | + priv->atl_done_map &= ~(1 << slot); |
| 1676 | + } else { |
| 1677 | + skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); |
| 1678 | + isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, |
| 1679 | + skip_map | (1 << slot)); |
| 1680 | + priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP); |
| 1681 | + priv->int_done_map &= ~(1 << slot); |
| 1682 | + } |
| 1683 | + |
| 1684 | + skip_map &= ~(1 << slot); |
| 1685 | + qh->slot = slot; |
| 1686 | + qtd->status = QTD_XFER_STARTED; |
| 1687 | + slots[slot].qtd = qtd; |
| 1688 | + slots[slot].qh = qh; |
| 1689 | + |
| 1690 | + ptd_write(hcd, ptd_offset, slot, ptd); |
| 1691 | + |
| 1692 | + if (ptd_offset == ATL_PTD_OFFSET) |
| 1693 | + isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map); |
| 1694 | + else |
| 1695 | + isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map); |
| 1696 | +} |
| 1697 | + |
| 1698 | +static int is_short_bulk(struct isp1760_qtd *qtd) |
| 1699 | +{ |
| 1700 | + return (usb_pipebulk(qtd->urb->pipe) && |
| 1701 | + (qtd->actual_length < qtd->length)); |
| 1702 | +} |
| 1703 | + |
| 1704 | +static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, |
| 1705 | + struct list_head *urb_list) |
| 1706 | +{ |
| 1707 | + struct isp1760_qtd *qtd, *qtd_next; |
| 1708 | + struct urb_listitem *urb_listitem; |
| 1709 | + int last_qtd; |
| 1710 | + |
| 1711 | + list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) { |
| 1712 | + if (qtd->status < QTD_XFER_COMPLETE) |
| 1713 | + break; |
| 1714 | + |
| 1715 | + last_qtd = last_qtd_of_urb(qtd, qh); |
| 1716 | + |
| 1717 | + if ((!last_qtd) && (qtd->status == QTD_RETIRE)) |
| 1718 | + qtd_next->status = QTD_RETIRE; |
| 1719 | + |
| 1720 | + if (qtd->status == QTD_XFER_COMPLETE) { |
| 1721 | + if (qtd->actual_length) { |
| 1722 | + switch (qtd->packet_type) { |
| 1723 | + case IN_PID: |
| 1724 | + mem_read(hcd, qtd->payload_addr, |
| 1725 | + qtd->data_buffer, |
| 1726 | + qtd->actual_length); |
| 1727 | + fallthrough; |
| 1728 | + case OUT_PID: |
| 1729 | + qtd->urb->actual_length += |
| 1730 | + qtd->actual_length; |
| 1731 | + fallthrough; |
| 1732 | + case SETUP_PID: |
| 1733 | + break; |
| 1734 | + } |
| 1735 | + } |
| 1736 | + |
| 1737 | + if (is_short_bulk(qtd)) { |
| 1738 | + if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 1739 | + qtd->urb->status = -EREMOTEIO; |
| 1740 | + if (!last_qtd) |
| 1741 | + qtd_next->status = QTD_RETIRE; |
| 1742 | + } |
| 1743 | + } |
| 1744 | + |
| 1745 | + if (qtd->payload_addr) |
| 1746 | + free_mem(hcd, qtd); |
| 1747 | + |
| 1748 | + if (last_qtd) { |
| 1749 | + if ((qtd->status == QTD_RETIRE) && |
| 1750 | + (qtd->urb->status == -EINPROGRESS)) |
| 1751 | + qtd->urb->status = -EPIPE; |
| 1752 | + /* Defer calling of urb_done() since it releases lock */ |
| 1753 | + urb_listitem = kmem_cache_alloc(urb_listitem_cachep, |
| 1754 | + GFP_ATOMIC); |
| 1755 | + if (unlikely(!urb_listitem)) |
| 1756 | + break; /* Try again on next call */ |
| 1757 | + urb_listitem->urb = qtd->urb; |
| 1758 | + list_add_tail(&urb_listitem->urb_list, urb_list); |
| 1759 | + } |
| 1760 | + |
| 1761 | + list_del(&qtd->qtd_list); |
| 1762 | + qtd_free(qtd); |
| 1763 | + } |
| 1764 | +} |
| 1765 | + |
| 1766 | +#define ENQUEUE_DEPTH 2 |
| 1767 | +static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) |
| 1768 | +{ |
| 1769 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1770 | + const struct isp1760_memory_layout *mem = priv->memory_layout; |
| 1771 | + int slot_num = mem->slot_num; |
| 1772 | + int ptd_offset; |
| 1773 | + struct isp1760_slotinfo *slots; |
| 1774 | + int curr_slot, free_slot; |
| 1775 | + int n; |
| 1776 | + struct ptd ptd; |
| 1777 | + struct isp1760_qtd *qtd; |
| 1778 | + |
| 1779 | + if (unlikely(list_empty(&qh->qtd_list))) |
| 1780 | + return; |
| 1781 | + |
| 1782 | + /* Make sure this endpoint's TT buffer is clean before queueing ptds */ |
| 1783 | + if (qh->tt_buffer_dirty) |
| 1784 | + return; |
| 1785 | + |
| 1786 | + if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd, |
| 1787 | + qtd_list)->urb->pipe)) { |
| 1788 | + ptd_offset = INT_PTD_OFFSET; |
| 1789 | + slots = priv->int_slots; |
| 1790 | + } else { |
| 1791 | + ptd_offset = ATL_PTD_OFFSET; |
| 1792 | + slots = priv->atl_slots; |
| 1793 | + } |
| 1794 | + |
| 1795 | + free_slot = -1; |
| 1796 | + for (curr_slot = 0; curr_slot < slot_num; curr_slot++) { |
| 1797 | + if ((free_slot == -1) && (slots[curr_slot].qtd == NULL)) |
| 1798 | + free_slot = curr_slot; |
| 1799 | + if (slots[curr_slot].qh == qh) |
| 1800 | + break; |
| 1801 | + } |
| 1802 | + |
| 1803 | + n = 0; |
| 1804 | + list_for_each_entry(qtd, &qh->qtd_list, qtd_list) { |
| 1805 | + if (qtd->status == QTD_ENQUEUED) { |
| 1806 | + WARN_ON(qtd->payload_addr); |
| 1807 | + alloc_mem(hcd, qtd); |
| 1808 | + if ((qtd->length) && (!qtd->payload_addr)) |
| 1809 | + break; |
| 1810 | + |
| 1811 | + if (qtd->length && (qtd->packet_type == SETUP_PID || |
| 1812 | + qtd->packet_type == OUT_PID)) { |
| 1813 | + mem_write(hcd, qtd->payload_addr, |
| 1814 | + qtd->data_buffer, qtd->length); |
| 1815 | + } |
| 1816 | + |
| 1817 | + qtd->status = QTD_PAYLOAD_ALLOC; |
| 1818 | + } |
| 1819 | + |
| 1820 | + if (qtd->status == QTD_PAYLOAD_ALLOC) { |
| 1821 | +/* |
| 1822 | + if ((curr_slot > 31) && (free_slot == -1)) |
| 1823 | + printf("%s: No slot " |
| 1824 | + "available for transfer\n", __func__); |
| 1825 | +*/ |
| 1826 | + /* Start xfer for this endpoint if not already done */ |
| 1827 | + if ((curr_slot > slot_num - 1) && (free_slot > -1)) { |
| 1828 | + if (usb_pipeint(qtd->urb->pipe)) |
| 1829 | + create_ptd_int(qh, qtd, &ptd); |
| 1830 | + else |
| 1831 | + create_ptd_atl(qh, qtd, &ptd); |
| 1832 | + |
| 1833 | + start_bus_transfer(hcd, ptd_offset, free_slot, |
| 1834 | + slots, qtd, qh, &ptd); |
| 1835 | + curr_slot = free_slot; |
| 1836 | + } |
| 1837 | + |
| 1838 | + n++; |
| 1839 | + if (n >= ENQUEUE_DEPTH) |
| 1840 | + break; |
| 1841 | + } |
| 1842 | + } |
| 1843 | +} |
| 1844 | + |
| 1845 | +static void schedule_ptds(struct usb_hcd *hcd) |
| 1846 | +{ |
| 1847 | + struct isp1760_hcd *priv; |
| 1848 | + struct isp1760_qh *qh, *qh_next; |
| 1849 | + struct list_head *ep_queue; |
| 1850 | + LIST_HEAD(urb_list); |
| 1851 | + struct urb_listitem *urb_listitem, *urb_listitem_next; |
| 1852 | + int i; |
| 1853 | + |
| 1854 | + if (!hcd) { |
| 1855 | + WARN_ON(1); |
| 1856 | + return; |
| 1857 | + } |
| 1858 | + |
| 1859 | + priv = hcd_to_priv(hcd); |
| 1860 | + |
| 1861 | + /* |
| 1862 | + * check finished/retired xfers, transfer payloads, call urb_done() |
| 1863 | + */ |
| 1864 | + for (i = 0; i < QH_END; i++) { |
| 1865 | + ep_queue = &priv->qh_list[i]; |
| 1866 | + list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) |
| 1867 | + collect_qtds(hcd, qh, &urb_list); |
| 1868 | + } |
| 1869 | + |
| 1870 | + list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list, |
| 1871 | + urb_list) { |
| 1872 | + isp1760_urb_done(hcd, urb_listitem->urb); |
| 1873 | + kmem_cache_free(urb_listitem_cachep, urb_listitem); |
| 1874 | + } |
| 1875 | + |
| 1876 | + /* |
| 1877 | + * Schedule packets for transfer. |
| 1878 | + * |
| 1879 | + * According to USB2.0 specification: |
| 1880 | + * |
| 1881 | + * 1st prio: interrupt xfers, up to 80 % of bandwidth |
| 1882 | + * 2nd prio: control xfers |
| 1883 | + * 3rd prio: bulk xfers |
| 1884 | + * |
| 1885 | + * ... but let's use a simpler scheme here (mostly because ISP1761 doc |
| 1886 | + * is very unclear on how to prioritize traffic): |
| 1887 | + * |
| 1888 | + * 1) Enqueue any queued control transfers, as long as payload chip mem |
| 1889 | + * and PTD ATL slots are available. |
| 1890 | + * 2) Enqueue any queued INT transfers, as long as payload chip mem |
| 1891 | + * and PTD INT slots are available. |
| 1892 | + * 3) Enqueue any queued bulk transfers, as long as payload chip mem |
| 1893 | + * and PTD ATL slots are available. |
| 1894 | + * |
| 1895 | + * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between |
| 1896 | + * conservation of chip mem and performance. |
| 1897 | + * |
| 1898 | + * I'm sure this scheme could be improved upon! |
| 1899 | + */ |
| 1900 | + for (i = 0; i < QH_END; i++) { |
| 1901 | + ep_queue = &priv->qh_list[i]; |
| 1902 | + list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) |
| 1903 | + enqueue_qtds(hcd, qh); |
| 1904 | + } |
| 1905 | +} |
| 1906 | + |
| 1907 | +#define PTD_STATE_QTD_DONE 1 |
| 1908 | +#define PTD_STATE_QTD_RELOAD 2 |
| 1909 | +#define PTD_STATE_URB_RETIRE 3 |
| 1910 | + |
| 1911 | +static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd, |
| 1912 | + struct urb *urb) |
| 1913 | +{ |
| 1914 | + u32 dw4; |
| 1915 | + int i; |
| 1916 | + |
| 1917 | + dw4 = TO_U32(ptd->dw4); |
| 1918 | + dw4 >>= 8; |
| 1919 | + |
| 1920 | + /* FIXME: ISP1761 datasheet does not say what to do with these. Do we |
| 1921 | + need to handle these errors? Is it done in hardware? */ |
| 1922 | + if (ptd->dw3 & DW3_HALT_BIT) { |
| 1923 | + |
| 1924 | + urb->status = -EPROTO; /* Default unknown error */ |
| 1925 | + |
| 1926 | + for (i = 0; i < 8; i++) { |
| 1927 | + switch (dw4 & 0x7) { |
| 1928 | + case INT_UNDERRUN: |
| 1929 | + printf("underrun during uFrame %d\n", i); |
| 1930 | + urb->status = -ECOMM; /* Could not write data */ |
| 1931 | + break; |
| 1932 | + case INT_EXACT: |
| 1933 | + printf("transaction error uFrame %d\n", i); |
| 1934 | + urb->status = -EPROTO; /* timeout, bad CRC, PID |
| 1935 | + error etc. */ |
| 1936 | + break; |
| 1937 | + case INT_BABBLE: |
| 1938 | + printf("babble error during uFrame %d\n", i); |
| 1939 | + urb->status = -EOVERFLOW; |
| 1940 | + break; |
| 1941 | + } |
| 1942 | + dw4 >>= 3; |
| 1943 | + } |
| 1944 | + |
| 1945 | + return PTD_STATE_URB_RETIRE; |
| 1946 | + } |
| 1947 | + |
| 1948 | + return PTD_STATE_QTD_DONE; |
| 1949 | +} |
| 1950 | + |
| 1951 | +static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd, |
| 1952 | + struct urb *urb) |
| 1953 | +{ |
| 1954 | + WARN_ON(!ptd); |
| 1955 | + if (ptd->dw3 & DW3_HALT_BIT) { |
| 1956 | + if (ptd->dw3 & DW3_BABBLE_BIT) |
| 1957 | + urb->status = -EOVERFLOW; |
| 1958 | + else if (FROM_DW3_CERR(ptd->dw3)) |
| 1959 | + urb->status = -EPIPE; /* Stall */ |
| 1960 | + else |
| 1961 | + urb->status = -EPROTO; /* Unknown */ |
| 1962 | + |
| 1963 | + /* usefull debug |
| 1964 | + printf("%s: ptd error:\n" |
| 1965 | + " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n" |
| 1966 | + " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n", |
| 1967 | + __func__, |
| 1968 | + ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3, |
| 1969 | + ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7); |
| 1970 | + */ |
| 1971 | + |
| 1972 | + return PTD_STATE_URB_RETIRE; |
| 1973 | + } |
| 1974 | + |
| 1975 | + /* Transfer Error, *but* active and no HALT -> reload */ |
| 1976 | + if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) |
| 1977 | + return PTD_STATE_QTD_RELOAD; |
| 1978 | + |
| 1979 | + /* |
| 1980 | + * NAKs are handled in HW by the chip. Usually if the |
| 1981 | + * device is not able to send data fast enough. |
| 1982 | + * This happens mostly on slower hardware. |
| 1983 | + */ |
| 1984 | + if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) |
| 1985 | + return PTD_STATE_QTD_RELOAD; |
| 1986 | + |
| 1987 | + return PTD_STATE_QTD_DONE; |
| 1988 | +} |
| 1989 | + |
| 1990 | +static void handle_done_ptds(struct usb_hcd *hcd) |
| 1991 | +{ |
| 1992 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1993 | + struct isp1760_slotinfo *slots; |
| 1994 | + struct isp1760_qtd *qtd; |
| 1995 | + struct isp1760_qh *qh; |
| 1996 | + struct ptd ptd; |
| 1997 | + u32 ptd_offset; |
| 1998 | + int modified; |
| 1999 | + int skip_map; |
| 2000 | + int state; |
| 2001 | + int slot; |
| 2002 | + |
| 2003 | + skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); |
| 2004 | + priv->int_done_map &= ~skip_map; |
| 2005 | + skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); |
| 2006 | + priv->atl_done_map &= ~skip_map; |
| 2007 | + |
| 2008 | + modified = priv->int_done_map || priv->atl_done_map; |
| 2009 | + |
| 2010 | + while (priv->int_done_map || priv->atl_done_map) { |
| 2011 | + if (priv->int_done_map) { |
| 2012 | + /* INT ptd */ |
| 2013 | + slot = __ffs(priv->int_done_map); |
| 2014 | + priv->int_done_map &= ~(1 << slot); |
| 2015 | + slots = priv->int_slots; |
| 2016 | + /* This should not trigger, and could be removed if |
| 2017 | + noone have any problems with it triggering: */ |
| 2018 | + if (!slots[slot].qh) { |
| 2019 | + WARN_ON(1); |
| 2020 | + continue; |
| 2021 | + } |
| 2022 | + ptd_offset = INT_PTD_OFFSET; |
| 2023 | + ptd_read(hcd, INT_PTD_OFFSET, slot, &ptd); |
| 2024 | + state = check_int_transfer(hcd, &ptd, |
| 2025 | + slots[slot].qtd->urb); |
| 2026 | + } else { |
| 2027 | + /* ATL ptd */ |
| 2028 | + slot = __ffs(priv->atl_done_map); |
| 2029 | + priv->atl_done_map &= ~(1 << slot); |
| 2030 | + slots = priv->atl_slots; |
| 2031 | + /* This should not trigger, and could be removed if |
| 2032 | + noone have any problems with it triggering: */ |
| 2033 | + if (!slots[slot].qh) { |
| 2034 | + WARN_ON(1); |
| 2035 | + continue; |
| 2036 | + } |
| 2037 | + ptd_offset = ATL_PTD_OFFSET; |
| 2038 | + ptd_read(hcd, ATL_PTD_OFFSET, slot, &ptd); |
| 2039 | + state = check_atl_transfer(hcd, &ptd, |
| 2040 | + slots[slot].qtd->urb); |
| 2041 | + } |
| 2042 | + |
| 2043 | + qtd = slots[slot].qtd; |
| 2044 | + slots[slot].qtd = NULL; |
| 2045 | + qh = slots[slot].qh; |
| 2046 | + slots[slot].qh = NULL; |
| 2047 | + qh->slot = -1; |
| 2048 | + |
| 2049 | + WARN_ON(qtd->status != QTD_XFER_STARTED); |
| 2050 | + |
| 2051 | + switch (state) { |
| 2052 | + case PTD_STATE_QTD_DONE: |
| 2053 | + if ((usb_pipeint(qtd->urb->pipe)) && |
| 2054 | + (qtd->urb->dev->speed != USB_SPEED_HIGH)) |
| 2055 | + qtd->actual_length = |
| 2056 | + FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3); |
| 2057 | + else |
| 2058 | + qtd->actual_length = |
| 2059 | + FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3); |
| 2060 | + |
| 2061 | + qtd->status = QTD_XFER_COMPLETE; |
| 2062 | + |
| 2063 | + if (list_is_last(&qtd->qtd_list, &qh->qtd_list) || |
| 2064 | + is_short_bulk(qtd)) |
| 2065 | + qtd = NULL; |
| 2066 | + else |
| 2067 | + qtd = list_entry(qtd->qtd_list.next, |
| 2068 | + typeof(*qtd), qtd_list); |
| 2069 | + |
| 2070 | + qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); |
| 2071 | + qh->ping = FROM_DW3_PING(ptd.dw3); |
| 2072 | + |
| 2073 | + break; |
| 2074 | + |
| 2075 | + case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */ |
| 2076 | + qtd->status = QTD_PAYLOAD_ALLOC; |
| 2077 | + ptd.dw0 |= DW0_VALID_BIT; |
| 2078 | + /* RL counter = ERR counter */ |
| 2079 | + ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf); |
| 2080 | + ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2)); |
| 2081 | + ptd.dw3 &= ~TO_DW3_CERR(3); |
| 2082 | + ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER); |
| 2083 | + |
| 2084 | + qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); |
| 2085 | + qh->ping = FROM_DW3_PING(ptd.dw3); |
| 2086 | + break; |
| 2087 | + |
| 2088 | + case PTD_STATE_URB_RETIRE: |
| 2089 | + qtd->status = QTD_RETIRE; |
| 2090 | + qtd = NULL; |
| 2091 | + qh->toggle = 0; |
| 2092 | + qh->ping = 0; |
| 2093 | + break; |
| 2094 | + |
| 2095 | + default: |
| 2096 | + WARN_ON(1); |
| 2097 | + continue; |
| 2098 | + } |
| 2099 | + |
| 2100 | + if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) { |
| 2101 | + if (slots == priv->int_slots) { |
| 2102 | + if (state == PTD_STATE_QTD_RELOAD) |
| 2103 | + dev_err(priv->dev, |
| 2104 | + "%s: PTD_STATE_QTD_RELOAD on " |
| 2105 | + "interrupt packet\n", __func__); |
| 2106 | + if (state != PTD_STATE_QTD_RELOAD) |
| 2107 | + create_ptd_int(qh, qtd, &ptd); |
| 2108 | + } else { |
| 2109 | + if (state != PTD_STATE_QTD_RELOAD) |
| 2110 | + create_ptd_atl(qh, qtd, &ptd); |
| 2111 | + } |
| 2112 | + |
| 2113 | + start_bus_transfer(hcd, ptd_offset, slot, slots, qtd, |
| 2114 | + qh, &ptd); |
| 2115 | + } |
| 2116 | + } |
| 2117 | + |
| 2118 | + if (modified) |
| 2119 | + schedule_ptds(hcd); |
| 2120 | +} |
| 2121 | + |
| 2122 | +static irqreturn_t isp1760_irq(int irq, void *__hci) |
| 2123 | +{ |
| 2124 | + struct usb_hcd *hcd = __hci; |
| 2125 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 2126 | + irqreturn_t irqret = IRQ_NONE; |
| 2127 | + u32 int_reg; |
| 2128 | + u32 imask; |
| 2129 | + |
| 2130 | + imask = isp1760_hcd_read(hcd, HC_INTERRUPT); |
| 2131 | + if (unlikely(!imask)) |
| 2132 | + return irqret; |
| 2133 | + |
| 2134 | + int_reg = priv->is_isp1763 ? ISP1763_HC_INTERRUPT : |
| 2135 | + ISP176x_HC_INTERRUPT; |
| 2136 | + isp1760_reg_write(priv->regs, int_reg, imask); |
| 2137 | + |
| 2138 | + priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP); |
| 2139 | + priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP); |
| 2140 | + |
| 2141 | + handle_done_ptds(hcd); |
| 2142 | + |
| 2143 | + irqret = IRQ_HANDLED; |
| 2144 | + |
| 2145 | + return irqret; |
| 2146 | +} |
| 2147 | + |
| 2148 | +static int isp1763_run(struct usb_hcd *hcd) |
| 2149 | +{ |
| 2150 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 2151 | + int retval; |
| 2152 | + u32 chipid_h; |
| 2153 | + u32 chipid_l; |
| 2154 | + u32 chip_rev; |
| 2155 | + u32 ptd_atl_int; |
| 2156 | + u32 ptd_iso; |
| 2157 | + |
| 2158 | + chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); |
| 2159 | + chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW); |
| 2160 | + chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV); |
| 2161 | + printf("USB ISP %02x%02x HW rev. %d started\n", chipid_h, |
| 2162 | + chipid_l, chip_rev); |
| 2163 | + |
| 2164 | + isp1760_hcd_clear(hcd, ISO_BUF_FILL); |
| 2165 | + isp1760_hcd_clear(hcd, INT_BUF_FILL); |
| 2166 | + isp1760_hcd_clear(hcd, ATL_BUF_FILL); |
| 2167 | + |
| 2168 | + isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); |
| 2169 | + isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); |
| 2170 | + isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); |
| 2171 | + ndelay(100); |
| 2172 | + isp1760_hcd_clear(hcd, HC_ATL_PTD_DONEMAP); |
| 2173 | + isp1760_hcd_clear(hcd, HC_INT_PTD_DONEMAP); |
| 2174 | + isp1760_hcd_clear(hcd, HC_ISO_PTD_DONEMAP); |
| 2175 | + |
| 2176 | + isp1760_hcd_set(hcd, HW_OTG_DISABLE); |
| 2177 | + isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(7)); |
| 2178 | + isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(15)); |
| 2179 | + mdelay(10); |
| 2180 | + |
| 2181 | + isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE); |
| 2182 | + isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE); |
| 2183 | + |
| 2184 | + isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN); |
| 2185 | + |
| 2186 | + isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND); |
| 2187 | + isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND); |
| 2188 | + isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND); |
| 2189 | + |
| 2190 | + isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR); |
| 2191 | + isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR); |
| 2192 | + isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR); |
| 2193 | + |
| 2194 | + ptd_atl_int = 0x8000; |
| 2195 | + ptd_iso = 0x0001; |
| 2196 | + |
| 2197 | + isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int); |
| 2198 | + isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int); |
| 2199 | + isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso); |
| 2200 | + |
| 2201 | + isp1760_hcd_set(hcd, ATL_BUF_FILL); |
| 2202 | + isp1760_hcd_set(hcd, INT_BUF_FILL); |
| 2203 | + |
| 2204 | + isp1760_hcd_clear(hcd, CMD_LRESET); |
| 2205 | + isp1760_hcd_clear(hcd, CMD_RESET); |
| 2206 | + |
| 2207 | + retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000); |
| 2208 | + if (retval) |
| 2209 | + return retval; |
| 2210 | + |
| 2211 | + down_write(&ehci_cf_port_reset_rwsem); |
| 2212 | + retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000); |
| 2213 | + up_write(&ehci_cf_port_reset_rwsem); |
| 2214 | + retval = 0; |
| 2215 | + if (retval) |
| 2216 | + return retval; |
| 2217 | + |
| 2218 | + return 0; |
| 2219 | +} |
| 2220 | + |
| 2221 | +static int isp1760_run(struct usb_hcd *hcd) |
| 2222 | +{ |
| 2223 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 2224 | + int retval; |
| 2225 | + u32 chipid_h; |
| 2226 | + u32 chipid_l; |
| 2227 | + u32 chip_rev; |
| 2228 | + u32 ptd_atl_int; |
| 2229 | + u32 ptd_iso; |
| 2230 | + |
| 2231 | + /* |
| 2232 | + * ISP1763 have some differences in the setup and order to enable |
| 2233 | + * the ports, disable otg, setup buffers, and ATL, INT, ISO status. |
| 2234 | + * So, just handle it a separate sequence. |
| 2235 | + */ |
| 2236 | + if (priv->is_isp1763) |
| 2237 | + return isp1763_run(hcd); |
| 2238 | + |
| 2239 | + /* Set PTD interrupt AND & OR maps */ |
| 2240 | + isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND); |
| 2241 | + isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND); |
| 2242 | + isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND); |
| 2243 | + |
| 2244 | + isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR); |
| 2245 | + isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR); |
| 2246 | + isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR); |
| 2247 | + |
| 2248 | + /* step 23 passed */ |
| 2249 | + |
| 2250 | + isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN); |
| 2251 | + |
| 2252 | + isp1760_hcd_clear(hcd, CMD_LRESET); |
| 2253 | + isp1760_hcd_clear(hcd, CMD_RESET); |
| 2254 | + |
| 2255 | + retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000); |
| 2256 | + if (retval) |
| 2257 | + return retval; |
| 2258 | + |
| 2259 | + /* |
| 2260 | + * XXX |
| 2261 | + * Spec says to write FLAG_CF as last config action, priv code grabs |
| 2262 | + * the semaphore while doing so. |
| 2263 | + */ |
| 2264 | + down_write(&ehci_cf_port_reset_rwsem); |
| 2265 | + |
| 2266 | + retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000); |
| 2267 | + up_write(&ehci_cf_port_reset_rwsem); |
| 2268 | + if (retval) |
| 2269 | + return retval; |
| 2270 | + |
| 2271 | + chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); |
| 2272 | + chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW); |
| 2273 | + chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV); |
| 2274 | + dev_info(priv->dev, "USB ISP %02x%02x HW rev. %d started\n", |
| 2275 | + chipid_h, chipid_l, chip_rev); |
| 2276 | + |
| 2277 | + /* PTD Register Init Part 2, Step 28 */ |
| 2278 | + |
| 2279 | + /* Setup registers controlling PTD checking */ |
| 2280 | + ptd_atl_int = 0x80000000; |
| 2281 | + ptd_iso = 0x00000001; |
| 2282 | + |
| 2283 | + isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int); |
| 2284 | + isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int); |
| 2285 | + isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso); |
| 2286 | + |
| 2287 | + isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); |
| 2288 | + isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); |
| 2289 | + isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); |
| 2290 | + |
| 2291 | + isp1760_hcd_set(hcd, ATL_BUF_FILL); |
| 2292 | + isp1760_hcd_set(hcd, INT_BUF_FILL); |
| 2293 | + |
| 2294 | + /* GRR this is run-once init(), being done every time the HC starts. |
| 2295 | + * So long as they're part of class devices, we can't do it init() |
| 2296 | + * since the class device isn't created that early. |
| 2297 | + */ |
| 2298 | + return 0; |
| 2299 | +} |
| 2300 | + |
| 2301 | +static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len) |
| 2302 | +{ |
| 2303 | + qtd->data_buffer = databuffer; |
| 2304 | + |
| 2305 | + qtd->length = len; |
| 2306 | + |
| 2307 | + return qtd->length; |
| 2308 | +} |
| 2309 | + |
| 2310 | +static void qtd_list_free(struct list_head *qtd_list) |
| 2311 | +{ |
| 2312 | + struct isp1760_qtd *qtd, *qtd_next; |
| 2313 | + |
| 2314 | + list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) { |
| 2315 | + list_del(&qtd->qtd_list); |
| 2316 | + qtd_free(qtd); |
| 2317 | + } |
| 2318 | +} |
| 2319 | + |
| 2320 | +/* |
| 2321 | + * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize. |
| 2322 | + * Also calculate the PID type (SETUP/IN/OUT) for each packet. |
| 2323 | + */ |
| 2324 | +#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) |
| 2325 | +static void packetize_urb(struct usb_hcd *hcd, |
| 2326 | + struct urb *urb, struct list_head *head, gfp_t flags) |
| 2327 | +{ |
| 2328 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 2329 | + const struct isp1760_memory_layout *mem = priv->memory_layout; |
| 2330 | + struct isp1760_qtd *qtd; |
| 2331 | + void *buf; |
| 2332 | + int len, maxpacketsize; |
| 2333 | + u8 packet_type; |
| 2334 | + |
| 2335 | + /* |
| 2336 | + * URBs map to sequences of QTDs: one logical transaction |
| 2337 | + */ |
| 2338 | + |
| 2339 | + if (!urb->transfer_buffer && urb->transfer_buffer_length) { |
| 2340 | + /* XXX This looks like usb storage / SCSI bug */ |
| 2341 | + dev_err(priv->dev, "buf is null, dma is %08lx len is %d\n", |
| 2342 | + (long unsigned)urb->transfer_dma, |
| 2343 | + urb->transfer_buffer_length); |
| 2344 | + WARN_ON(1); |
| 2345 | + } |
| 2346 | + |
| 2347 | + if (usb_pipein(urb->pipe)) |
| 2348 | + packet_type = IN_PID; |
| 2349 | + else |
| 2350 | + packet_type = OUT_PID; |
| 2351 | + |
| 2352 | + if (usb_pipecontrol(urb->pipe)) { |
| 2353 | + qtd = qtd_alloc(flags, urb, SETUP_PID); |
| 2354 | + if (!qtd) |
| 2355 | + goto cleanup; |
| 2356 | + qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest)); |
| 2357 | + list_add_tail(&qtd->qtd_list, head); |
| 2358 | + |
| 2359 | + /* for zero length DATA stages, STATUS is always IN */ |
| 2360 | + if (urb->transfer_buffer_length == 0) |
| 2361 | + packet_type = IN_PID; |
| 2362 | + } |
| 2363 | + |
| 2364 | + maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe)); |
| 2365 | + |
| 2366 | + /* |
| 2367 | + * buffer gets wrapped in one or more qtds; |
| 2368 | + * last one may be "short" (including zero len) |
| 2369 | + * and may serve as a control status ack |
| 2370 | + */ |
| 2371 | + buf = urb->transfer_buffer; |
| 2372 | + len = urb->transfer_buffer_length; |
| 2373 | + |
| 2374 | + for (;;) { |
| 2375 | + int this_qtd_len; |
| 2376 | + |
| 2377 | + qtd = qtd_alloc(flags, urb, packet_type); |
| 2378 | + if (!qtd) |
| 2379 | + goto cleanup; |
| 2380 | + |
| 2381 | + if (len > mem->blocks_size[ISP176x_BLOCK_NUM - 1]) |
| 2382 | + len = mem->blocks_size[ISP176x_BLOCK_NUM - 1]; |
| 2383 | + |
| 2384 | + this_qtd_len = qtd_fill(qtd, buf, len); |
| 2385 | + list_add_tail(&qtd->qtd_list, head); |
| 2386 | + |
| 2387 | + len -= this_qtd_len; |
| 2388 | + buf += this_qtd_len; |
| 2389 | + |
| 2390 | + if (len <= 0) |
| 2391 | + break; |
| 2392 | + } |
| 2393 | + |
| 2394 | + /* |
| 2395 | + * control requests may need a terminating data "status" ack; |
| 2396 | + * bulk ones may need a terminating short packet (zero length). |
| 2397 | + */ |
| 2398 | + if (urb->transfer_buffer_length != 0) { |
| 2399 | + int one_more = 0; |
| 2400 | + |
| 2401 | + if (usb_pipecontrol(urb->pipe)) { |
| 2402 | + one_more = 1; |
| 2403 | + if (packet_type == IN_PID) |
| 2404 | + packet_type = OUT_PID; |
| 2405 | + else |
| 2406 | + packet_type = IN_PID; |
| 2407 | + } else if (usb_pipebulk(urb->pipe) |
| 2408 | + && (urb->transfer_flags & URB_ZERO_PACKET) |
| 2409 | + && !(urb->transfer_buffer_length % |
| 2410 | + maxpacketsize)) { |
| 2411 | + one_more = 1; |
| 2412 | + } |
| 2413 | + if (one_more) { |
| 2414 | + qtd = qtd_alloc(flags, urb, packet_type); |
| 2415 | + if (!qtd) |
| 2416 | + goto cleanup; |
| 2417 | + |
| 2418 | + /* never any data in such packets */ |
| 2419 | + qtd_fill(qtd, NULL, 0); |
| 2420 | + list_add_tail(&qtd->qtd_list, head); |
| 2421 | + } |
| 2422 | + } |
| 2423 | + |
| 2424 | + return; |
| 2425 | + |
| 2426 | +cleanup: |
| 2427 | + qtd_list_free(head); |
| 2428 | +} |
| 2429 | + |
| 2430 | +static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, |
| 2431 | + gfp_t mem_flags) |
| 2432 | +{ |
| 2433 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 2434 | + struct isp1760_qh *qh = NULL; |
| 2435 | + struct list_head *ep_queue; |
| 2436 | + LIST_HEAD(new_qtds); |
| 2437 | + int qh_in_queue; |
| 2438 | + int retval; |
| 2439 | + int epnum; |
| 2440 | + |
| 2441 | + switch (usb_pipetype(urb->pipe)) { |
| 2442 | + case PIPE_CONTROL: |
| 2443 | + ep_queue = &priv->qh_list[QH_CONTROL]; |
| 2444 | + break; |
| 2445 | + case PIPE_BULK: |
| 2446 | + ep_queue = &priv->qh_list[QH_BULK]; |
| 2447 | + break; |
| 2448 | + case PIPE_INTERRUPT: |
| 2449 | + ep_queue = &priv->qh_list[QH_INTERRUPT]; |
| 2450 | + break; |
| 2451 | + case PIPE_ISOCHRONOUS: |
| 2452 | + printf("isochronous USB packets not yet supported\n"); |
| 2453 | + return -EPIPE; |
| 2454 | + default: |
| 2455 | + printf("unknown pipe type\n"); |
| 2456 | + return -EPIPE; |
| 2457 | + } |
| 2458 | + |
| 2459 | + if (usb_pipein(urb->pipe)) |
| 2460 | + urb->actual_length = 0; |
| 2461 | + |
| 2462 | + packetize_urb(hcd, urb, &new_qtds, mem_flags); |
| 2463 | + if (list_empty(&new_qtds)) |
| 2464 | + return -ENOMEM; |
| 2465 | + |
| 2466 | + retval = usb_hcd_link_urb_to_ep(hcd, urb); |
| 2467 | + if (retval) { |
| 2468 | + qtd_list_free(&new_qtds); |
| 2469 | + goto out; |
| 2470 | + } |
| 2471 | + |
| 2472 | + epnum = usb_pipeendpoint(urb->pipe); |
| 2473 | + |
| 2474 | + qh_in_queue = 0; |
| 2475 | + list_for_each_entry(qh, ep_queue, qh_list) { |
| 2476 | + if (qh->epnum == epnum) { |
| 2477 | + qh_in_queue = 1; |
| 2478 | + break; |
| 2479 | + } |
| 2480 | + } |
| 2481 | + |
| 2482 | + if (!qh_in_queue) { |
| 2483 | + qh = qh_alloc(GFP_ATOMIC); |
| 2484 | + if (!qh) { |
| 2485 | + retval = -ENOMEM; |
| 2486 | + usb_hcd_unlink_urb_from_ep(hcd, urb); |
| 2487 | + qtd_list_free(&new_qtds); |
| 2488 | + goto out; |
| 2489 | + } |
| 2490 | + |
| 2491 | + qh->epnum = epnum; |
| 2492 | + list_add_tail(&qh->qh_list, ep_queue); |
| 2493 | + urb->ep->hcpriv = qh; |
| 2494 | + } |
| 2495 | + |
| 2496 | + list_splice_tail(&new_qtds, &qh->qtd_list); |
| 2497 | + schedule_ptds(hcd); |
| 2498 | + |
| 2499 | +out: |
| 2500 | + return retval; |
| 2501 | +} |
| 2502 | + |
| 2503 | +static void kill_transfer(struct usb_hcd *hcd, struct urb *urb, |
| 2504 | + struct isp1760_qh *qh) |
| 2505 | +{ |
| 2506 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 2507 | + int skip_map; |
| 2508 | + |
| 2509 | + WARN_ON(qh->slot == -1); |
| 2510 | + |
| 2511 | + /* We need to forcefully reclaim the slot since some transfers never |
| 2512 | + return, e.g. interrupt transfers and NAKed bulk transfers. */ |
| 2513 | + if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) { |
| 2514 | + skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); |
| 2515 | + skip_map |= (1 << qh->slot); |
| 2516 | + isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map); |
| 2517 | + ndelay(100); |
| 2518 | + priv->atl_slots[qh->slot].qh = NULL; |
| 2519 | + priv->atl_slots[qh->slot].qtd = NULL; |
| 2520 | + } else { |
| 2521 | + skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); |
| 2522 | + skip_map |= (1 << qh->slot); |
| 2523 | + isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map); |
| 2524 | + priv->int_slots[qh->slot].qh = NULL; |
| 2525 | + priv->int_slots[qh->slot].qtd = NULL; |
| 2526 | + } |
| 2527 | + |
| 2528 | + qh->slot = -1; |
| 2529 | +} |
| 2530 | + |
| 2531 | +/* |
| 2532 | + * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing |
| 2533 | + * any active transfer belonging to the urb in the process. |
| 2534 | + */ |
| 2535 | +static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh, |
| 2536 | + struct isp1760_qtd *qtd) |
| 2537 | +{ |
| 2538 | + struct urb *urb; |
| 2539 | + int urb_was_running; |
| 2540 | + |
| 2541 | + urb = qtd->urb; |
| 2542 | + urb_was_running = 0; |
| 2543 | + list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) { |
| 2544 | + if (qtd->urb != urb) |
| 2545 | + break; |
| 2546 | + |
| 2547 | + if (qtd->status >= QTD_XFER_STARTED) |
| 2548 | + urb_was_running = 1; |
| 2549 | + if (last_qtd_of_urb(qtd, qh) && |
| 2550 | + (qtd->status >= QTD_XFER_COMPLETE)) |
| 2551 | + urb_was_running = 0; |
| 2552 | + |
| 2553 | + if (qtd->status == QTD_XFER_STARTED) |
| 2554 | + kill_transfer(hcd, urb, qh); |
| 2555 | + qtd->status = QTD_RETIRE; |
| 2556 | + } |
| 2557 | +} |
| 2558 | + |
| 2559 | +int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
| 2560 | +{ |
| 2561 | + struct isp1760_qtd *qtd; |
| 2562 | + struct isp1760_qh *qh; |
| 2563 | + int retval = 0; |
| 2564 | + |
| 2565 | + retval = usb_hcd_check_unlink_urb(hcd, urb, status); |
| 2566 | + if (retval) |
| 2567 | + goto out; |
| 2568 | + |
| 2569 | + qh = urb->ep->hcpriv; |
| 2570 | + if (!qh) { |
| 2571 | + retval = -EINVAL; |
| 2572 | + goto out; |
| 2573 | + } |
| 2574 | + |
| 2575 | + list_for_each_entry(qtd, &qh->qtd_list, qtd_list) |
| 2576 | + if (qtd->urb == urb) { |
| 2577 | + dequeue_urb_from_qtd(hcd, qh, qtd); |
| 2578 | + list_move(&qtd->qtd_list, &qh->qtd_list); |
| 2579 | + break; |
| 2580 | + } |
| 2581 | + |
| 2582 | + urb->status = status; |
| 2583 | + schedule_ptds(hcd); |
| 2584 | + |
| 2585 | +out: |
| 2586 | + return retval; |
| 2587 | +} |
| 2588 | + |
| 2589 | +static void isp1760_hub_descriptor(struct isp1760_hcd *priv, |
| 2590 | + struct usb_hub_descriptor *desc) |
| 2591 | +{ |
| 2592 | + int ports; |
| 2593 | + u16 temp; |
| 2594 | + |
| 2595 | + ports = isp1760_hcd_n_ports(priv->hcd); |
| 2596 | + |
| 2597 | + desc->bDescriptorType = USB_DT_HUB; |
| 2598 | + /* priv 1.0, 2.3.9 says 20ms max */ |
| 2599 | + desc->bPwrOn2PwrGood = 10; |
| 2600 | + desc->bHubContrCurrent = 0; |
| 2601 | + |
| 2602 | + desc->bNbrPorts = ports; |
| 2603 | + temp = 1 + (ports / 8); |
| 2604 | + desc->bLength = 7 + 2 * temp; |
| 2605 | + |
| 2606 | + /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ |
| 2607 | + memset(&desc->u.hs.DeviceRemovable[0], 0, temp); |
| 2608 | + memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); |
| 2609 | + |
| 2610 | + /* per-port overcurrent reporting */ |
| 2611 | + temp = HUB_CHAR_INDV_PORT_OCPM; |
| 2612 | + if (isp1760_hcd_ppc_is_set(priv->hcd)) |
| 2613 | + /* per-port power control */ |
| 2614 | + temp |= HUB_CHAR_INDV_PORT_LPSM; |
| 2615 | + else |
| 2616 | + /* no power switching */ |
| 2617 | + temp |= HUB_CHAR_NO_LPSM; |
| 2618 | + desc->wHubCharacteristics = cpu_to_le16(temp); |
| 2619 | +} |
| 2620 | + |
| 2621 | +#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) |
| 2622 | + |
| 2623 | +static void check_reset_complete(struct usb_hcd *hcd, int index) |
| 2624 | +{ |
| 2625 | + if (!(isp1760_hcd_is_set(hcd, PORT_CONNECT))) |
| 2626 | + return; |
| 2627 | + |
| 2628 | + /* if reset finished and it's still not enabled -- handoff */ |
| 2629 | + if (!isp1760_hcd_is_set(hcd, PORT_PE)) { |
| 2630 | + printf("port %d full speed --> companion\n", index + 1); |
| 2631 | + |
| 2632 | + isp1760_hcd_set(hcd, PORT_OWNER); |
| 2633 | + |
| 2634 | + isp1760_hcd_clear(hcd, PORT_CSC); |
| 2635 | + } else { |
| 2636 | + printf("port %d high speed\n", index + 1); |
| 2637 | + } |
| 2638 | + |
| 2639 | + return; |
| 2640 | +} |
| 2641 | + |
| 2642 | +static int isp1760_hub_control(struct usb_hcd *hcd, struct usb_device *dev, |
| 2643 | + unsigned long pipe, void *buffer, int length, |
| 2644 | + struct devrequest *setup) |
| 2645 | +{ |
| 2646 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 2647 | + u16 typeReq, wValue, wIndex; |
| 2648 | + unsigned long flags; |
| 2649 | + char *buf = buffer; |
| 2650 | + void *src = NULL; |
| 2651 | + int src_len = 0; |
| 2652 | + int retval = 0; |
| 2653 | + u32 status; |
| 2654 | + int ports; |
| 2655 | + |
| 2656 | + if (!setup) |
| 2657 | + return -EINVAL; |
| 2658 | + |
| 2659 | + ports = isp1760_hcd_n_ports(hcd); |
| 2660 | + |
| 2661 | + typeReq = setup->request | (setup->requesttype << 8); |
| 2662 | + wValue = le16_to_cpu(setup->value); |
| 2663 | + wIndex = le16_to_cpu(setup->index); |
| 2664 | + |
| 2665 | + /* |
| 2666 | + * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. |
| 2667 | + * HCS_INDICATOR may say we can change LEDs to off/amber/green. |
| 2668 | + * (track current state ourselves) ... blink for diagnostics, |
| 2669 | + * power, "this is the one", etc. EHCI spec supports this. |
| 2670 | + */ |
| 2671 | + |
| 2672 | + switch (typeReq) { |
| 2673 | + case DeviceOutRequest | USB_REQ_SET_ADDRESS: |
| 2674 | + break; |
| 2675 | + case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: |
| 2676 | + /* Nothing to do */ |
| 2677 | + break; |
| 2678 | + case DeviceRequest | USB_REQ_GET_DESCRIPTOR: |
| 2679 | + switch (wValue & 0xff00) { |
| 2680 | + case USB_DT_DEVICE << 8: |
| 2681 | + src = &rh_descriptor.device; |
| 2682 | + src_len = 0x12; |
| 2683 | + break; |
| 2684 | + case USB_DT_CONFIG << 8: |
| 2685 | + src = &rh_descriptor.config; |
| 2686 | + src_len = 0x09; |
| 2687 | + break; |
| 2688 | + case USB_DT_STRING << 8: |
| 2689 | + switch (wValue & 0xff) { |
| 2690 | + case 0: /* Language */ |
| 2691 | + src = "\4\3\19\4"; |
| 2692 | + src_len = 4; |
| 2693 | + break; |
| 2694 | + case 1: /* Vendor String */ |
| 2695 | + src = "\16\3U\0-\0B\0o\0o\0t\0"; |
| 2696 | + src_len = 14; |
| 2697 | + break; |
| 2698 | + case 2: /* Product Name */ |
| 2699 | + src = "\52\3I\0S\0P\0-\0 " |
| 2700 | + "\0H\0o\0s\0t\0 " |
| 2701 | + "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; |
| 2702 | + src_len = 42; |
| 2703 | + break; |
| 2704 | + default: |
| 2705 | + goto error; |
| 2706 | + } |
| 2707 | + break; |
| 2708 | + } |
| 2709 | + break; |
| 2710 | + case ClearHubFeature: |
| 2711 | + switch (wValue) { |
| 2712 | + case C_HUB_LOCAL_POWER: |
| 2713 | + case C_HUB_OVER_CURRENT: |
| 2714 | + /* no hub-wide feature/status flags */ |
| 2715 | + break; |
| 2716 | + default: |
| 2717 | + goto error; |
| 2718 | + } |
| 2719 | + break; |
| 2720 | + case ClearPortFeature: |
| 2721 | + if (!wIndex || wIndex > ports) |
| 2722 | + goto error; |
| 2723 | + wIndex--; |
| 2724 | + |
| 2725 | + /* |
| 2726 | + * Even if OWNER is set, so the port is owned by the |
| 2727 | + * companion controller, hub_wq needs to be able to clear |
| 2728 | + * the port-change status bits (especially |
| 2729 | + * USB_PORT_STAT_C_CONNECTION). |
| 2730 | + */ |
| 2731 | + |
| 2732 | + switch (wValue) { |
| 2733 | + case USB_PORT_FEAT_ENABLE: |
| 2734 | + isp1760_hcd_clear(hcd, PORT_PE); |
| 2735 | + break; |
| 2736 | + case USB_PORT_FEAT_C_ENABLE: |
| 2737 | + /* XXX error? */ |
| 2738 | + break; |
| 2739 | + case USB_PORT_FEAT_SUSPEND: |
| 2740 | + if (isp1760_hcd_is_set(hcd, PORT_RESET)) |
| 2741 | + goto error; |
| 2742 | + |
| 2743 | + if (isp1760_hcd_is_set(hcd, PORT_SUSPEND)) { |
| 2744 | + if (!isp1760_hcd_is_set(hcd, PORT_PE)) |
| 2745 | + goto error; |
| 2746 | + /* resume signaling for 20 msec */ |
| 2747 | + isp1760_hcd_clear(hcd, PORT_CSC); |
| 2748 | + isp1760_hcd_set(hcd, PORT_RESUME); |
| 2749 | + |
| 2750 | + priv->reset_done = get_timer(0) + 40; |
| 2751 | + } |
| 2752 | + break; |
| 2753 | + case USB_PORT_FEAT_C_SUSPEND: |
| 2754 | + /* we auto-clear this feature */ |
| 2755 | + break; |
| 2756 | + case USB_PORT_FEAT_POWER: |
| 2757 | + if (isp1760_hcd_ppc_is_set(hcd)) |
| 2758 | + isp1760_hcd_clear(hcd, PORT_POWER); |
| 2759 | + break; |
| 2760 | + case USB_PORT_FEAT_C_CONNECTION: |
| 2761 | + isp1760_hcd_set(hcd, PORT_CSC); |
| 2762 | + break; |
| 2763 | + case USB_PORT_FEAT_C_OVER_CURRENT: |
| 2764 | + /* XXX error ?*/ |
| 2765 | + break; |
| 2766 | + case USB_PORT_FEAT_C_RESET: |
| 2767 | + /* GetPortStatus clears reset */ |
| 2768 | + break; |
| 2769 | + default: |
| 2770 | + goto error; |
| 2771 | + } |
| 2772 | + isp1760_hcd_read(hcd, CMD_RUN); |
| 2773 | + break; |
| 2774 | + case GetHubDescriptor: |
| 2775 | + isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) buf); |
| 2776 | + break; |
| 2777 | + case GetHubStatus: |
| 2778 | + /* no hub-wide feature/status flags */ |
| 2779 | + memset(buf, 0, 4); |
| 2780 | + break; |
| 2781 | + case GetPortStatus: |
| 2782 | + if (!wIndex || wIndex > ports) |
| 2783 | + goto error; |
| 2784 | + wIndex--; |
| 2785 | + status = 0; |
| 2786 | + |
| 2787 | + /* wPortChange bits */ |
| 2788 | + if (isp1760_hcd_is_set(hcd, PORT_CSC)) |
| 2789 | + status |= USB_PORT_STAT_C_CONNECTION << 16; |
| 2790 | + |
| 2791 | + /* whoever resumes must GetPortStatus to complete it!! */ |
| 2792 | + if (isp1760_hcd_is_set(hcd, PORT_RESUME)) { |
| 2793 | + status |= USB_PORT_STAT_C_SUSPEND << 16; |
| 2794 | + |
| 2795 | + if (!priv->reset_done) { |
| 2796 | + priv->reset_done = get_timer(0) + 20; |
| 2797 | + } else if (get_timer(0) > priv->reset_done) { |
| 2798 | + /* stop resume signaling */ |
| 2799 | + isp1760_hcd_clear(hcd, PORT_CSC); |
| 2800 | + |
| 2801 | + retval = isp1760_hcd_clear_and_wait(hcd, |
| 2802 | + PORT_RESUME, 2000); |
| 2803 | + if (retval != 0) { |
| 2804 | + printf("port %d resume error %d\n", |
| 2805 | + wIndex + 1, retval); |
| 2806 | + goto error; |
| 2807 | + } |
| 2808 | + } |
| 2809 | + } |
| 2810 | + |
| 2811 | + /* whoever resets must GetPortStatus to complete it!! */ |
| 2812 | + if (isp1760_hcd_is_set(hcd, PORT_RESET) && |
| 2813 | + get_timer(0) > priv->reset_done) { |
| 2814 | + status |= USB_PORT_STAT_C_RESET << 16; |
| 2815 | + priv->reset_done = 0; |
| 2816 | + |
| 2817 | + /* force reset to complete */ |
| 2818 | + /* REVISIT: some hardware needs 550+ usec to clear |
| 2819 | + * this bit; seems too long to spin routinely... |
| 2820 | + */ |
| 2821 | + retval = isp1760_hcd_clear_and_wait(hcd, PORT_RESET, |
| 2822 | + 750); |
| 2823 | + if (retval != 0) { |
| 2824 | + printf("port %d reset error %d\n", wIndex + 1, |
| 2825 | + retval); |
| 2826 | + goto error; |
| 2827 | + } |
| 2828 | + |
| 2829 | + /* see what we found out */ |
| 2830 | + check_reset_complete(hcd, wIndex); |
| 2831 | + } |
| 2832 | + /* |
| 2833 | + * Even if OWNER is set, there's no harm letting hub_wq |
| 2834 | + * see the wPortStatus values (they should all be 0 except |
| 2835 | + * for PORT_POWER anyway). |
| 2836 | + */ |
| 2837 | + |
| 2838 | + if (isp1760_hcd_is_set(hcd, PORT_OWNER)) |
| 2839 | + printf("PORT_OWNER is set\n"); |
| 2840 | + |
| 2841 | + if (isp1760_hcd_is_set(hcd, PORT_CONNECT)) { |
| 2842 | + status |= USB_PORT_STAT_CONNECTION; |
| 2843 | + |
| 2844 | + /* status may be from integrated TT */ |
| 2845 | + status |= USB_PORT_STAT_HIGH_SPEED; |
| 2846 | + } |
| 2847 | + if (isp1760_hcd_is_set(hcd, PORT_PE)) |
| 2848 | + status |= USB_PORT_STAT_ENABLE; |
| 2849 | + if (isp1760_hcd_is_set(hcd, PORT_SUSPEND) && |
| 2850 | + isp1760_hcd_is_set(hcd, PORT_RESUME)) |
| 2851 | + status |= USB_PORT_STAT_SUSPEND; |
| 2852 | + if (isp1760_hcd_is_set(hcd, PORT_RESET)) |
| 2853 | + status |= USB_PORT_STAT_RESET; |
| 2854 | + if (isp1760_hcd_is_set(hcd, PORT_POWER)) |
| 2855 | + status |= USB_PORT_STAT_POWER; |
| 2856 | + |
| 2857 | + put_unaligned(cpu_to_le32(status), (__le32 *) buf); |
| 2858 | + break; |
| 2859 | + case SetHubFeature: |
| 2860 | + switch (wValue) { |
| 2861 | + case C_HUB_LOCAL_POWER: |
| 2862 | + case C_HUB_OVER_CURRENT: |
| 2863 | + /* no hub-wide feature/status flags */ |
| 2864 | + break; |
| 2865 | + default: |
| 2866 | + goto error; |
| 2867 | + } |
| 2868 | + break; |
| 2869 | + case SetPortFeature: |
| 2870 | + wIndex &= 0xff; |
| 2871 | + if (!wIndex || wIndex > ports) |
| 2872 | + goto error; |
| 2873 | + wIndex--; |
| 2874 | + |
| 2875 | + if (isp1760_hcd_is_set(hcd, PORT_OWNER)) |
| 2876 | + break; |
| 2877 | + |
| 2878 | + switch (wValue) { |
| 2879 | + case USB_PORT_FEAT_ENABLE: |
| 2880 | + isp1760_hcd_set(hcd, PORT_PE); |
| 2881 | + break; |
| 2882 | + |
| 2883 | + case USB_PORT_FEAT_SUSPEND: |
| 2884 | + if (!isp1760_hcd_is_set(hcd, PORT_PE) || |
| 2885 | + isp1760_hcd_is_set(hcd, PORT_RESET)) |
| 2886 | + goto error; |
| 2887 | + |
| 2888 | + isp1760_hcd_set(hcd, PORT_SUSPEND); |
| 2889 | + break; |
| 2890 | + case USB_PORT_FEAT_POWER: |
| 2891 | + if (isp1760_hcd_ppc_is_set(hcd)) |
| 2892 | + isp1760_hcd_set(hcd, PORT_POWER); |
| 2893 | + break; |
| 2894 | + case USB_PORT_FEAT_RESET: |
| 2895 | + if (isp1760_hcd_is_set(hcd, PORT_RESUME)) |
| 2896 | + goto error; |
| 2897 | + /* line status bits may report this as low speed, |
| 2898 | + * which can be fine if this root hub has a |
| 2899 | + * transaction translator built in. |
| 2900 | + */ |
| 2901 | + if ((isp1760_hcd_is_set(hcd, PORT_CONNECT) && |
| 2902 | + !isp1760_hcd_is_set(hcd, PORT_PE)) && |
| 2903 | + (isp1760_hcd_read(hcd, PORT_LSTATUS) == 1)) { |
| 2904 | + isp1760_hcd_set(hcd, PORT_OWNER); |
| 2905 | + } else { |
| 2906 | + isp1760_hcd_set(hcd, PORT_RESET); |
| 2907 | + isp1760_hcd_clear(hcd, PORT_PE); |
| 2908 | + |
| 2909 | + priv->reset_done = get_timer(0) + 50; |
| 2910 | + } |
| 2911 | + break; |
| 2912 | + default: |
| 2913 | + goto error; |
| 2914 | + } |
| 2915 | + break; |
| 2916 | + |
| 2917 | + default: |
| 2918 | + printf("root: unknown request: 0x%0x\n", typeReq); |
| 2919 | + goto error; |
| 2920 | + } |
| 2921 | + spin_unlock_irqrestore(&priv->lock, flags); |
| 2922 | + |
| 2923 | + if (src_len) { |
| 2924 | + length = min(src_len, length); |
| 2925 | + |
| 2926 | + if (src != NULL && length > 0) |
| 2927 | + memcpy(buffer, src, length); |
| 2928 | + else |
| 2929 | + printf("zero copy USB descriptor\n"); |
| 2930 | + } |
| 2931 | + |
| 2932 | + dev->act_len = length; |
| 2933 | + dev->status = 0; |
| 2934 | + |
| 2935 | + return 0; |
| 2936 | + |
| 2937 | +error: |
| 2938 | + /* "stall" on error */ |
| 2939 | + dev->act_len = 0; |
| 2940 | + dev->status = USB_ST_STALLED; |
| 2941 | + return -EPIPE; |
| 2942 | +} |
| 2943 | + |
| 2944 | +#ifndef __UBOOT__ |
| 2945 | +static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) |
| 2946 | +{ |
| 2947 | + u32 status = 0; |
| 2948 | + int retval = 1; |
| 2949 | + |
| 2950 | + /* init status to no-changes */ |
| 2951 | + buf[0] = 0; |
| 2952 | + |
| 2953 | + if (isp1760_hcd_is_set(hcd, PORT_OWNER) && |
| 2954 | + isp1760_hcd_is_set(hcd, PORT_CSC)) { |
| 2955 | + isp1760_hcd_clear(hcd, PORT_CSC); |
| 2956 | + goto done; |
| 2957 | + } |
| 2958 | + |
| 2959 | +done: |
| 2960 | + return status ? retval : 0; |
| 2961 | +} |
| 2962 | + |
| 2963 | +static void isp1760_endpoint_disable(struct usb_hcd *hcd, |
| 2964 | + struct usb_host_endpoint *ep) |
| 2965 | +{ |
| 2966 | + struct isp1760_qh *qh, *qh_iter; |
| 2967 | + unsigned long spinflags; |
| 2968 | + int i; |
| 2969 | + |
| 2970 | + qh = ep->hcpriv; |
| 2971 | + if (!qh) |
| 2972 | + return; |
| 2973 | + |
| 2974 | + WARN_ON(!list_empty(&qh->qtd_list)); |
| 2975 | + |
| 2976 | + for (i = 0; i < QH_END; i++) |
| 2977 | + list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list) |
| 2978 | + if (qh_iter == qh) { |
| 2979 | + list_del(&qh_iter->qh_list); |
| 2980 | + i = QH_END; |
| 2981 | + break; |
| 2982 | + } |
| 2983 | + qh_free(qh); |
| 2984 | + ep->hcpriv = NULL; |
| 2985 | + |
| 2986 | + schedule_ptds(hcd); |
| 2987 | +} |
| 2988 | + |
| 2989 | +static int isp1760_get_frame(struct usb_hcd *hcd) |
| 2990 | +{ |
| 2991 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 2992 | + u32 fr; |
| 2993 | + |
| 2994 | + fr = isp1760_hcd_read(hcd, HC_FRINDEX); |
| 2995 | + return (fr >> 3) % priv->periodic_size; |
| 2996 | +} |
| 2997 | + |
| 2998 | +static void isp1760_stop(struct usb_hcd *hcd) |
| 2999 | +{ |
| 3000 | + struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 3001 | + |
| 3002 | + msleep(20); |
| 3003 | + |
| 3004 | + spin_lock_irq(&priv->lock); |
| 3005 | + ehci_reset(hcd); |
| 3006 | + /* Disable IRQ */ |
| 3007 | + isp1760_hcd_clear(hcd, HW_GLOBAL_INTR_EN); |
| 3008 | + spin_unlock_irq(&priv->lock); |
| 3009 | + |
| 3010 | + isp1760_hcd_clear(hcd, FLAG_CF); |
| 3011 | +} |
| 3012 | + |
| 3013 | +static void isp1760_shutdown(struct usb_hcd *hcd) |
| 3014 | +{ |
| 3015 | + isp1760_stop(hcd); |
| 3016 | + |
| 3017 | + isp1760_hcd_clear(hcd, HW_GLOBAL_INTR_EN); |
| 3018 | + |
| 3019 | + isp1760_hcd_clear(hcd, CMD_RUN); |
| 3020 | +} |
| 3021 | + |
| 3022 | +static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd, |
| 3023 | + struct usb_host_endpoint *ep) |
| 3024 | +{ |
| 3025 | + struct isp1760_qh *qh = ep->hcpriv; |
| 3026 | + unsigned long spinflags; |
| 3027 | + |
| 3028 | + if (!qh) |
| 3029 | + return; |
| 3030 | + |
| 3031 | + qh->tt_buffer_dirty = 0; |
| 3032 | + schedule_ptds(hcd); |
| 3033 | +} |
| 3034 | + |
| 3035 | + |
| 3036 | +static const struct hc_driver isp1760_hc_driver = { |
| 3037 | + .description = "isp1760-hcd", |
| 3038 | + .product_desc = "NXP ISP1760 USB Host Controller", |
| 3039 | + .hcd_priv_size = sizeof(struct isp1760_hcd *), |
| 3040 | + .irq = isp1760_irq, |
| 3041 | + .flags = HCD_MEMORY | HCD_USB2, |
| 3042 | + .reset = isp1760_hc_setup, |
| 3043 | + .start = isp1760_run, |
| 3044 | + .stop = isp1760_stop, |
| 3045 | + .shutdown = isp1760_shutdown, |
| 3046 | + .urb_enqueue = isp1760_urb_enqueue, |
| 3047 | + .urb_dequeue = isp1760_urb_dequeue, |
| 3048 | + .endpoint_disable = isp1760_endpoint_disable, |
| 3049 | + .get_frame_number = isp1760_get_frame, |
| 3050 | + .hub_status_data = isp1760_hub_status_data, |
| 3051 | + .hub_control = isp1760_hub_control, |
| 3052 | + .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete, |
| 3053 | +}; |
| 3054 | +#endif // __UBOOT__ |
| 3055 | + |
| 3056 | +int __init isp1760_init_kmem_once(void) |
| 3057 | +{ |
| 3058 | + urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem", |
| 3059 | + sizeof(struct urb_listitem), 0, SLAB_TEMPORARY | |
| 3060 | + SLAB_MEM_SPREAD, NULL); |
| 3061 | + |
| 3062 | + if (!urb_listitem_cachep) |
| 3063 | + return -ENOMEM; |
| 3064 | + |
| 3065 | + qtd_cachep = kmem_cache_create("isp1760_qtd", |
| 3066 | + sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY | |
| 3067 | + SLAB_MEM_SPREAD, NULL); |
| 3068 | + |
| 3069 | + if (!qtd_cachep) |
| 3070 | + return -ENOMEM; |
| 3071 | + |
| 3072 | + qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh), |
| 3073 | + 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL); |
| 3074 | + |
| 3075 | + if (!qh_cachep) { |
| 3076 | + kmem_cache_destroy(qtd_cachep); |
| 3077 | + return -ENOMEM; |
| 3078 | + } |
| 3079 | + |
| 3080 | + return 0; |
| 3081 | +} |
| 3082 | + |
| 3083 | +void isp1760_deinit_kmem_cache(void) |
| 3084 | +{ |
| 3085 | + kmem_cache_destroy(qtd_cachep); |
| 3086 | + kmem_cache_destroy(qh_cachep); |
| 3087 | + kmem_cache_destroy(urb_listitem_cachep); |
| 3088 | +} |
| 3089 | + |
| 3090 | +int isp1760_hcd_lowlevel_init(struct isp1760_hcd *priv) |
| 3091 | +{ |
| 3092 | + int ret; |
| 3093 | + |
| 3094 | + ret = isp1760_hc_setup(priv->hcd); |
| 3095 | + if (ret < 0) |
| 3096 | + return ret; |
| 3097 | + |
| 3098 | + ret = isp1760_run(priv->hcd); |
| 3099 | + if (ret < 0) |
| 3100 | + return ret; |
| 3101 | + |
| 3102 | + return 0; |
| 3103 | +} |
| 3104 | + |
| 3105 | +static const struct usb_urb_ops isp1760_urb_ops = { |
| 3106 | + .urb_enqueue = isp1760_urb_enqueue, |
| 3107 | + .urb_dequeue = isp1760_urb_dequeue, |
| 3108 | + .hub_control = isp1760_hub_control, |
| 3109 | + .isr = isp1760_irq, |
| 3110 | +}; |
| 3111 | + |
| 3112 | +int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem, |
| 3113 | + int irq, unsigned long irqflags, |
| 3114 | + struct udevice *dev) |
| 3115 | +{ |
| 3116 | + const struct isp1760_memory_layout *mem_layout = priv->memory_layout; |
| 3117 | + struct isp1760_host_data *host = dev_get_priv(dev); |
| 3118 | + struct usb_hcd *hcd = &host->hcd; |
| 3119 | + int ret; |
| 3120 | + |
| 3121 | + priv->hcd = hcd; |
| 3122 | + |
| 3123 | + hcd->hcd_priv = priv; |
| 3124 | + |
| 3125 | + priv->hcd = hcd; |
| 3126 | + |
| 3127 | + hcd->urb_ops = &isp1760_urb_ops; |
| 3128 | + |
| 3129 | + priv->atl_slots = kcalloc(mem_layout->slot_num, |
| 3130 | + sizeof(struct isp1760_slotinfo), GFP_KERNEL); |
| 3131 | + if (!priv->atl_slots) |
| 3132 | + return -ENOMEM; |
| 3133 | + |
| 3134 | + priv->int_slots = kcalloc(mem_layout->slot_num, |
| 3135 | + sizeof(struct isp1760_slotinfo), GFP_KERNEL); |
| 3136 | + if (!priv->int_slots) { |
| 3137 | + ret = -ENOMEM; |
| 3138 | + goto free_atl_slots; |
| 3139 | + } |
| 3140 | + |
| 3141 | + host->host_speed = USB_SPEED_HIGH; |
| 3142 | + |
| 3143 | + init_memory(priv); |
| 3144 | + |
| 3145 | + return 0; |
| 3146 | + |
| 3147 | +free_atl_slots: |
| 3148 | + kfree(priv->atl_slots); |
| 3149 | + |
| 3150 | + return ret; |
| 3151 | +} |
| 3152 | + |
| 3153 | +void isp1760_hcd_unregister(struct isp1760_hcd *priv) |
| 3154 | +{ |
| 3155 | + struct isp1760_qh *qh, *qh_next; |
| 3156 | + int i; |
| 3157 | + |
| 3158 | + for (i = 0; i < QH_END; i++) |
| 3159 | + list_for_each_entry_safe(qh, qh_next, &priv->qh_list[i], |
| 3160 | + qh_list) { |
| 3161 | + qtd_list_free(&qh->qtd_list); |
| 3162 | + list_del(&qh->qh_list); |
| 3163 | + qh_free(qh); |
| 3164 | + } |
| 3165 | + |
| 3166 | + kfree(priv->atl_slots); |
| 3167 | + kfree(priv->int_slots); |
| 3168 | +} |
| 3169 | diff --git a/drivers/usb/isp1760/isp1760-hcd.h b/drivers/usb/isp1760/isp1760-hcd.h |
| 3170 | new file mode 100644 |
| 3171 | index 000000000000..00f5ca8c1f75 |
| 3172 | --- /dev/null |
| 3173 | +++ b/drivers/usb/isp1760/isp1760-hcd.h |
| 3174 | @@ -0,0 +1,82 @@ |
| 3175 | +/* SPDX-License-Identifier: GPL-2.0 */ |
| 3176 | +#ifndef _ISP1760_HCD_H_ |
| 3177 | +#define _ISP1760_HCD_H_ |
| 3178 | + |
| 3179 | +#include <regmap.h> |
| 3180 | + |
| 3181 | +#include "isp1760-regs.h" |
| 3182 | + |
| 3183 | +struct isp1760_qh; |
| 3184 | +struct isp1760_qtd; |
| 3185 | +struct resource; |
| 3186 | +struct usb_hcd; |
| 3187 | + |
| 3188 | +struct isp1760_slotinfo { |
| 3189 | + struct isp1760_qh *qh; |
| 3190 | + struct isp1760_qtd *qtd; |
| 3191 | + unsigned long timestamp; |
| 3192 | +}; |
| 3193 | + |
| 3194 | +/* chip memory management */ |
| 3195 | +#define ISP176x_BLOCK_MAX (32 + 20 + 4) |
| 3196 | +#define ISP176x_BLOCK_NUM 3 |
| 3197 | + |
| 3198 | +struct isp1760_memory_layout { |
| 3199 | + unsigned int blocks[ISP176x_BLOCK_NUM]; |
| 3200 | + unsigned int blocks_size[ISP176x_BLOCK_NUM]; |
| 3201 | + |
| 3202 | + unsigned int slot_num; |
| 3203 | + unsigned int payload_blocks; |
| 3204 | + unsigned int payload_area_size; |
| 3205 | +}; |
| 3206 | + |
| 3207 | +struct isp1760_memory_chunk { |
| 3208 | + unsigned int start; |
| 3209 | + unsigned int size; |
| 3210 | + unsigned int free; |
| 3211 | +}; |
| 3212 | + |
| 3213 | +enum isp1760_queue_head_types { |
| 3214 | + QH_CONTROL, |
| 3215 | + QH_BULK, |
| 3216 | + QH_INTERRUPT, |
| 3217 | + QH_END |
| 3218 | +}; |
| 3219 | + |
| 3220 | +struct isp1760_hcd { |
| 3221 | + struct usb_hcd *hcd; |
| 3222 | + struct udevice *dev; |
| 3223 | + |
| 3224 | + void __iomem *base; |
| 3225 | + |
| 3226 | + struct regmap *regs; |
| 3227 | + struct regmap_field *fields[HC_FIELD_MAX]; |
| 3228 | + |
| 3229 | + bool is_isp1763; |
| 3230 | + const struct isp1760_memory_layout *memory_layout; |
| 3231 | + |
| 3232 | + spinlock_t lock; |
| 3233 | + struct isp1760_slotinfo *atl_slots; |
| 3234 | + int atl_done_map; |
| 3235 | + struct isp1760_slotinfo *int_slots; |
| 3236 | + int int_done_map; |
| 3237 | + struct isp1760_memory_chunk memory_pool[ISP176x_BLOCK_MAX]; |
| 3238 | + struct list_head qh_list[QH_END]; |
| 3239 | + |
| 3240 | + /* periodic schedule support */ |
| 3241 | +#define DEFAULT_I_TDPS 1024 |
| 3242 | + unsigned periodic_size; |
| 3243 | + unsigned i_thresh; |
| 3244 | + unsigned long reset_done; |
| 3245 | + unsigned long next_statechange; |
| 3246 | +}; |
| 3247 | + |
| 3248 | +int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem, |
| 3249 | + int irq, unsigned long irqflags, struct udevice *dev); |
| 3250 | +void isp1760_hcd_unregister(struct isp1760_hcd *priv); |
| 3251 | +int isp1760_hcd_lowlevel_init(struct isp1760_hcd *priv); |
| 3252 | + |
| 3253 | +int isp1760_init_kmem_once(void); |
| 3254 | +void isp1760_deinit_kmem_cache(void); |
| 3255 | + |
| 3256 | +#endif /* _ISP1760_HCD_H_ */ |
| 3257 | diff --git a/drivers/usb/isp1760/isp1760-if.c b/drivers/usb/isp1760/isp1760-if.c |
| 3258 | new file mode 100644 |
| 3259 | index 000000000000..c610da6b23fb |
| 3260 | --- /dev/null |
| 3261 | +++ b/drivers/usb/isp1760/isp1760-if.c |
| 3262 | @@ -0,0 +1,127 @@ |
| 3263 | +// SPDX-License-Identifier: GPL-2.0 |
| 3264 | +/* |
| 3265 | + * Copyright 2021 Linaro, Rui Miguel Silva <rui.silva@linaro.org> |
| 3266 | + * |
| 3267 | + * based on original code from: |
| 3268 | + * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de> |
| 3269 | + */ |
| 3270 | + |
| 3271 | +#include <common.h> |
| 3272 | +#include <dm.h> |
| 3273 | +#include <dm/device-internal.h> |
| 3274 | +#include <dm/device_compat.h> |
| 3275 | +#include <dm/devres.h> |
| 3276 | +#include <dm/lists.h> |
| 3277 | +#include <linux/bug.h> |
| 3278 | +#include <linux/io.h> |
| 3279 | +#include <linux/kernel.h> |
| 3280 | +#include <linux/usb/otg.h> |
| 3281 | +#include <log.h> |
| 3282 | +#include <usb.h> |
| 3283 | + |
| 3284 | +#include "isp1760-core.h" |
| 3285 | +#include "isp1760-regs.h" |
| 3286 | +#include "isp1760-uboot.h" |
| 3287 | + |
| 3288 | + |
| 3289 | +static int isp1760_of_to_plat(struct udevice *dev) |
| 3290 | +{ |
| 3291 | + struct isp1760_device *isp = dev_get_plat(dev); |
| 3292 | + unsigned int devflags = 0; |
| 3293 | + u32 bus_width = 0; |
| 3294 | + ofnode dp; |
| 3295 | + |
| 3296 | + |
| 3297 | + if (!dev_has_ofnode(dev)) { |
| 3298 | + /* select isp1763 as the default device */ |
| 3299 | + devflags = ISP1760_FLAG_ISP1763 | ISP1760_FLAG_BUS_WIDTH_16; |
| 3300 | + pr_err("isp1760: no platform data\n"); |
| 3301 | + goto isp_setup; |
| 3302 | + } |
| 3303 | + |
| 3304 | + dp = dev_ofnode(dev); |
| 3305 | + |
| 3306 | + if (ofnode_device_is_compatible(dp, "nxp,usb-isp1761")) |
| 3307 | + devflags |= ISP1760_FLAG_ISP1761; |
| 3308 | + |
| 3309 | + if (ofnode_device_is_compatible(dp, "nxp,usb-isp1763")) |
| 3310 | + devflags |= ISP1760_FLAG_ISP1763; |
| 3311 | + |
| 3312 | + /* |
| 3313 | + * Some systems wire up only 8 of 16 data lines or |
| 3314 | + * 16 of the 32 data lines |
| 3315 | + */ |
| 3316 | + bus_width = ofnode_read_u32_default(dp, "bus-width", 16); |
| 3317 | + if (bus_width == 16) |
| 3318 | + devflags |= ISP1760_FLAG_BUS_WIDTH_16; |
| 3319 | + else if (bus_width == 8) |
| 3320 | + devflags |= ISP1760_FLAG_BUS_WIDTH_8; |
| 3321 | + |
| 3322 | + if (usb_get_dr_mode(dev_ofnode(dev)) == USB_DR_MODE_PERIPHERAL) |
| 3323 | + devflags |= ISP1760_FLAG_PERIPHERAL_EN; |
| 3324 | + |
| 3325 | + if (ofnode_read_bool(dp, "analog-oc")) |
| 3326 | + devflags |= ISP1760_FLAG_ANALOG_OC; |
| 3327 | + |
| 3328 | + if (ofnode_read_bool(dp, "dack-polarity")) |
| 3329 | + devflags |= ISP1760_FLAG_DACK_POL_HIGH; |
| 3330 | + |
| 3331 | + if (ofnode_read_bool(dp, "dreq-polarity")) |
| 3332 | + devflags |= ISP1760_FLAG_DREQ_POL_HIGH; |
| 3333 | + |
| 3334 | +isp_setup: |
| 3335 | + isp->devflags = devflags; |
| 3336 | + isp->dev = dev; |
| 3337 | + |
| 3338 | + return 0; |
| 3339 | +} |
| 3340 | + |
| 3341 | +static int isp1760_plat_probe(struct udevice *dev) |
| 3342 | +{ |
| 3343 | + struct isp1760_device *isp = dev_get_plat(dev); |
| 3344 | + struct resource mem_res; |
| 3345 | + struct resource irq_res; |
| 3346 | + int ret; |
| 3347 | + |
| 3348 | + dev_read_resource(dev, 0, &mem_res); |
| 3349 | + dev_read_resource(dev, 1, &irq_res); |
| 3350 | + |
| 3351 | + isp1760_init_kmem_once(); |
| 3352 | + |
| 3353 | + ret = isp1760_register(isp, &mem_res, irq_res.start, irq_res.flags); |
| 3354 | + if (ret < 0) { |
| 3355 | + isp1760_deinit_kmem_cache(); |
| 3356 | + return ret; |
| 3357 | + } |
| 3358 | + |
| 3359 | + return 0; |
| 3360 | +} |
| 3361 | + |
| 3362 | +static int isp1760_plat_remove(struct udevice *dev) |
| 3363 | +{ |
| 3364 | + struct isp1760_device *isp = dev_get_plat(dev); |
| 3365 | + |
| 3366 | + isp1760_deinit_kmem_cache(); |
| 3367 | + isp1760_unregister(isp); |
| 3368 | + |
| 3369 | + return 0; |
| 3370 | +} |
| 3371 | + |
| 3372 | +static const struct udevice_id isp1760_ids[] = { |
| 3373 | + { .compatible = "nxp,usb-isp1760", }, |
| 3374 | + { .compatible = "nxp,usb-isp1761", }, |
| 3375 | + { .compatible = "nxp,usb-isp1763", }, |
| 3376 | + { }, |
| 3377 | +}; |
| 3378 | + |
| 3379 | +U_BOOT_DRIVER(isp1760) = { |
| 3380 | + .name = "isp1760", |
| 3381 | + .id = UCLASS_USB, |
| 3382 | + .of_match = isp1760_ids, |
| 3383 | + .of_to_plat = isp1760_of_to_plat, |
| 3384 | + .ops = &isp1760_usb_ops, |
| 3385 | + .probe = isp1760_plat_probe, |
| 3386 | + .remove = isp1760_plat_remove, |
| 3387 | + .plat_auto = sizeof(struct isp1760_device), |
| 3388 | + .priv_auto = sizeof(struct isp1760_host_data), |
| 3389 | +}; |
| 3390 | diff --git a/drivers/usb/isp1760/isp1760-regs.h b/drivers/usb/isp1760/isp1760-regs.h |
| 3391 | new file mode 100644 |
| 3392 | index 000000000000..94ea60c20b2a |
| 3393 | --- /dev/null |
| 3394 | +++ b/drivers/usb/isp1760/isp1760-regs.h |
| 3395 | @@ -0,0 +1,292 @@ |
| 3396 | +/* SPDX-License-Identifier: GPL-2.0 */ |
| 3397 | +/* |
| 3398 | + * Driver for the NXP ISP1760 chip |
| 3399 | + * |
| 3400 | + * Copyright 2021 Linaro, Rui Miguel Silva |
| 3401 | + * Copyright 2014 Laurent Pinchart |
| 3402 | + * Copyright 2007 Sebastian Siewior |
| 3403 | + * |
| 3404 | + * Contacts: |
| 3405 | + * Sebastian Siewior <bigeasy@linutronix.de> |
| 3406 | + * Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
| 3407 | + * Rui Miguel Silva <rui.silva@linaro.org> |
| 3408 | + */ |
| 3409 | + |
| 3410 | +#ifndef _ISP176x_REGS_H_ |
| 3411 | +#define _ISP176x_REGS_H_ |
| 3412 | + |
| 3413 | +/* ----------------------------------------------------------------------------- |
| 3414 | + * Host Controller |
| 3415 | + */ |
| 3416 | + |
| 3417 | +/* ISP1760/31 */ |
| 3418 | +/* EHCI capability registers */ |
| 3419 | +#define ISP176x_HC_VERSION 0x002 |
| 3420 | +#define ISP176x_HC_HCSPARAMS 0x004 |
| 3421 | +#define ISP176x_HC_HCCPARAMS 0x008 |
| 3422 | + |
| 3423 | +/* EHCI operational registers */ |
| 3424 | +#define ISP176x_HC_USBCMD 0x020 |
| 3425 | +#define ISP176x_HC_USBSTS 0x024 |
| 3426 | +#define ISP176x_HC_FRINDEX 0x02c |
| 3427 | + |
| 3428 | +#define ISP176x_HC_CONFIGFLAG 0x060 |
| 3429 | +#define ISP176x_HC_PORTSC1 0x064 |
| 3430 | + |
| 3431 | +#define ISP176x_HC_ISO_PTD_DONEMAP 0x130 |
| 3432 | +#define ISP176x_HC_ISO_PTD_SKIPMAP 0x134 |
| 3433 | +#define ISP176x_HC_ISO_PTD_LASTPTD 0x138 |
| 3434 | +#define ISP176x_HC_INT_PTD_DONEMAP 0x140 |
| 3435 | +#define ISP176x_HC_INT_PTD_SKIPMAP 0x144 |
| 3436 | +#define ISP176x_HC_INT_PTD_LASTPTD 0x148 |
| 3437 | +#define ISP176x_HC_ATL_PTD_DONEMAP 0x150 |
| 3438 | +#define ISP176x_HC_ATL_PTD_SKIPMAP 0x154 |
| 3439 | +#define ISP176x_HC_ATL_PTD_LASTPTD 0x158 |
| 3440 | + |
| 3441 | +/* Configuration Register */ |
| 3442 | +#define ISP176x_HC_HW_MODE_CTRL 0x300 |
| 3443 | +#define ISP176x_HC_CHIP_ID 0x304 |
| 3444 | +#define ISP176x_HC_SCRATCH 0x308 |
| 3445 | +#define ISP176x_HC_RESET 0x30c |
| 3446 | +#define ISP176x_HC_BUFFER_STATUS 0x334 |
| 3447 | +#define ISP176x_HC_MEMORY 0x33c |
| 3448 | + |
| 3449 | +/* Interrupt Register */ |
| 3450 | +#define ISP176x_HC_INTERRUPT 0x310 |
| 3451 | +#define ISP176x_HC_INTERRUPT_ENABLE 0x314 |
| 3452 | +#define ISP176x_HC_ISO_IRQ_MASK_OR 0x318 |
| 3453 | +#define ISP176x_HC_INT_IRQ_MASK_OR 0x31c |
| 3454 | +#define ISP176x_HC_ATL_IRQ_MASK_OR 0x320 |
| 3455 | +#define ISP176x_HC_ISO_IRQ_MASK_AND 0x324 |
| 3456 | +#define ISP176x_HC_INT_IRQ_MASK_AND 0x328 |
| 3457 | +#define ISP176x_HC_ATL_IRQ_MASK_AND 0x32c |
| 3458 | + |
| 3459 | +#define ISP176x_HC_OTG_CTRL_SET 0x374 |
| 3460 | +#define ISP176x_HC_OTG_CTRL_CLEAR 0x376 |
| 3461 | + |
| 3462 | +enum isp176x_host_controller_fields { |
| 3463 | + /* HC_PORTSC1 */ |
| 3464 | + PORT_OWNER, PORT_POWER, PORT_LSTATUS, PORT_RESET, PORT_SUSPEND, |
| 3465 | + PORT_RESUME, PORT_PE, PORT_CSC, PORT_CONNECT, |
| 3466 | + /* HC_HCSPARAMS */ |
| 3467 | + HCS_PPC, HCS_N_PORTS, |
| 3468 | + /* HC_HCCPARAMS */ |
| 3469 | + HCC_ISOC_CACHE, HCC_ISOC_THRES, |
| 3470 | + /* HC_USBCMD */ |
| 3471 | + CMD_LRESET, CMD_RESET, CMD_RUN, |
| 3472 | + /* HC_USBSTS */ |
| 3473 | + STS_PCD, |
| 3474 | + /* HC_FRINDEX */ |
| 3475 | + HC_FRINDEX, |
| 3476 | + /* HC_CONFIGFLAG */ |
| 3477 | + FLAG_CF, |
| 3478 | + /* ISO/INT/ATL PTD */ |
| 3479 | + HC_ISO_PTD_DONEMAP, HC_ISO_PTD_SKIPMAP, HC_ISO_PTD_LASTPTD, |
| 3480 | + HC_INT_PTD_DONEMAP, HC_INT_PTD_SKIPMAP, HC_INT_PTD_LASTPTD, |
| 3481 | + HC_ATL_PTD_DONEMAP, HC_ATL_PTD_SKIPMAP, HC_ATL_PTD_LASTPTD, |
| 3482 | + /* HC_HW_MODE_CTRL */ |
| 3483 | + ALL_ATX_RESET, HW_ANA_DIGI_OC, HW_DEV_DMA, HW_COMN_IRQ, HW_COMN_DMA, |
| 3484 | + HW_DATA_BUS_WIDTH, HW_DACK_POL_HIGH, HW_DREQ_POL_HIGH, HW_INTR_HIGH_ACT, |
| 3485 | + HW_INTF_LOCK, HW_INTR_EDGE_TRIG, HW_GLOBAL_INTR_EN, |
| 3486 | + /* HC_CHIP_ID */ |
| 3487 | + HC_CHIP_ID_HIGH, HC_CHIP_ID_LOW, HC_CHIP_REV, |
| 3488 | + /* HC_SCRATCH */ |
| 3489 | + HC_SCRATCH, |
| 3490 | + /* HC_RESET */ |
| 3491 | + SW_RESET_RESET_ATX, SW_RESET_RESET_HC, SW_RESET_RESET_ALL, |
| 3492 | + /* HC_BUFFER_STATUS */ |
| 3493 | + ISO_BUF_FILL, INT_BUF_FILL, ATL_BUF_FILL, |
| 3494 | + /* HC_MEMORY */ |
| 3495 | + MEM_BANK_SEL, MEM_START_ADDR, |
| 3496 | + /* HC_DATA */ |
| 3497 | + HC_DATA, |
| 3498 | + /* HC_INTERRUPT */ |
| 3499 | + HC_INTERRUPT, |
| 3500 | + /* HC_INTERRUPT_ENABLE */ |
| 3501 | + HC_INT_IRQ_ENABLE, HC_ATL_IRQ_ENABLE, |
| 3502 | + /* INTERRUPT MASKS */ |
| 3503 | + HC_ISO_IRQ_MASK_OR, HC_INT_IRQ_MASK_OR, HC_ATL_IRQ_MASK_OR, |
| 3504 | + HC_ISO_IRQ_MASK_AND, HC_INT_IRQ_MASK_AND, HC_ATL_IRQ_MASK_AND, |
| 3505 | + /* HW_OTG_CTRL_SET */ |
| 3506 | + HW_OTG_DISABLE, HW_SW_SEL_HC_DC, HW_VBUS_DRV, HW_SEL_CP_EXT, |
| 3507 | + HW_DM_PULLDOWN, HW_DP_PULLDOWN, HW_DP_PULLUP, HW_HC_2_DIS, |
| 3508 | + /* HW_OTG_CTRL_CLR */ |
| 3509 | + HW_OTG_DISABLE_CLEAR, HW_SW_SEL_HC_DC_CLEAR, HW_VBUS_DRV_CLEAR, |
| 3510 | + HW_SEL_CP_EXT_CLEAR, HW_DM_PULLDOWN_CLEAR, HW_DP_PULLDOWN_CLEAR, |
| 3511 | + HW_DP_PULLUP_CLEAR, HW_HC_2_DIS_CLEAR, |
| 3512 | + /* Last element */ |
| 3513 | + HC_FIELD_MAX, |
| 3514 | +}; |
| 3515 | + |
| 3516 | +/* ISP1763 */ |
| 3517 | +/* EHCI operational registers */ |
| 3518 | +#define ISP1763_HC_USBCMD 0x8c |
| 3519 | +#define ISP1763_HC_USBSTS 0x90 |
| 3520 | +#define ISP1763_HC_FRINDEX 0x98 |
| 3521 | + |
| 3522 | +#define ISP1763_HC_CONFIGFLAG 0x9c |
| 3523 | +#define ISP1763_HC_PORTSC1 0xa0 |
| 3524 | + |
| 3525 | +#define ISP1763_HC_ISO_PTD_DONEMAP 0xa4 |
| 3526 | +#define ISP1763_HC_ISO_PTD_SKIPMAP 0xa6 |
| 3527 | +#define ISP1763_HC_ISO_PTD_LASTPTD 0xa8 |
| 3528 | +#define ISP1763_HC_INT_PTD_DONEMAP 0xaa |
| 3529 | +#define ISP1763_HC_INT_PTD_SKIPMAP 0xac |
| 3530 | +#define ISP1763_HC_INT_PTD_LASTPTD 0xae |
| 3531 | +#define ISP1763_HC_ATL_PTD_DONEMAP 0xb0 |
| 3532 | +#define ISP1763_HC_ATL_PTD_SKIPMAP 0xb2 |
| 3533 | +#define ISP1763_HC_ATL_PTD_LASTPTD 0xb4 |
| 3534 | + |
| 3535 | +/* Configuration Register */ |
| 3536 | +#define ISP1763_HC_HW_MODE_CTRL 0xb6 |
| 3537 | +#define ISP1763_HC_CHIP_REV 0x70 |
| 3538 | +#define ISP1763_HC_CHIP_ID 0x72 |
| 3539 | +#define ISP1763_HC_SCRATCH 0x78 |
| 3540 | +#define ISP1763_HC_RESET 0xb8 |
| 3541 | +#define ISP1763_HC_BUFFER_STATUS 0xba |
| 3542 | +#define ISP1763_HC_MEMORY 0xc4 |
| 3543 | +#define ISP1763_HC_DATA 0xc6 |
| 3544 | + |
| 3545 | +/* Interrupt Register */ |
| 3546 | +#define ISP1763_HC_INTERRUPT 0xd4 |
| 3547 | +#define ISP1763_HC_INTERRUPT_ENABLE 0xd6 |
| 3548 | +#define ISP1763_HC_ISO_IRQ_MASK_OR 0xd8 |
| 3549 | +#define ISP1763_HC_INT_IRQ_MASK_OR 0xda |
| 3550 | +#define ISP1763_HC_ATL_IRQ_MASK_OR 0xdc |
| 3551 | +#define ISP1763_HC_ISO_IRQ_MASK_AND 0xde |
| 3552 | +#define ISP1763_HC_INT_IRQ_MASK_AND 0xe0 |
| 3553 | +#define ISP1763_HC_ATL_IRQ_MASK_AND 0xe2 |
| 3554 | + |
| 3555 | +#define ISP1763_HC_OTG_CTRL_SET 0xe4 |
| 3556 | +#define ISP1763_HC_OTG_CTRL_CLEAR 0xe6 |
| 3557 | + |
| 3558 | +/* ----------------------------------------------------------------------------- |
| 3559 | + * Peripheral Controller |
| 3560 | + */ |
| 3561 | + |
| 3562 | +#define DC_IEPTX(n) (1 << (11 + 2 * (n))) |
| 3563 | +#define DC_IEPRX(n) (1 << (10 + 2 * (n))) |
| 3564 | +#define DC_IEPRXTX(n) (3 << (10 + 2 * (n))) |
| 3565 | + |
| 3566 | +#define ISP176x_DC_CDBGMOD_ACK BIT(6) |
| 3567 | +#define ISP176x_DC_DDBGMODIN_ACK BIT(4) |
| 3568 | +#define ISP176x_DC_DDBGMODOUT_ACK BIT(2) |
| 3569 | + |
| 3570 | +#define ISP176x_DC_IEP0SETUP BIT(8) |
| 3571 | +#define ISP176x_DC_IEVBUS BIT(7) |
| 3572 | +#define ISP176x_DC_IEHS_STA BIT(5) |
| 3573 | +#define ISP176x_DC_IERESM BIT(4) |
| 3574 | +#define ISP176x_DC_IESUSP BIT(3) |
| 3575 | +#define ISP176x_DC_IEBRST BIT(0) |
| 3576 | + |
| 3577 | +#define ISP176x_DC_ENDPTYP_ISOC 0x01 |
| 3578 | +#define ISP176x_DC_ENDPTYP_BULK 0x02 |
| 3579 | +#define ISP176x_DC_ENDPTYP_INTERRUPT 0x03 |
| 3580 | + |
| 3581 | +/* Initialization Registers */ |
| 3582 | +#define ISP176x_DC_ADDRESS 0x0200 |
| 3583 | +#define ISP176x_DC_MODE 0x020c |
| 3584 | +#define ISP176x_DC_INTCONF 0x0210 |
| 3585 | +#define ISP176x_DC_DEBUG 0x0212 |
| 3586 | +#define ISP176x_DC_INTENABLE 0x0214 |
| 3587 | + |
| 3588 | +/* Data Flow Registers */ |
| 3589 | +#define ISP176x_DC_EPMAXPKTSZ 0x0204 |
| 3590 | +#define ISP176x_DC_EPTYPE 0x0208 |
| 3591 | + |
| 3592 | +#define ISP176x_DC_BUFLEN 0x021c |
| 3593 | +#define ISP176x_DC_BUFSTAT 0x021e |
| 3594 | +#define ISP176x_DC_DATAPORT 0x0220 |
| 3595 | + |
| 3596 | +#define ISP176x_DC_CTRLFUNC 0x0228 |
| 3597 | +#define ISP176x_DC_EPINDEX 0x022c |
| 3598 | + |
| 3599 | +/* DMA Registers */ |
| 3600 | +#define ISP176x_DC_DMACMD 0x0230 |
| 3601 | +#define ISP176x_DC_DMATXCOUNT 0x0234 |
| 3602 | +#define ISP176x_DC_DMACONF 0x0238 |
| 3603 | +#define ISP176x_DC_DMAHW 0x023c |
| 3604 | +#define ISP176x_DC_DMAINTREASON 0x0250 |
| 3605 | +#define ISP176x_DC_DMAINTEN 0x0254 |
| 3606 | +#define ISP176x_DC_DMAEP 0x0258 |
| 3607 | +#define ISP176x_DC_DMABURSTCOUNT 0x0264 |
| 3608 | + |
| 3609 | +/* General Registers */ |
| 3610 | +#define ISP176x_DC_INTERRUPT 0x0218 |
| 3611 | +#define ISP176x_DC_CHIPID 0x0270 |
| 3612 | +#define ISP176x_DC_FRAMENUM 0x0274 |
| 3613 | +#define ISP176x_DC_SCRATCH 0x0278 |
| 3614 | +#define ISP176x_DC_UNLOCKDEV 0x027c |
| 3615 | +#define ISP176x_DC_INTPULSEWIDTH 0x0280 |
| 3616 | +#define ISP176x_DC_TESTMODE 0x0284 |
| 3617 | + |
| 3618 | +enum isp176x_device_controller_fields { |
| 3619 | + /* DC_ADDRESS */ |
| 3620 | + DC_DEVEN, DC_DEVADDR, |
| 3621 | + /* DC_MODE */ |
| 3622 | + DC_VBUSSTAT, DC_SFRESET, DC_GLINTENA, |
| 3623 | + /* DC_INTCONF */ |
| 3624 | + DC_CDBGMOD_ACK, DC_DDBGMODIN_ACK, DC_DDBGMODOUT_ACK, DC_INTPOL, |
| 3625 | + /* DC_INTENABLE */ |
| 3626 | + DC_IEPRXTX_7, DC_IEPRXTX_6, DC_IEPRXTX_5, DC_IEPRXTX_4, DC_IEPRXTX_3, |
| 3627 | + DC_IEPRXTX_2, DC_IEPRXTX_1, DC_IEPRXTX_0, |
| 3628 | + DC_IEP0SETUP, DC_IEVBUS, DC_IEHS_STA, DC_IERESM, DC_IESUSP, DC_IEBRST, |
| 3629 | + /* DC_EPINDEX */ |
| 3630 | + DC_EP0SETUP, DC_ENDPIDX, DC_EPDIR, |
| 3631 | + /* DC_CTRLFUNC */ |
| 3632 | + DC_CLBUF, DC_VENDP, DC_DSEN, DC_STATUS, DC_STALL, |
| 3633 | + /* DC_BUFLEN */ |
| 3634 | + DC_BUFLEN, |
| 3635 | + /* DC_EPMAXPKTSZ */ |
| 3636 | + DC_FFOSZ, |
| 3637 | + /* DC_EPTYPE */ |
| 3638 | + DC_EPENABLE, DC_ENDPTYP, |
| 3639 | + /* DC_FRAMENUM */ |
| 3640 | + DC_FRAMENUM, DC_UFRAMENUM, |
| 3641 | + /* DC_CHIP_ID */ |
| 3642 | + DC_CHIP_ID_HIGH, DC_CHIP_ID_LOW, |
| 3643 | + /* DC_SCRATCH */ |
| 3644 | + DC_SCRATCH, |
| 3645 | + /* Last element */ |
| 3646 | + DC_FIELD_MAX, |
| 3647 | +}; |
| 3648 | + |
| 3649 | +/* ISP1763 */ |
| 3650 | +/* Initialization Registers */ |
| 3651 | +#define ISP1763_DC_ADDRESS 0x00 |
| 3652 | +#define ISP1763_DC_MODE 0x0c |
| 3653 | +#define ISP1763_DC_INTCONF 0x10 |
| 3654 | +#define ISP1763_DC_INTENABLE 0x14 |
| 3655 | + |
| 3656 | +/* Data Flow Registers */ |
| 3657 | +#define ISP1763_DC_EPMAXPKTSZ 0x04 |
| 3658 | +#define ISP1763_DC_EPTYPE 0x08 |
| 3659 | + |
| 3660 | +#define ISP1763_DC_BUFLEN 0x1c |
| 3661 | +#define ISP1763_DC_BUFSTAT 0x1e |
| 3662 | +#define ISP1763_DC_DATAPORT 0x20 |
| 3663 | + |
| 3664 | +#define ISP1763_DC_CTRLFUNC 0x28 |
| 3665 | +#define ISP1763_DC_EPINDEX 0x2c |
| 3666 | + |
| 3667 | +/* DMA Registers */ |
| 3668 | +#define ISP1763_DC_DMACMD 0x30 |
| 3669 | +#define ISP1763_DC_DMATXCOUNT 0x34 |
| 3670 | +#define ISP1763_DC_DMACONF 0x38 |
| 3671 | +#define ISP1763_DC_DMAHW 0x3c |
| 3672 | +#define ISP1763_DC_DMAINTREASON 0x50 |
| 3673 | +#define ISP1763_DC_DMAINTEN 0x54 |
| 3674 | +#define ISP1763_DC_DMAEP 0x58 |
| 3675 | +#define ISP1763_DC_DMABURSTCOUNT 0x64 |
| 3676 | + |
| 3677 | +/* General Registers */ |
| 3678 | +#define ISP1763_DC_INTERRUPT 0x18 |
| 3679 | +#define ISP1763_DC_CHIPID_LOW 0x70 |
| 3680 | +#define ISP1763_DC_CHIPID_HIGH 0x72 |
| 3681 | +#define ISP1763_DC_FRAMENUM 0x74 |
| 3682 | +#define ISP1763_DC_SCRATCH 0x78 |
| 3683 | +#define ISP1763_DC_UNLOCKDEV 0x7c |
| 3684 | +#define ISP1763_DC_INTPULSEWIDTH 0x80 |
| 3685 | +#define ISP1763_DC_TESTMODE 0x84 |
| 3686 | + |
| 3687 | +#endif |
| 3688 | diff --git a/drivers/usb/isp1760/isp1760-uboot.c b/drivers/usb/isp1760/isp1760-uboot.c |
| 3689 | new file mode 100644 |
| 3690 | index 000000000000..7635210fe2b4 |
| 3691 | --- /dev/null |
| 3692 | +++ b/drivers/usb/isp1760/isp1760-uboot.c |
| 3693 | @@ -0,0 +1,76 @@ |
| 3694 | +// SPDX-License-Identifier: GPL-2.0 |
| 3695 | +/* |
| 3696 | + * Driver for the NXP ISP1760 chip |
| 3697 | + * |
| 3698 | + * Copyright 2021 Linaro, Rui Miguel Silva <rui.silva@linaro.org> |
| 3699 | + * |
| 3700 | + */ |
| 3701 | + |
| 3702 | +#include <common.h> |
| 3703 | +#include <dm.h> |
| 3704 | +#include <dm/device-internal.h> |
| 3705 | +#include <dm/device_compat.h> |
| 3706 | +#include <dm/devres.h> |
| 3707 | +#include <dm/lists.h> |
| 3708 | +#include <linux/bug.h> |
| 3709 | +#include <linux/io.h> |
| 3710 | +#include <linux/kernel.h> |
| 3711 | +#include <linux/usb/otg.h> |
| 3712 | +#include <linux/usb/usb_urb_compat.h> |
| 3713 | +#include <log.h> |
| 3714 | +#include <usb.h> |
| 3715 | + |
| 3716 | +#include "isp1760-core.h" |
| 3717 | +#include "isp1760-hcd.h" |
| 3718 | +#include "isp1760-regs.h" |
| 3719 | +#include "isp1760-uboot.h" |
| 3720 | + |
| 3721 | +static int isp1760_msg_submit_control(struct udevice *dev, |
| 3722 | + struct usb_device *udev, |
| 3723 | + unsigned long pipe, void *buffer, |
| 3724 | + int length, struct devrequest *setup) |
| 3725 | +{ |
| 3726 | + struct isp1760_host_data *host = dev_get_priv(dev); |
| 3727 | + |
| 3728 | + return usb_urb_submit_control(&host->hcd, &host->urb, &host->hep, udev, |
| 3729 | + pipe, buffer, length, setup, 0, |
| 3730 | + host->host_speed); |
| 3731 | +} |
| 3732 | + |
| 3733 | +static int isp1760_msg_submit_bulk(struct udevice *dev, struct usb_device *udev, |
| 3734 | + unsigned long pipe, void *buffer, int length) |
| 3735 | +{ |
| 3736 | + struct isp1760_host_data *host = dev_get_priv(dev); |
| 3737 | + |
| 3738 | + return usb_urb_submit_bulk(&host->hcd, &host->urb, &host->hep, udev, |
| 3739 | + pipe, buffer, length); |
| 3740 | +} |
| 3741 | + |
| 3742 | +static int isp1760_msg_submit_irq(struct udevice *dev, struct usb_device *udev, |
| 3743 | + unsigned long pipe, void *buffer, int length, |
| 3744 | + int interval, bool nonblock) |
| 3745 | +{ |
| 3746 | + struct isp1760_host_data *host = dev_get_priv(dev); |
| 3747 | + |
| 3748 | + return usb_urb_submit_irq(&host->hcd, &host->urb, &host->hep, udev, |
| 3749 | + pipe, buffer, length, interval); |
| 3750 | +} |
| 3751 | + |
| 3752 | +static int isp1760_get_max_xfer_size(struct udevice *dev, size_t *size) |
| 3753 | +{ |
| 3754 | + struct isp1760_host_data *host = dev_get_priv(dev); |
| 3755 | + struct isp1760_hcd *priv = host->hcd.hcd_priv; |
| 3756 | + const struct isp1760_memory_layout *mem = priv->memory_layout; |
| 3757 | + |
| 3758 | + *size = mem->blocks_size[ISP176x_BLOCK_NUM - 1]; |
| 3759 | + |
| 3760 | + return 0; |
| 3761 | +} |
| 3762 | + |
| 3763 | + |
| 3764 | +struct dm_usb_ops isp1760_usb_ops = { |
| 3765 | + .control = isp1760_msg_submit_control, |
| 3766 | + .bulk = isp1760_msg_submit_bulk, |
| 3767 | + .interrupt = isp1760_msg_submit_irq, |
| 3768 | + .get_max_xfer_size = isp1760_get_max_xfer_size, |
| 3769 | +}; |
| 3770 | diff --git a/drivers/usb/isp1760/isp1760-uboot.h b/drivers/usb/isp1760/isp1760-uboot.h |
| 3771 | new file mode 100644 |
| 3772 | index 000000000000..2486de6f9e27 |
| 3773 | --- /dev/null |
| 3774 | +++ b/drivers/usb/isp1760/isp1760-uboot.h |
| 3775 | @@ -0,0 +1,27 @@ |
| 3776 | +// SPDX-License-Identifier: GPL-2.0 |
| 3777 | +/* |
| 3778 | + * Driver for the NXP ISP1760 chip |
| 3779 | + * |
| 3780 | + * Copyright 2021 Linaro, Rui Miguel Silva <rui.silva@linaro.org> |
| 3781 | + * |
| 3782 | + */ |
| 3783 | + |
| 3784 | +#ifndef __ISP1760_UBOOT_H__ |
| 3785 | +#define __ISP1760_UBOOT_H__ |
| 3786 | + |
| 3787 | +#include <linux/usb/usb_urb_compat.h> |
| 3788 | +#include <usb.h> |
| 3789 | + |
| 3790 | +#include "isp1760-core.h" |
| 3791 | + |
| 3792 | +struct isp1760_host_data { |
| 3793 | + struct isp1760_hcd *priv; |
| 3794 | + struct usb_hcd hcd; |
| 3795 | + enum usb_device_speed host_speed; |
| 3796 | + struct usb_host_endpoint hep; |
| 3797 | + struct urb urb; |
| 3798 | +}; |
| 3799 | + |
| 3800 | +extern struct dm_usb_ops isp1760_usb_ops; |
| 3801 | + |
| 3802 | +#endif |
| 3803 | -- |
Patrick Williams | 92b42cb | 2022-09-03 06:53:57 -0500 | [diff] [blame^] | 3804 | 2.37.1 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 3805 | |