blob: 8cab40c2006369f47715e322bfd012147070b37a [file] [log] [blame]
Patrick Williams92b42cb2022-09-03 06:53:57 -05001From c0b01dff84d74f1b5aaff0d9b594e0aaec16c744 Mon Sep 17 00:00:00 2001
Brad Bishopbec4ebc2022-08-03 09:55:16 -04002From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
3Date: Tue, 2 Nov 2021 16:44:39 +0000
Patrick Williams92b42cb2022-09-03 06:53:57 -05004Subject: [PATCH 10/24] arm_ffa: corstone1000: enable FF-A and MM support
Brad Bishopbec4ebc2022-08-03 09:55:16 -04005
6This commit allows corstone1000 platform to perform
7MM communication between u-boot and the secure world
8using FF-A transport.
9
10Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
11Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
12---
13 configs/corstone1000_defconfig | 1 +
14 include/configs/corstone1000.h | 15 +++++++++++++++
15 2 files changed, 16 insertions(+)
16
17diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
18index e573fe6fe6a2..b042d4e49419 100644
19--- a/configs/corstone1000_defconfig
20+++ b/configs/corstone1000_defconfig
21@@ -44,6 +44,7 @@ CONFIG_USB=y
22 CONFIG_DM_USB=y
23 CONFIG_USB_ISP1760=y
24 CONFIG_USB_STORAGE=y
25+CONFIG_ARM_FFA_TRANSPORT=y
26 CONFIG_EFI_MM_COMM_TEE=y
27 # CONFIG_OPTEE is not set
28 # CONFIG_GENERATE_SMBIOS_TABLE is not set
29diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
30index 8ba0effb0ab2..afc9ccfc192b 100644
31--- a/include/configs/corstone1000.h
32+++ b/include/configs/corstone1000.h
33@@ -14,6 +14,21 @@
34
35 #include <linux/sizes.h>
36
37+/* MM SP UUID binary data (little-endian format) */
38+#define MM_SP_UUID_DATA \
39+ 0xed, 0x32, 0xd5, 0x33, \
40+ 0x99, 0xe6, 0x42, 0x09, \
41+ 0x9c, 0xc0, 0x2d, 0x72, \
42+ 0xcd, 0xd9, 0x98, 0xa7
43+
44+#define FFA_SHARED_MM_BUFFER_SIZE SZ_4K /* 4 KB */
45+
46+/*
47+ * shared buffer physical address used for communication between
48+ * u-boot and the MM SP
49+ */
50+#define FFA_SHARED_MM_BUFFER_ADDR (0x023F8000)
51+
52 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
53 #define CONFIG_SKIP_LOWLEVEL_INIT
54
55--
Patrick Williams92b42cb2022-09-03 06:53:57 -0500562.37.1
Brad Bishopbec4ebc2022-08-03 09:55:16 -040057