Patrick Williams | 92b42cb | 2022-09-03 06:53:57 -0500 | [diff] [blame^] | 1 | Upstream-Status: Pending [Not submitted to upstream yet] |
| 2 | Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> |
| 3 | |
| 4 | From 22ba7c7789082dbc179921962cdcadece4499c89 Mon Sep 17 00:00:00 2001 |
| 5 | From: Vishnu Banavath <vishnu.banavath@arm.com> |
| 6 | Date: Thu, 30 Jun 2022 18:36:26 +0100 |
| 7 | Subject: [PATCH] plat-n1sdp: add N1SDP platform support |
| 8 | |
| 9 | These changes are to add N1SDP platform to optee-os |
| 10 | |
| 11 | Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> |
| 12 | |
| 13 | diff --git a/core/arch/arm/plat-n1sdp/conf.mk b/core/arch/arm/plat-n1sdp/conf.mk |
| 14 | new file mode 100644 |
| 15 | index 00000000..06b4975a |
| 16 | --- /dev/null |
| 17 | +++ b/core/arch/arm/plat-n1sdp/conf.mk |
| 18 | @@ -0,0 +1,41 @@ |
| 19 | +include core/arch/arm/cpu/cortex-armv8-0.mk |
| 20 | + |
| 21 | +CFG_DEBUG_INFO = y |
| 22 | +CFG_TEE_CORE_LOG_LEVEL = 4 |
| 23 | + |
| 24 | +# Workaround 808870: Unconditional VLDM instructions might cause an |
| 25 | +# alignment fault even though the address is aligned |
| 26 | +# Either hard float must be disabled for AArch32 or strict alignment checks |
| 27 | +# must be disabled |
| 28 | +ifeq ($(CFG_SCTLR_ALIGNMENT_CHECK),y) |
| 29 | +$(call force,CFG_TA_ARM32_NO_HARD_FLOAT_SUPPORT,y) |
| 30 | +else |
| 31 | +$(call force,CFG_SCTLR_ALIGNMENT_CHECK,n) |
| 32 | +endif |
| 33 | + |
| 34 | +CFG_ARM64_core ?= y |
| 35 | + |
| 36 | +CFG_ARM_GICV3 = y |
| 37 | + |
| 38 | +# ARM debugger needs this |
| 39 | +platform-cflags-debug-info = -gdwarf-4 |
| 40 | +platform-aflags-debug-info = -gdwarf-4 |
| 41 | + |
| 42 | +CFG_CORE_SEL1_SPMC = y |
| 43 | +CFG_WITH_ARM_TRUSTED_FW = y |
| 44 | + |
| 45 | +$(call force,CFG_GIC,y) |
| 46 | +$(call force,CFG_PL011,y) |
| 47 | +$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) |
| 48 | + |
| 49 | +CFG_CORE_HEAP_SIZE = 0x32000 # 200kb |
| 50 | + |
| 51 | +CFG_TEE_CORE_NB_CORE = 4 |
| 52 | +CFG_TZDRAM_START ?= 0x08000000 |
| 53 | +CFG_TZDRAM_SIZE ?= 0x02008000 |
| 54 | + |
| 55 | +CFG_SHMEM_START ?= 0x83000000 |
| 56 | +CFG_SHMEM_SIZE ?= 0x00210000 |
| 57 | +# DRAM1 is defined above 4G |
| 58 | +$(call force,CFG_CORE_LARGE_PHYS_ADDR,y) |
| 59 | +$(call force,CFG_CORE_ARM64_PA_BITS,36) |
| 60 | diff --git a/core/arch/arm/plat-n1sdp/main.c b/core/arch/arm/plat-n1sdp/main.c |
| 61 | new file mode 100644 |
| 62 | index 00000000..cfb7f19b |
| 63 | --- /dev/null |
| 64 | +++ b/core/arch/arm/plat-n1sdp/main.c |
| 65 | @@ -0,0 +1,63 @@ |
| 66 | +// SPDX-License-Identifier: BSD-2-Clause |
| 67 | +/* |
| 68 | + * Copyright (c) 2022, Arm Limited. |
| 69 | + */ |
| 70 | + |
| 71 | +#include <arm.h> |
| 72 | +#include <console.h> |
| 73 | +#include <drivers/gic.h> |
| 74 | +#include <drivers/pl011.h> |
| 75 | +#include <drivers/tpm2_mmio.h> |
| 76 | +#include <drivers/tpm2_ptp_fifo.h> |
| 77 | +#include <drivers/tzc400.h> |
| 78 | +#include <initcall.h> |
| 79 | +#include <keep.h> |
| 80 | +#include <kernel/boot.h> |
| 81 | +#include <kernel/interrupt.h> |
| 82 | +#include <kernel/misc.h> |
| 83 | +#include <kernel/notif.h> |
| 84 | +#include <kernel/panic.h> |
| 85 | +#include <kernel/spinlock.h> |
| 86 | +#include <kernel/tee_time.h> |
| 87 | +#include <mm/core_memprot.h> |
| 88 | +#include <mm/core_mmu.h> |
| 89 | +#include <platform_config.h> |
| 90 | +#include <sm/psci.h> |
| 91 | +#include <stdint.h> |
| 92 | +#include <string.h> |
| 93 | +#include <trace.h> |
| 94 | + |
| 95 | +static struct gic_data gic_data __nex_bss; |
| 96 | +static struct pl011_data console_data __nex_bss; |
| 97 | + |
| 98 | +register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); |
| 99 | + |
| 100 | +register_ddr(DRAM0_BASE, DRAM0_SIZE); |
| 101 | + |
| 102 | +register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); |
| 103 | +register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); |
| 104 | +register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GIC_DIST_REG_SIZE); |
| 105 | + |
| 106 | +void main_init_gic(void) |
| 107 | +{ |
| 108 | + gic_init_base_addr(&gic_data, GICC_BASE, |
| 109 | + GICD_BASE); |
| 110 | + itr_init(&gic_data.chip); |
| 111 | +} |
| 112 | + |
| 113 | +void main_secondary_init_gic(void) |
| 114 | +{ |
| 115 | + gic_cpu_init(&gic_data); |
| 116 | +} |
| 117 | + |
| 118 | +void itr_core_handler(void) |
| 119 | +{ |
| 120 | + gic_it_handle(&gic_data); |
| 121 | +} |
| 122 | + |
| 123 | +void console_init(void) |
| 124 | +{ |
| 125 | + pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, |
| 126 | + CONSOLE_BAUDRATE); |
| 127 | + register_serial_console(&console_data.chip); |
| 128 | +} |
| 129 | diff --git a/core/arch/arm/plat-n1sdp/n1sdp_core_pos.S b/core/arch/arm/plat-n1sdp/n1sdp_core_pos.S |
| 130 | new file mode 100644 |
| 131 | index 00000000..439d4e67 |
| 132 | --- /dev/null |
| 133 | +++ b/core/arch/arm/plat-n1sdp/n1sdp_core_pos.S |
| 134 | @@ -0,0 +1,32 @@ |
| 135 | +/* SPDX-License-Identifier: BSD-2-Clause */ |
| 136 | +/* |
| 137 | + * Copyright (c) 2022, Arm Limited |
| 138 | + */ |
| 139 | + |
| 140 | +#include <asm.S> |
| 141 | +#include <arm.h> |
| 142 | +#include "platform_config.h" |
| 143 | + |
| 144 | +FUNC get_core_pos_mpidr , : |
| 145 | + mov x4, x0 |
| 146 | + |
| 147 | + /* |
| 148 | + * The MT bit in MPIDR is always set for n1sdp and the |
| 149 | + * affinity level 0 corresponds to thread affinity level. |
| 150 | + */ |
| 151 | + |
| 152 | + /* Extract individual affinity fields from MPIDR */ |
| 153 | + ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS |
| 154 | + ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS |
| 155 | + ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS |
| 156 | + ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS |
| 157 | + |
| 158 | + /* Compute linear position */ |
| 159 | + mov x4, #N1SDP_MAX_CLUSTERS_PER_CHIP |
| 160 | + madd x2, x3, x4, x2 |
| 161 | + mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER |
| 162 | + madd x1, x2, x4, x1 |
| 163 | + mov x4, #N1SDP_MAX_PE_PER_CPU |
| 164 | + madd x0, x1, x4, x0 |
| 165 | + ret |
| 166 | +END_FUNC get_core_pos_mpidr |
| 167 | diff --git a/core/arch/arm/plat-n1sdp/platform_config.h b/core/arch/arm/plat-n1sdp/platform_config.h |
| 168 | new file mode 100644 |
| 169 | index 00000000..81b99409 |
| 170 | --- /dev/null |
| 171 | +++ b/core/arch/arm/plat-n1sdp/platform_config.h |
| 172 | @@ -0,0 +1,49 @@ |
| 173 | +/* SPDX-License-Identifier: BSD-2-Clause */ |
| 174 | +/* |
| 175 | + * Copyright (c) 2022, Arm Limited |
| 176 | + */ |
| 177 | + |
| 178 | +#ifndef PLATFORM_CONFIG_H |
| 179 | +#define PLATFORM_CONFIG_H |
| 180 | + |
| 181 | +#include <mm/generic_ram_layout.h> |
| 182 | +#include <stdint.h> |
| 183 | + |
| 184 | +/* Make stacks aligned to data cache line length */ |
| 185 | +#define STACK_ALIGNMENT 64 |
| 186 | + |
| 187 | + /* N1SDP topology related constants */ |
| 188 | +#define N1SDP_MAX_CPUS_PER_CLUSTER U(2) |
| 189 | +#define PLAT_ARM_CLUSTER_COUNT U(2) |
| 190 | +#define PLAT_N1SDP_CHIP_COUNT U(2) |
| 191 | +#define N1SDP_MAX_CLUSTERS_PER_CHIP U(2) |
| 192 | +#define N1SDP_MAX_PE_PER_CPU U(1) |
| 193 | + |
| 194 | +#define PLATFORM_CORE_COUNT (PLAT_N1SDP_CHIP_COUNT * \ |
| 195 | + PLAT_ARM_CLUSTER_COUNT * \ |
| 196 | + N1SDP_MAX_CPUS_PER_CLUSTER * \ |
| 197 | + N1SDP_MAX_PE_PER_CPU) |
| 198 | + |
| 199 | +#define GIC_BASE 0x2c010000 |
| 200 | + |
| 201 | +#define UART1_BASE 0x1C0A0000 |
| 202 | +#define UART1_CLK_IN_HZ 24000000 /*24MHz*/ |
| 203 | + |
| 204 | +#define CONSOLE_UART_BASE UART1_BASE |
| 205 | +#define CONSOLE_UART_CLK_IN_HZ UART1_CLK_IN_HZ |
| 206 | + |
| 207 | +#define DRAM0_BASE 0x80000000 |
| 208 | +#define DRAM0_SIZE 0x80000000 |
| 209 | + |
| 210 | +#define GICD_BASE 0x30000000 |
| 211 | +#define GICC_BASE 0x2C000000 |
| 212 | +#define GICR_BASE 0x300C0000 |
| 213 | + |
| 214 | +#ifndef UART_BAUDRATE |
| 215 | +#define UART_BAUDRATE 115200 |
| 216 | +#endif |
| 217 | +#ifndef CONSOLE_BAUDRATE |
| 218 | +#define CONSOLE_BAUDRATE UART_BAUDRATE |
| 219 | +#endif |
| 220 | + |
| 221 | +#endif /*PLATFORM_CONFIG_H*/ |
| 222 | diff --git a/core/arch/arm/plat-n1sdp/sub.mk b/core/arch/arm/plat-n1sdp/sub.mk |
| 223 | new file mode 100644 |
| 224 | index 00000000..a0b49da1 |
| 225 | --- /dev/null |
| 226 | +++ b/core/arch/arm/plat-n1sdp/sub.mk |
| 227 | @@ -0,0 +1,3 @@ |
| 228 | +global-incdirs-y += . |
| 229 | +srcs-y += main.c |
| 230 | +srcs-y += n1sdp_core_pos.S |
| 231 | -- |
| 232 | 2.17.1 |
| 233 | |