| Patrick Williams | 92b42cb | 2022-09-03 06:53:57 -0500 | [diff] [blame^] | 1 | Upstream-Status: Pending [Not submitted to upstream yet] |
| 2 | Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> |
| 3 | |
| 4 | From 0c3ce4c09cd7d2ff4cd2e62acab899dd88dc9514 Mon Sep 17 00:00:00 2001 |
| 5 | From: Vishnu Banavath <vishnu.banavath@arm.com> |
| 6 | Date: Wed, 20 Jul 2022 16:45:59 +0100 |
| 7 | Subject: [PATCH] HACK: disable instruction cache and data cache. |
| 8 | |
| 9 | For some reason, n1sdp fails to boot with instruction cache and |
| 10 | data cache enabled. This is a temporary change to disable I cache |
| 11 | and D cache until a proper fix is found. |
| 12 | |
| 13 | Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> |
| 14 | |
| 15 | %% original patch: 0003-HACK-disable-instruction-cache-and-data-cache.patch |
| 16 | |
| 17 | diff --git a/core/arch/arm/kernel/entry_a64.S b/core/arch/arm/kernel/entry_a64.S |
| 18 | index 875b6e69..594d6928 100644 |
| 19 | --- a/core/arch/arm/kernel/entry_a64.S |
| 20 | +++ b/core/arch/arm/kernel/entry_a64.S |
| 21 | @@ -52,7 +52,7 @@ |
| 22 | |
| 23 | .macro set_sctlr_el1 |
| 24 | mrs x0, sctlr_el1 |
| 25 | - orr x0, x0, #SCTLR_I |
| 26 | + bic x0, x0, #SCTLR_I |
| 27 | orr x0, x0, #SCTLR_SA |
| 28 | orr x0, x0, #SCTLR_SPAN |
| 29 | #if defined(CFG_CORE_RWDATA_NOEXEC) |
| 30 | @@ -490,11 +490,11 @@ LOCAL_FUNC enable_mmu , : , .identity_map |
| 31 | isb |
| 32 | |
| 33 | /* Enable I and D cache */ |
| 34 | - mrs x1, sctlr_el1 |
| 35 | + /* mrs x1, sctlr_el1 |
| 36 | orr x1, x1, #SCTLR_I |
| 37 | orr x1, x1, #SCTLR_C |
| 38 | msr sctlr_el1, x1 |
| 39 | - isb |
| 40 | + isb */ |
| 41 | |
| 42 | /* Adjust stack pointers and return address */ |
| 43 | msr spsel, #1 |
| 44 | -- |
| 45 | 2.17.1 |
| 46 | |