Andrew Geissler | 9347dd4 | 2023-03-03 12:38:41 -0600 | [diff] [blame^] | 1 | From bff110a95a5e4c9db2d61e629b4aa4b84530201e Mon Sep 17 00:00:00 2001 |
Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 2 | From: Jaxson Han <jaxson.han@arm.com> |
| 3 | Date: Tue, 25 May 2021 07:25:00 +0100 |
| 4 | Subject: [PATCH] gic-v3: Prepare for gicv3 with EL2 |
| 5 | |
| 6 | This is a preparation for allowing boot-wrapper configuring the gicv3 |
| 7 | with EL2. |
| 8 | |
| 9 | When confiuring with EL2, since there is no ICC_CTLR_EL2, the |
| 10 | ICC_CTLR_EL3 cannot be replaced with ICC_CTLR_EL2 simply. |
| 11 | See [https://developer.arm.com/documentation/ihi0069/latest/]. |
| 12 | |
| 13 | As the caller, gic_secure_init expects the ICC_CTLR to be written, |
| 14 | we change the function into gic_init_icc_ctlr(). In the GIC spec, |
| 15 | the r/w bits in this register ([6:0]) either affect EL3 IRQ routing |
| 16 | (not applicable since no EL3), non-secure IRQ handling (not applicable |
| 17 | since only secure state in Armv8-R aarch64), or are aliased to |
| 18 | ICC_CTLR_EL1 bits. |
| 19 | So, based on this, the new gic_init_icc_ctlr() would be: |
| 20 | When currentEL is EL3, init ICC_CTLR_EL3 as before. |
| 21 | When currentEL is not EL3, init ICC_CTLR_EL1 with ICC_CTLR_EL1_RESET. |
| 22 | |
| 23 | Upstream-Status: Pending |
| 24 | Signed-off-by: Jaxson Han <jaxson.han@arm.com> |
| 25 | Reviewed-by: Andre Przywara <andre.przywara@arm.com> |
| 26 | --- |
| 27 | arch/aarch32/include/asm/gic-v3.h | 7 +++++++ |
| 28 | arch/aarch64/include/asm/gic-v3.h | 23 ++++++++++++++++++++--- |
| 29 | common/gic-v3.c | 2 +- |
| 30 | 3 files changed, 28 insertions(+), 4 deletions(-) |
| 31 | |
| 32 | diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h |
| 33 | index 65f38de..11e7bc7 100644 |
| 34 | --- a/arch/aarch32/include/asm/gic-v3.h |
| 35 | +++ b/arch/aarch32/include/asm/gic-v3.h |
| 36 | @@ -9,6 +9,8 @@ |
| 37 | #ifndef __ASM_AARCH32_GICV3_H |
| 38 | #define __ASM_AARCH32_GICV3_H |
| 39 | |
| 40 | +#define ICC_CTLR_RESET (0UL) |
| 41 | + |
| 42 | static inline void gic_write_icc_sre(uint32_t val) |
| 43 | { |
| 44 | asm volatile ("mcr p15, 6, %0, c12, c12, 5" : : "r" (val)); |
| 45 | @@ -19,4 +21,9 @@ static inline void gic_write_icc_ctlr(uint32_t val) |
| 46 | asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val)); |
| 47 | } |
| 48 | |
| 49 | +static inline void gic_init_icc_ctlr() |
| 50 | +{ |
| 51 | + gic_write_icc_ctlr(ICC_CTLR_RESET); |
| 52 | +} |
| 53 | + |
| 54 | #endif |
| 55 | diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h |
| 56 | index 5b32380..090ab0b 100644 |
| 57 | --- a/arch/aarch64/include/asm/gic-v3.h |
| 58 | +++ b/arch/aarch64/include/asm/gic-v3.h |
| 59 | @@ -15,14 +15,31 @@ |
| 60 | #define ICC_CTLR_EL3 "S3_6_C12_C12_4" |
| 61 | #define ICC_PMR_EL1 "S3_0_C4_C6_0" |
| 62 | |
| 63 | +#define ICC_CTLR_EL3_RESET (0UL) |
| 64 | +#define ICC_CTLR_EL1_RESET (0UL) |
| 65 | + |
| 66 | +static inline uint32_t current_el(void) |
| 67 | +{ |
| 68 | + uint32_t val; |
| 69 | + |
| 70 | + asm volatile ("mrs %0, CurrentEL" : "=r" (val)); |
| 71 | + return val; |
| 72 | +} |
| 73 | + |
| 74 | static inline void gic_write_icc_sre(uint32_t val) |
| 75 | { |
| 76 | - asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val)); |
| 77 | + if (current_el() == CURRENTEL_EL3) |
| 78 | + asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val)); |
| 79 | + else |
| 80 | + asm volatile ("msr " ICC_SRE_EL2 ", %0" : : "r" (val)); |
| 81 | } |
| 82 | |
| 83 | -static inline void gic_write_icc_ctlr(uint32_t val) |
| 84 | +static inline void gic_init_icc_ctlr() |
| 85 | { |
| 86 | - asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val)); |
| 87 | + if (current_el() == CURRENTEL_EL3) |
| 88 | + asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (ICC_CTLR_EL3_RESET)); |
| 89 | + else |
| 90 | + asm volatile ("msr " ICC_CTLR_EL1 ", %0" : : "r" (ICC_CTLR_EL1_RESET)); |
| 91 | } |
| 92 | |
| 93 | #endif |
| 94 | diff --git a/common/gic-v3.c b/common/gic-v3.c |
| 95 | index 6207007..a0fe564 100644 |
| 96 | --- a/common/gic-v3.c |
| 97 | +++ b/common/gic-v3.c |
| 98 | @@ -117,6 +117,6 @@ void gic_secure_init(void) |
| 99 | gic_write_icc_sre(ICC_SRE_Enable | ICC_SRE_DIB | ICC_SRE_DFB | ICC_SRE_SRE); |
| 100 | isb(); |
| 101 | |
| 102 | - gic_write_icc_ctlr(0); |
| 103 | + gic_init_icc_ctlr(); |
| 104 | isb(); |
| 105 | } |