blob: c0d1fcbbb831c7da8f48de6d876ae3581f323f6e [file] [log] [blame]
Andrew Geissler9347dd42023-03-03 12:38:41 -06001From 7c5e40d9f8699a55ac2187c035429c643e6d0ef0 Mon Sep 17 00:00:00 2001
Brad Bishopbec4ebc2022-08-03 09:55:16 -04002From: Jaxson Han <jaxson.han@arm.com>
3Date: Tue, 2 Nov 2021 15:10:28 +0800
4Subject: [PATCH] lds: Rearrange and mark the sections
5
6To make it possible for the next stage to protect sections with MPU,
7boot-wrapper needs to provide the text and data section information.
8By rearranging the .data .rodata and .vector sections, all sections
9can be split into 2 big sections:
10 - RO and Executable
11 - RW and Non-Executable
12Add firmware_data to mark the boundry, thus:
13firmware_start to firmware_data - 1 indicates RO and Executable section,
14firmware_data to firmware_end - 1 indicates RW and Non-Executable
15section.
16
17Also, the firmware_data and firmware_end should align with 64 bytes,
18since Armv8R AArch64 MPU requires it.
19
20Issue-ID: SCM-3816
21Upstream-Status: Inappropriate [other]
22 Implementation pending further discussion
23Signed-off-by: Jaxson Han <jaxson.han@arm.com>
24Change-Id: I55342aa7492f2c7b5c16ab9a6472c8cb45cff8fd
25---
26 model.lds.S | 7 ++++++-
27 1 file changed, 6 insertions(+), 1 deletion(-)
28
29diff --git a/model.lds.S b/model.lds.S
30index ab98ddf..85451f9 100644
31--- a/model.lds.S
32+++ b/model.lds.S
33@@ -63,12 +63,16 @@ SECTIONS
34 }
35 #endif
36
37+#define FIRMWARE_ALIGN . = ALIGN(1 << 6)
38 .boot PHYS_OFFSET: {
39 PROVIDE(firmware_start = .);
40 *(.init)
41 *(.text*)
42- *(.data* .rodata* .bss* COMMON)
43 *(.vectors)
44+ *(.rodata*)
45+ FIRMWARE_ALIGN;
46+ PROVIDE(firmware_data = .);
47+ *(.data* .bss* COMMON)
48 *(.stack)
49 PROVIDE(etext = .);
50 }
51@@ -77,6 +81,7 @@ SECTIONS
52 mbox = .;
53 QUAD(0x0)
54 }
55+ FIRMWARE_ALIGN;
56 PROVIDE(firmware_end = .);
57
58 ASSERT(etext <= (PHYS_OFFSET + TEXT_LIMIT), ".text overflow!")