blob: 2d0311a5f893667efdf76cf3834e72a52545931a [file] [log] [blame]
Brad Bishopbec4ebc2022-08-03 09:55:16 -04001/*
2 * Copyright (c) 2015-2016 ARM Limited
3 * All rights reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Andreas Sandberg
29 */
30
31/dts-v1/;
32
33/memreserve/ 0x80000000 0x00010000;
34
35/include/ "vexpress_gem5_v2.dtsi"
36
37/ {
38 model = "V2P-AARCH64";
39 compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress";
40
41 memory@80000000 {
42 device_type = "memory";
43 reg = <0 0x80000000 0x4 0x00000000>;
44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 cpu@0 {
51 device_type = "cpu";
52 compatible = "gem5,armv8", "arm,armv8";
53 reg = < 0 >;
54 enable-method = "spin-table";
55 cpu-release-addr = <0 0x8000fff8>;
56 };
57
58 cpu@1 {
59 device_type = "cpu";
60 compatible = "gem5,armv8", "arm,armv8";
61 reg = < 1 >;
62 enable-method = "spin-table";
63 cpu-release-addr = <0 0x8000fff8>;
64 };
65
66 cpu@2 {
67 device_type = "cpu";
68 compatible = "gem5,armv8", "arm,armv8";
69 reg = < 2 >;
70 enable-method = "spin-table";
71 cpu-release-addr = <0 0x8000fff8>;
72 };
73
74 cpu@3 {
75 device_type = "cpu";
76 compatible = "gem5,armv8", "arm,armv8";
77 reg = < 3 >;
78 enable-method = "spin-table";
79 cpu-release-addr = <0 0x8000fff8>;
80 };
81
82 };
83
84 virt-encoder {
85 compatible = "drm,virtual-encoder";
86 port {
87 dp0_virt_input: endpoint@0 {
88 remote-endpoint = <&dp0_output>;
89 };
90 };
91
92 display-timings {
93 native-mode = <&timing0>;
94
95 timing0: timing_1080p60 {
96 /* 1920x1080-60 */
97 clock-frequency = <148500000>;
98 hactive = <1920>;
99 vactive = <1080>;
100 hfront-porch = <148>;
101 hback-porch = <88>;
102 hsync-len = <44>;
103 vfront-porch = <36>;
104 vback-porch = <4>;
105 vsync-len = <5>;
106 };
107 };
108 };
109};
110
111&dp0 {
112 status = "ok";
113
114 port {
115 dp0_output: endpoint@0 {
116 remote-endpoint = <&dp0_virt_input>;
117 };
118 };
119};