Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2017, 2019 ARM Limited |
| 3 | * All rights reserved |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions are |
| 7 | * met: redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer; |
| 9 | * redistributions in binary form must reproduce the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer in the |
| 11 | * documentation and/or other materials provided with the distribution; |
| 12 | * neither the name of the copyright holders nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived from |
| 14 | * this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | * Authors: Andreas Sandberg |
| 29 | */ |
| 30 | |
| 31 | / { |
| 32 | arm,hbi = <0x0>; |
| 33 | arm,vexpress,site = <0xf>; |
| 34 | interrupt-parent = <&gic>; |
| 35 | #address-cells = <2>; |
| 36 | #size-cells = <2>; |
| 37 | |
| 38 | gic: interrupt-controller@2c000000 { |
| 39 | compatible = "arm,gic-v3"; |
| 40 | #interrupt-cells = <0x3>; |
| 41 | #address-cells = <0x2>; |
| 42 | ranges; |
| 43 | interrupt-controller; |
| 44 | redistributor-stride = <0x0 0x40000>; // 256kB stride |
| 45 | reg = <0x0 0x2c000000 0x0 0x10000 |
| 46 | 0x0 0x2c010000 0x0 0x2000000 // room for 128 redistributors using 128K each (256K strided...) |
| 47 | 0x0 0x0 0x0 0x0>; |
| 48 | interrupts = <1 9 0xf04>; |
| 49 | #size-cells = <0x2>; |
| 50 | linux,phandle = <0x1>; |
| 51 | phandle = <0x1>; |
| 52 | |
| 53 | gic-its@2e010000 { |
| 54 | compatible = "arm,gic-v3-its"; |
| 55 | msi-controller; |
| 56 | #msi-cells = <1>; |
| 57 | reg = <0x0 0x2e010000 0 0x20000>; |
| 58 | }; |
| 59 | }; |
| 60 | |
| 61 | timer { |
| 62 | compatible = "arm,cortex-a15-timer", |
| 63 | "arm,armv7-timer"; |
| 64 | interrupts = <1 13 0xf08>, |
| 65 | <1 14 0xf08>, |
| 66 | <1 11 0xf08>, |
| 67 | <1 10 0xf08>; |
| 68 | clocks = <&osc_sys>; |
| 69 | clock-names="apb_pclk"; |
| 70 | }; |
| 71 | |
| 72 | pci { |
| 73 | compatible = "pci-host-ecam-generic"; |
| 74 | device_type = "pci"; |
| 75 | #address-cells = <0x3>; |
| 76 | #size-cells = <0x2>; |
| 77 | #interrupt-cells = <0x1>; |
| 78 | |
| 79 | reg = <0x0 0x30000000 0x0 0x10000000>; |
| 80 | |
| 81 | ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>, |
| 82 | <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; |
| 83 | |
| 84 | /* |
| 85 | child unit address, #cells = #address-cells |
| 86 | child interrupt specifier, #cells = #interrupt-cells (INTA = 1, INTB = 2, INTC = 3 and INTD = 4) |
| 87 | interrupt-parent, phandle |
| 88 | parent unit address, #cells = #address-cells@gic |
| 89 | parent interrupt specifier, #cells = #interrupt-cells@gic |
| 90 | */ |
| 91 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x44 0x1 |
| 92 | 0x800 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x45 0x1 |
| 93 | 0x1000 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x46 0x1 |
| 94 | 0x1800 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x47 0x1>; |
| 95 | |
| 96 | interrupt-map-mask = <0x001800 0x0 0x0 0x0>; |
| 97 | dma-coherent; |
| 98 | }; |
| 99 | |
| 100 | kmi@1c060000 { |
| 101 | compatible = "arm,pl050", "arm,primecell"; |
| 102 | reg = <0x0 0x1c060000 0x0 0x1000>; |
| 103 | interrupts = <0 12 4>; |
| 104 | clocks = <&v2m_clk24mhz>, <&osc_smb>; |
| 105 | clock-names = "KMIREFCLK", "apb_pclk"; |
| 106 | }; |
| 107 | |
| 108 | kmi@1c070000 { |
| 109 | compatible = "arm,pl050", "arm,primecell"; |
| 110 | reg = <0x0 0x1c070000 0x0 0x1000>; |
| 111 | interrupts = <0 13 4>; |
| 112 | clocks = <&v2m_clk24mhz>, <&osc_smb>; |
| 113 | clock-names = "KMIREFCLK", "apb_pclk"; |
| 114 | }; |
| 115 | |
| 116 | uart0: uart@1c090000 { |
| 117 | compatible = "arm,pl011", "arm,primecell"; |
| 118 | reg = <0x0 0x1c090000 0x0 0x1000>; |
| 119 | interrupts = <0 5 4>; |
| 120 | clocks = <&osc_peripheral>, <&osc_smb>; |
| 121 | clock-names = "uartclk", "apb_pclk"; |
| 122 | }; |
| 123 | |
| 124 | rtc@1c170000 { |
| 125 | compatible = "arm,pl031", "arm,primecell"; |
| 126 | reg = <0x0 0x1c170000 0x0 0x1000>; |
| 127 | interrupts = <0 4 4>; |
| 128 | clocks = <&osc_smb>; |
| 129 | clock-names = "apb_pclk"; |
| 130 | }; |
| 131 | |
| 132 | v2m_clk24mhz: clk24mhz { |
| 133 | compatible = "fixed-clock"; |
| 134 | #clock-cells = <0>; |
| 135 | clock-frequency = <24000000>; |
| 136 | clock-output-names = "v2m:clk24mhz"; |
| 137 | }; |
| 138 | |
| 139 | |
| 140 | v2m_sysreg: sysreg@1c010000 { |
| 141 | compatible = "arm,vexpress-sysreg"; |
| 142 | reg = <0 0x1c010000 0x0 0x1000>; |
| 143 | gpio-controller; |
| 144 | #gpio-cells = <2>; |
| 145 | }; |
| 146 | |
| 147 | vio@1c130000 { |
| 148 | compatible = "virtio,mmio"; |
| 149 | reg = <0 0x1c130000 0x0 0x1000>; |
| 150 | interrupts = <0 42 4>; |
| 151 | }; |
| 152 | |
| 153 | vio@1c140000 { |
| 154 | compatible = "virtio,mmio"; |
| 155 | reg = <0 0x1c140000 0x0 0x1000>; |
| 156 | interrupts = <0 43 4>; |
| 157 | }; |
| 158 | |
| 159 | dcc { |
| 160 | compatible = "arm,vexpress,config-bus"; |
| 161 | arm,vexpress,config-bridge = <&v2m_sysreg>; |
| 162 | |
| 163 | osc_pxl: osc@5 { |
| 164 | compatible = "arm,vexpress-osc"; |
| 165 | arm,vexpress-sysreg,func = <1 5>; |
| 166 | freq-range = <23750000 1000000000>; |
| 167 | #clock-cells = <0>; |
| 168 | clock-output-names = "oscclk5"; |
| 169 | }; |
| 170 | |
| 171 | osc_smb: osc@6 { |
| 172 | compatible = "arm,vexpress-osc"; |
| 173 | arm,vexpress-sysreg,func = <1 6>; |
| 174 | freq-range = <20000000 50000000>; |
| 175 | #clock-cells = <0>; |
| 176 | clock-output-names = "oscclk6"; |
| 177 | }; |
| 178 | |
| 179 | osc_sys: osc@7 { |
| 180 | compatible = "arm,vexpress-osc"; |
| 181 | arm,vexpress-sysreg,func = <1 7>; |
| 182 | freq-range = <20000000 60000000>; |
| 183 | #clock-cells = <0>; |
| 184 | clock-output-names = "oscclk7"; |
| 185 | }; |
| 186 | }; |
| 187 | |
| 188 | |
| 189 | mcc { |
| 190 | compatible = "arm,vexpress,config-bus"; |
| 191 | arm,vexpress,config-bridge = <&v2m_sysreg>; |
| 192 | arm,vexpress,site = <0>; |
| 193 | |
| 194 | osc_peripheral: osc@2 { |
| 195 | compatible = "arm,vexpress-osc"; |
| 196 | arm,vexpress-sysreg,func = <1 2>; |
| 197 | freq-range = <24000000 24000000>; |
| 198 | #clock-cells = <0>; |
| 199 | clock-output-names = "v2m:oscclk2"; |
| 200 | }; |
| 201 | }; |
| 202 | }; |