Chanh Nguyen | 1019776 | 2021-03-18 00:06:08 +0700 | [diff] [blame] | 1 | From 2c9ab641f2a7ea146a468ec4301c416010badff7 Mon Sep 17 00:00:00 2001 |
| 2 | From: Chanh Nguyen <chanh@os.amperecomputing.com> |
| 3 | Date: Wed, 17 Mar 2021 14:11:18 +0700 |
| 4 | Subject: [PATCH] aspeed: support Mt.Jade platform init |
| 5 | |
| 6 | This commit adds platform init for Mt.Jade platform. |
| 7 | |
| 8 | Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com> |
| 9 | Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com> |
| 10 | --- |
| 11 | arch/arm/include/asm/arch-aspeed/ast_scu.h | 1 + |
| 12 | arch/arm/include/asm/arch-aspeed/regs-scu.h | 4 ++ |
| 13 | arch/arm/mach-aspeed/ast-scu.c | 18 +++++ |
| 14 | board/aspeed/ast-g5/ast-g5.c | 76 +++++++++++++++++++++ |
| 15 | include/configs/ast-g5-phy.h | 3 + |
| 16 | 5 files changed, 102 insertions(+) |
| 17 | |
| 18 | diff --git a/arch/arm/include/asm/arch-aspeed/ast_scu.h b/arch/arm/include/asm/arch-aspeed/ast_scu.h |
| 19 | index f5c9126ec0..e2d06ccc1f 100644 |
| 20 | --- a/arch/arm/include/asm/arch-aspeed/ast_scu.h |
| 21 | +++ b/arch/arm/include/asm/arch-aspeed/ast_scu.h |
| 22 | @@ -46,5 +46,6 @@ extern void ast_scu_init_eth(u8 num); |
| 23 | extern void ast_scu_multi_func_eth(u8 num); |
| 24 | extern void ast_scu_multi_func_romcs(u8 num); |
| 25 | extern void ast_scu_switch_pwm_to_gpio_mode(void); |
| 26 | +extern void ast_scu_switch_espi_to_gpio_mode(void); |
| 27 | |
| 28 | #endif |
| 29 | diff --git a/arch/arm/include/asm/arch-aspeed/regs-scu.h b/arch/arm/include/asm/arch-aspeed/regs-scu.h |
| 30 | index b714fa9234..704ad75b4e 100644 |
| 31 | --- a/arch/arm/include/asm/arch-aspeed/regs-scu.h |
| 32 | +++ b/arch/arm/include/asm/arch-aspeed/regs-scu.h |
| 33 | @@ -76,6 +76,7 @@ |
| 34 | #define AST_SCU_FUN_PIN_CTRL7 0xA0 /* Multi-function Pin Control#7*/ |
| 35 | #define AST_SCU_FUN_PIN_CTRL8 0xA4 /* Multi-function Pin Control#8*/ |
| 36 | #define AST_SCU_FUN_PIN_CTRL9 0xA8 /* Multi-function Pin Control#9*/ |
| 37 | +#define AST_SCU_FUN_PIN_CTRL10 0xAC /* Multi-function Pin Control#10*/ |
| 38 | #define AST_SCU_MAC_CLK_DELAY_100M 0xB8 /* MAC interface clock delay 100M setting*/ |
| 39 | #define AST_SCU_MAC_CLK_DELAY_10M 0xBC /* MAC interface clock delay 10M setting*/ |
| 40 | #define AST_SCU_PWR_SAVING_EN 0xC0 /* Power Saving Wakeup Enable*/ |
| 41 | @@ -921,6 +922,9 @@ |
| 42 | #define SCU_FUN_PIN_ROMA19 (0x1 << 1) |
| 43 | #define SCU_FUN_PIN_ROMA18 (0x1) |
| 44 | |
| 45 | +/* AST_SCU_FUN_PIN_CTRL10 0xAC - Multi-function Pin Control#10 */ |
| 46 | +#define SCU_FUN_PIN_ESPI(x) (0x1 << (x)) |
| 47 | + |
| 48 | /* AST_SCU_PWR_SAVING_EN 0xC0 - Power Saving Wakeup Enable */ |
| 49 | /* AST_SCU_PWR_SAVING_CTRL 0xC4 - Power Saving Wakeup Control */ |
| 50 | /* AST_SCU_HW_STRAP2 0xD0 - Haardware strapping register set 2 */ |
| 51 | diff --git a/arch/arm/mach-aspeed/ast-scu.c b/arch/arm/mach-aspeed/ast-scu.c |
| 52 | index c7ab66415f..71c043d3e8 100644 |
| 53 | --- a/arch/arm/mach-aspeed/ast-scu.c |
| 54 | +++ b/arch/arm/mach-aspeed/ast-scu.c |
| 55 | @@ -554,3 +554,21 @@ void ast_scu_get_who_init_dram(void) |
| 56 | break; |
| 57 | } |
| 58 | } |
| 59 | + |
| 60 | +void ast_scu_switch_espi_to_gpio_mode(void) |
| 61 | +{ |
| 62 | + /* |
| 63 | + * This Function to set the ESPI pin to GPIO mode |
| 64 | + * This allow to setting AC5_READY |
| 65 | + */ |
| 66 | + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL10) & |
| 67 | + ~SCU_FUN_PIN_ESPI(0) & |
| 68 | + ~SCU_FUN_PIN_ESPI(1) & |
| 69 | + ~SCU_FUN_PIN_ESPI(2) & |
| 70 | + ~SCU_FUN_PIN_ESPI(3) & |
| 71 | + ~SCU_FUN_PIN_ESPI(4) & |
| 72 | + ~SCU_FUN_PIN_ESPI(5) & |
| 73 | + ~SCU_FUN_PIN_ESPI(6) & |
| 74 | + ~SCU_FUN_PIN_ESPI(7), |
| 75 | + AST_SCU_FUN_PIN_CTRL10); |
| 76 | +} |
| 77 | diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c |
| 78 | index ed83d65136..edf7f050a8 100644 |
| 79 | --- a/board/aspeed/ast-g5/ast-g5.c |
| 80 | +++ b/board/aspeed/ast-g5/ast-g5.c |
| 81 | @@ -163,3 +163,79 @@ void hw_watchdog_reset(void) |
| 82 | writel(0x4755, AST_WDT2_BASE + 0x08); |
| 83 | } |
| 84 | #endif /* CONFIG_WATCHDOG */ |
| 85 | + |
| 86 | +#ifdef CONFIG_BOARD_EARLY_INIT_F |
| 87 | +int board_gpio_init(void) |
| 88 | +{ |
| 89 | + int pgood = 0; |
| 90 | + |
| 91 | + /* GPIO_BMC_PSU_PG */ |
| 92 | + pgood = gpio_get_value(44); |
| 93 | + /* GPIO_BMC_OCP_AUX_PWREN */ |
| 94 | + gpio_direction_output(139, 1); |
| 95 | + |
| 96 | + if (pgood) |
| 97 | + { |
| 98 | + /* GPIO_BMC_SYS_ATX_PSON_L */ |
| 99 | + gpio_direction_output(42, 0); |
| 100 | + /* GPIO_BMC_OCP_MAIN_PWREN */ |
| 101 | + gpio_direction_output(140, 1); |
| 102 | + } |
| 103 | + else |
| 104 | + { |
| 105 | + /* GPIO_BMC_SYS_ATX_PSON_L */ |
| 106 | + gpio_direction_output(42, 1); |
| 107 | + /* GPIO_BMC_OCP_MAIN_PWREN */ |
| 108 | + gpio_direction_output(140, 0); |
| 109 | + } |
| 110 | + |
| 111 | + /* GPIOH7 GPIO_BMC_I2C6_RESET_L */ |
| 112 | + gpio_direction_output(63, 1); |
| 113 | + |
| 114 | + /* GPIOM4 S0_I2C9_ALERT_L */ |
| 115 | + gpio_direction_input(100); |
| 116 | + |
| 117 | + /* GPIOM5 S1_I2C9_ALERT_L */ |
| 118 | + gpio_direction_input(101); |
| 119 | + |
| 120 | + /* GPIOQ7 GPIO_BMC_VGA_FRONT_PRES_L */ |
| 121 | + gpio_direction_input(135); |
| 122 | + |
| 123 | + /* GPIOR1 GPIO_BMC_JTAG_SRST_L */ |
| 124 | + gpio_direction_output(137, 1); |
| 125 | + |
| 126 | + /* BMC_GPIOR2_EXT_HIGHTEMP_L */ |
| 127 | + gpio_direction_output(138, 1); |
| 128 | + |
| 129 | + /* GPIOS0 GPIO_S0_VRHOT_L */ |
| 130 | + gpio_direction_input(144); |
| 131 | + |
| 132 | + /* GPIOS1 GPIO_S1_VRHOT_L */ |
| 133 | + gpio_direction_input(145); |
| 134 | + |
| 135 | + /* GPIOS5 GPIO_BMC_VR_PMBUS_SEL_L */ |
| 136 | + gpio_direction_output(149, 1); |
| 137 | + |
| 138 | + /* GPIOY3 BMC_VGA_SEL */ |
| 139 | + gpio_direction_output(195, 1); |
| 140 | + |
| 141 | + /* GPIOAC1 GPIO_BMC_PCA9554_INT_L */ |
| 142 | + gpio_direction_input(225); |
| 143 | + |
| 144 | + /* GPIO_BMC_READY */ |
| 145 | + gpio_direction_output(229, 1); |
| 146 | + |
| 147 | + /* Enable I2C4 device access */ |
| 148 | + gpio_direction_output(194, 1); |
| 149 | + |
| 150 | + return 0; |
| 151 | +} |
| 152 | + |
| 153 | +int board_early_init_f(void) |
| 154 | +{ |
| 155 | + ast_scu_switch_espi_to_gpio_mode(); |
| 156 | + board_gpio_init(); |
| 157 | + |
| 158 | + return 0; |
| 159 | +} |
| 160 | +#endif /* CONFIG_BOARD_EARLY_INIT_F */ |
| 161 | diff --git a/include/configs/ast-g5-phy.h b/include/configs/ast-g5-phy.h |
| 162 | index ea7c66716a..a5e389616b 100644 |
| 163 | --- a/include/configs/ast-g5-phy.h |
| 164 | +++ b/include/configs/ast-g5-phy.h |
| 165 | @@ -34,4 +34,7 @@ |
| 166 | #define CONFIG_BOARD_LATE_INIT 1 |
| 167 | #define CONFIG_CMD_GPIO 1 /* Enable gpio command in shell */ |
| 168 | |
| 169 | +/* Call board_early_init_f */ |
| 170 | +#define CONFIG_BOARD_EARLY_INIT_F 1 |
| 171 | + |
| 172 | #endif /* __AST_G5_PHY_CONFIG_H */ |
| 173 | -- |
| 174 | 2.17.1 |
| 175 | |