Patrick Williams | b48b7b4 | 2016-08-17 15:04:38 -0500 | [diff] [blame^] | 1 | From 7b2a8a7869d257cba35f53f6d877877c29cdac27 Mon Sep 17 00:00:00 2001 |
| 2 | From: Paul Menzel <paulepanter@users.sourceforge.net> |
| 3 | Date: Sun, 14 Aug 2011 21:53:47 +0200 |
| 4 | Subject: [PATCH 2/4] Revert "fixed:[ios] Add memory barriers to atomic Add/Subtract and Increment/Decrement functions to ensure synchronized accesses." |
| 5 | |
| 6 | This reverts commit 9a10c48710df79118e39e9b3bb0a15bf1fe694d1. |
| 7 | |
| 8 | The build (OpenEmbedded `angstrom-2010.x` for `MACHINE = "beagleboard") fails with the following error. |
| 9 | |
| 10 | make -C xbmc/threads |
| 11 | make[1]: Entering directory `/oe/build-angstrom-next/angstrom-dev/work/armv7a-angstrom-linux-gnueabi/xbmc-10.05-r11+gitr0+9a10c48710df79118e39e9b3bb0a15bf1fe694d1/git/xbmc/threads' |
| 12 | CPP Atomics.o |
| 13 | /tmp/ccIzTm3L.s: Assembler messages: |
| 14 | /tmp/ccIzTm3L.s:40: Error: garbage following instruction -- `dmb ish' |
| 15 | /tmp/ccIzTm3L.s:48: Error: garbage following instruction -- `dmb ish' |
| 16 | /tmp/ccIzTm3L.s:76: Error: garbage following instruction -- `dmb ish' |
| 17 | /tmp/ccIzTm3L.s:83: Error: garbage following instruction -- `dmb ish' |
| 18 | /tmp/ccIzTm3L.s:111: Error: garbage following instruction -- `dmb ish' |
| 19 | /tmp/ccIzTm3L.s:118: Error: garbage following instruction -- `dmb ish' |
| 20 | /tmp/ccIzTm3L.s:145: Error: garbage following instruction -- `dmb ish' |
| 21 | /tmp/ccIzTm3L.s:152: Error: garbage following instruction -- `dmb ish' |
| 22 | /tmp/ccIzTm3L.s:180: Error: garbage following instruction -- `dmb ish' |
| 23 | /tmp/ccIzTm3L.s:187: Error: garbage following instruction -- `dmb ish' |
| 24 | make[1]: *** [Atomics.o] Error 1 |
| 25 | make[1]: Leaving directory `/oe/build-angstrom-next/angstrom-dev/work/armv7a-angstrom-linux-gnueabi/xbmc-10.05-r11+gitr0+9a10c48710df79118e39e9b3bb0a15bf1fe694d1/git/xbmc/threads' |
| 26 | make: *** [xbmc/threads/threads.a] Error 2 |
| 27 | --- |
| 28 | xbmc/threads/Atomics.cpp | 8 -------- |
| 29 | 1 files changed, 0 insertions(+), 8 deletions(-) |
| 30 | |
| 31 | diff --git a/xbmc/threads/Atomics.cpp b/xbmc/threads/Atomics.cpp |
| 32 | index 5b09f18..0a98a7e 100644 |
| 33 | --- a/xbmc/threads/Atomics.cpp |
| 34 | +++ b/xbmc/threads/Atomics.cpp |
| 35 | @@ -194,14 +194,12 @@ long AtomicIncrement(volatile long* pAddr) |
| 36 | { |
| 37 | register long val; |
| 38 | asm volatile ( |
| 39 | - "dmb ish \n" // Memory barrier. Make sure all memory accesses appearing before this complete before any that appear after |
| 40 | "1: \n" |
| 41 | "ldrex %0, [%1] \n" // (val = *pAddr) |
| 42 | "add %0, #1 \n" // (val += 1) |
| 43 | "strex r1, %0, [%1] \n" |
| 44 | "cmp r1, #0 \n" |
| 45 | "bne 1b \n" |
| 46 | - "dmb ish \n" // Memory barrier. |
| 47 | : "=&r" (val) |
| 48 | : "r"(pAddr) |
| 49 | : "r1" |
| 50 | @@ -273,14 +271,12 @@ long AtomicAdd(volatile long* pAddr, long amount) |
| 51 | { |
| 52 | register long val; |
| 53 | asm volatile ( |
| 54 | - "dmb ish \n" // Memory barrier. Make sure all memory accesses appearing before this complete before any that appear after |
| 55 | "1: \n" |
| 56 | "ldrex %0, [%1] \n" // (val = *pAddr) |
| 57 | "add %0, %2 \n" // (val += amount) |
| 58 | "strex r1, %0, [%1] \n" |
| 59 | "cmp r1, #0 \n" |
| 60 | "bne 1b \n" |
| 61 | - "dmb ish \n" // Memory barrier. |
| 62 | : "=&r" (val) |
| 63 | : "r"(pAddr), "r"(amount) |
| 64 | : "r1" |
| 65 | @@ -351,14 +347,12 @@ long AtomicDecrement(volatile long* pAddr) |
| 66 | { |
| 67 | register long val; |
| 68 | asm volatile ( |
| 69 | - "dmb ish \n" // Memory barrier. Make sure all memory accesses appearing before this complete before any that appear after |
| 70 | "1: \n" |
| 71 | "ldrex %0, [%1] \n" // (val = *pAddr) |
| 72 | "sub %0, #1 \n" // (val -= 1) |
| 73 | "strex r1, %0, [%1] \n" |
| 74 | "cmp r1, #0 \n" |
| 75 | "bne 1b \n" |
| 76 | - "dmb ish \n" // Memory barrier. |
| 77 | : "=&r" (val) |
| 78 | : "r"(pAddr) |
| 79 | : "r1" |
| 80 | @@ -431,14 +425,12 @@ long AtomicSubtract(volatile long* pAddr, long amount) |
| 81 | { |
| 82 | register long val; |
| 83 | asm volatile ( |
| 84 | - "dmb ish \n" // Memory barrier. Make sure all memory accesses appearing before this complete before any that appear after |
| 85 | "1: \n" |
| 86 | "ldrex %0, [%1] \n" // (val = *pAddr) |
| 87 | "sub %0, %2 \n" // (val -= amount) |
| 88 | "strex r1, %0, [%1] \n" |
| 89 | "cmp r1, #0 \n" |
| 90 | "bne 1b \n" |
| 91 | - "dmb ish \n" // Memory barrier. |
| 92 | : "=&r" (val) |
| 93 | : "r"(pAddr), "r"(amount) |
| 94 | : "r1" |
| 95 | -- |
| 96 | 1.7.2.5 |
| 97 | |