| Patrick Williams | b48b7b4 | 2016-08-17 15:04:38 -0500 | [diff] [blame^] | 1 | From aaae1616a09d359b52e929f944ca0ceb4bb7f831 Mon Sep 17 00:00:00 2001 |
| 2 | From: Paul Menzel <paulepanter@users.sourceforge.net> |
| 3 | Date: Sun, 14 Aug 2011 21:55:09 +0200 |
| 4 | Subject: [PATCH 3/4] Revert "fixed:[ios] Add memory barriers to cas() assembly to ensure alignment of memory accesses." |
| 5 | |
| 6 | This reverts commit 92bab651e2253d172879995b50985645b77fecd2. |
| 7 | |
| 8 | The build (OpenEmbedded `angstrom-2010.x` for `MACHINE = "beagleboard") fails with the following error. |
| 9 | |
| 10 | CPP Atomics.o |
| 11 | make[1]: Entering directory `/oe/build-angstrom-next/angstrom-dev/work/armv7a-angstrom-linux-gnueabi/xbmc-10.05-r11+gitr0+92bab651e2253d172879995b50985645b77fecd2/git/xbmc/windows' |
| 12 | CPP GUIMediaWindow.o |
| 13 | /tmp/ccrsywuV.s: Assembler messages: |
| 14 | /tmp/ccrsywuV.s:40: Error: garbage following instruction -- `dmb ish' |
| 15 | /tmp/ccrsywuV.s:48: Error: garbage following instruction -- `dmb ish' |
| 16 | make[1]: *** [Atomics.o] Error 1 |
| 17 | make[1]: Leaving directory `/oe/build-angstrom-next/angstrom-dev/work/armv7a-angstrom-linux-gnueabi/xbmc-10.05-r11+gitr0+92bab651e2253d172879995b50985645b77fecd2/git/xbmc/threads' |
| 18 | make: *** [xbmc/threads/threads.a] Error 2 |
| 19 | --- |
| 20 | xbmc/threads/Atomics.cpp | 33 ++++++++++++++++----------------- |
| 21 | 1 files changed, 16 insertions(+), 17 deletions(-) |
| 22 | |
| 23 | diff --git a/xbmc/threads/Atomics.cpp b/xbmc/threads/Atomics.cpp |
| 24 | index 0a98a7e..0967eb2 100644 |
| 25 | --- a/xbmc/threads/Atomics.cpp |
| 26 | +++ b/xbmc/threads/Atomics.cpp |
| 27 | @@ -49,23 +49,22 @@ long cas(volatile long *pAddr, long expectedVal, long swapVal) |
| 28 | #elif defined(__arm__) |
| 29 | long cas(volatile long* pAddr, long expectedVal, long swapVal) |
| 30 | { |
| 31 | - register long prev; |
| 32 | - asm volatile ( |
| 33 | - "dmb ish \n" // Memory barrier. Make sure all memory accesses appearing before this complete before any that appear after |
| 34 | - "1: \n" |
| 35 | - "ldrex %0, [%1] \n" // Load the current value of *pAddr(%1) into prev (%0) and lock pAddr, |
| 36 | - "cmp %0, %2 \n" // Verify that the current value (%0) == old value (%2) |
| 37 | - "bne 2f \n" // Bail if the two values are not equal [not as expected] |
| 38 | - "strex r1, %3, [%1] \n" |
| 39 | - "cmp r1, #0 \n" |
| 40 | - "bne 1b \n" |
| 41 | - "dmb ish \n" // Memory barrier. |
| 42 | - "2: \n" |
| 43 | - : "=&r" (prev) |
| 44 | - : "r"(pAddr), "r"(expectedVal),"r"(swapVal) |
| 45 | - : "r1" |
| 46 | - ); |
| 47 | - return prev; |
| 48 | + return(__sync_val_compare_and_swap(pAddr, expectedVal, swapVal)); |
| 49 | +// register long prev; |
| 50 | +// asm volatile ( |
| 51 | +// "1: \n" |
| 52 | +// "ldrex %0, [%1] \n" /* Load the current value of *pAddr(%1) into prev (%0) and lock pAddr, */ |
| 53 | +// "cmp %0, %2 \n" /* Verify that the current value (%0) == old value (%2) */ |
| 54 | +// "bne 2f \n" /* Bail if the two values are not equal [not as expected] */ |
| 55 | +// "strex r1, %3, [%1] \n" |
| 56 | +// "cmp r1, #0 \n" |
| 57 | +// "bne 1b \n" |
| 58 | +// "2: " |
| 59 | +// : "=&r" (prev) |
| 60 | +// : "r"(pAddr), "r"(expectedVal),"r"(swapVal) |
| 61 | +// : "r1" |
| 62 | +// ); |
| 63 | +// return prev; |
| 64 | } |
| 65 | |
| 66 | #elif defined(__mips__) |
| 67 | -- |
| 68 | 1.7.2.5 |
| 69 | |