blob: 676bdbb3afd4d84c37079e4b47f6108dd1c722dc [file] [log] [blame]
Andrew Geissler595f6302022-01-24 19:11:47 +00001From eb6d6579150bf4684603ce377c51e90ad3bb8109 Mon Sep 17 00:00:00 2001
2From: Khem Raj <raj.khem@gmail.com>
3Date: Sun, 15 Nov 2020 15:32:39 -0800
4Subject: [PATCH] numpy/core: Define RISCV-32 support
5
6Helps compile on riscv32
7
8Upstream-Status: Submitted [https://github.com/numpy/numpy/pull/17780]
9Signed-off-by: Khem Raj <raj.khem@gmail.com>
10---
11 numpy/core/include/numpy/npy_cpu.h | 3 +++
12 numpy/core/include/numpy/npy_endian.h | 1 +
13 2 files changed, 4 insertions(+)
14
15diff --git a/numpy/core/include/numpy/npy_cpu.h b/numpy/core/include/numpy/npy_cpu.h
16index 78d229e..04be511 100644
17--- a/numpy/core/include/numpy/npy_cpu.h
18+++ b/numpy/core/include/numpy/npy_cpu.h
19@@ -19,6 +19,7 @@
20 * NPY_CPU_ARCEB
21 * NPY_CPU_RISCV64
22 * NPY_CPU_LOONGARCH
23+ * NPY_CPU_RISCV32
24 * NPY_CPU_WASM
25 */
26 #ifndef NUMPY_CORE_INCLUDE_NUMPY_NPY_CPU_H_
27@@ -104,6 +105,8 @@
28 #define NPY_CPU_ARCEB
29 #elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 64
30 #define NPY_CPU_RISCV64
31+#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 32
32+ #define NPY_CPU_RISCV32
33 #elif defined(__loongarch__)
34 #define NPY_CPU_LOONGARCH
35 #elif defined(__EMSCRIPTEN__)
36diff --git a/numpy/core/include/numpy/npy_endian.h b/numpy/core/include/numpy/npy_endian.h
37index 5e58a7f..0926212 100644
38--- a/numpy/core/include/numpy/npy_endian.h
39+++ b/numpy/core/include/numpy/npy_endian.h
40@@ -49,6 +49,7 @@
41 || defined(NPY_CPU_PPC64LE) \
42 || defined(NPY_CPU_ARCEL) \
43 || defined(NPY_CPU_RISCV64) \
44+ || defined(NPY_CPU_RISCV32) \
45 || defined(NPY_CPU_LOONGARCH) \
46 || defined(NPY_CPU_WASM)
47 #define NPY_BYTE_ORDER NPY_LITTLE_ENDIAN
48--
492.20.1
50