Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 1 | From eadd9235d084da8022df2d232c90590f2160e433 Mon Sep 17 00:00:00 2001 |
| 2 | From: Viresh Kumar <viresh.kumar@linaro.org> |
| 3 | Date: Tue, 17 Nov 2020 15:32:06 +0530 |
| 4 | Subject: [PATCH 04/22] mailbox: arm_mhuv2: Add driver |
| 5 | |
| 6 | This adds driver for the ARM MHUv2 (Message Handling Unit) mailbox |
| 7 | controller. |
| 8 | |
| 9 | This is based on the accepted DT bindings of the controller and supports |
| 10 | combination of both transport protocols, i.e. doorbell and data-transfer. |
| 11 | |
| 12 | Transmitting and receiving data through the mailbox framework is done |
| 13 | through struct arm_mhuv2_mbox_msg. |
| 14 | |
| 15 | Based on the initial work done by Morten Borup Petersen from ARM. |
| 16 | |
| 17 | Co-developed-by: Tushar Khandelwal <tushar.khandelwal@arm.com> |
| 18 | Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com> |
| 19 | Tested-by: Usama Arif <usama.arif@arm.com> |
| 20 | Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> |
| 21 | Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> |
| 22 | |
| 23 | Upstream-Status: Backport [https://www.lkml.org/lkml/2020/11/17/235] |
| 24 | Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
| 25 | --- |
| 26 | MAINTAINERS | 9 + |
| 27 | drivers/mailbox/Kconfig | 7 + |
| 28 | drivers/mailbox/Makefile | 2 + |
| 29 | drivers/mailbox/arm_mhuv2.c | 1136 +++++++++++++++++++++ |
| 30 | include/linux/mailbox/arm_mhuv2_message.h | 20 + |
| 31 | 5 files changed, 1174 insertions(+) |
| 32 | create mode 100644 drivers/mailbox/arm_mhuv2.c |
| 33 | create mode 100644 include/linux/mailbox/arm_mhuv2_message.h |
| 34 | |
| 35 | diff --git a/MAINTAINERS b/MAINTAINERS |
| 36 | index 354831907474..5234423c477a 100644 |
| 37 | --- a/MAINTAINERS |
| 38 | +++ b/MAINTAINERS |
| 39 | @@ -10459,6 +10459,15 @@ F: drivers/mailbox/ |
| 40 | F: include/linux/mailbox_client.h |
| 41 | F: include/linux/mailbox_controller.h |
| 42 | |
| 43 | +MAILBOX ARM MHUv2 |
| 44 | +M: Viresh Kumar <viresh.kumar@linaro.org> |
| 45 | +M: Tushar Khandelwal <Tushar.Khandelwal@arm.com> |
| 46 | +L: linux-kernel@vger.kernel.org |
| 47 | +S: Maintained |
| 48 | +F: drivers/mailbox/arm_mhuv2.c |
| 49 | +F: include/linux/mailbox/arm_mhuv2_message.h |
| 50 | +F: Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml |
| 51 | + |
| 52 | MAN-PAGES: MANUAL PAGES FOR LINUX -- Sections 2, 3, 4, 5, and 7 |
| 53 | M: Michael Kerrisk <mtk.manpages@gmail.com> |
| 54 | L: linux-man@vger.kernel.org |
| 55 | diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig |
| 56 | index 05b1009e2820..3c0ea96a0a8b 100644 |
| 57 | --- a/drivers/mailbox/Kconfig |
| 58 | +++ b/drivers/mailbox/Kconfig |
| 59 | @@ -16,6 +16,13 @@ config ARM_MHU |
| 60 | The controller has 3 mailbox channels, the last of which can be |
| 61 | used in Secure mode only. |
| 62 | |
| 63 | +config ARM_MHU_V2 |
| 64 | + tristate "ARM MHUv2 Mailbox" |
| 65 | + depends on ARM_AMBA |
| 66 | + help |
| 67 | + Say Y here if you want to build the ARM MHUv2 controller driver, |
| 68 | + which provides unidirectional mailboxes between processing elements. |
| 69 | + |
| 70 | config IMX_MBOX |
| 71 | tristate "i.MX Mailbox" |
| 72 | depends on ARCH_MXC || COMPILE_TEST |
| 73 | diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile |
| 74 | index 2e06e02b2e03..7194fa92c787 100644 |
| 75 | --- a/drivers/mailbox/Makefile |
| 76 | +++ b/drivers/mailbox/Makefile |
| 77 | @@ -7,6 +7,8 @@ obj-$(CONFIG_MAILBOX_TEST) += mailbox-test.o |
| 78 | |
| 79 | obj-$(CONFIG_ARM_MHU) += arm_mhu.o arm_mhu_db.o |
| 80 | |
| 81 | +obj-$(CONFIG_ARM_MHU_V2) += arm_mhuv2.o |
| 82 | + |
| 83 | obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o |
| 84 | |
| 85 | obj-$(CONFIG_ARMADA_37XX_RWTM_MBOX) += armada-37xx-rwtm-mailbox.o |
| 86 | diff --git a/drivers/mailbox/arm_mhuv2.c b/drivers/mailbox/arm_mhuv2.c |
| 87 | new file mode 100644 |
| 88 | index 000000000000..67fb10885bb4 |
| 89 | --- /dev/null |
| 90 | +++ b/drivers/mailbox/arm_mhuv2.c |
| 91 | @@ -0,0 +1,1136 @@ |
| 92 | +// SPDX-License-Identifier: GPL-2.0 |
| 93 | +/* |
| 94 | + * ARM Message Handling Unit Version 2 (MHUv2) driver. |
| 95 | + * |
| 96 | + * Copyright (C) 2020 ARM Ltd. |
| 97 | + * Copyright (C) 2020 Linaro Ltd. |
| 98 | + * |
| 99 | + * An MHUv2 mailbox controller can provide up to 124 channel windows (each 32 |
| 100 | + * bit long) and the driver allows any combination of both the transport |
| 101 | + * protocol modes: data-transfer and doorbell, to be used on those channel |
| 102 | + * windows. |
| 103 | + * |
| 104 | + * The transport protocols should be specified in the device tree entry for the |
| 105 | + * device. The transport protocols determine how the underlying hardware |
| 106 | + * resources of the device are utilized when transmitting data. Refer to the |
| 107 | + * device tree bindings of the ARM MHUv2 controller for more details. |
| 108 | + * |
| 109 | + * The number of registered mailbox channels is dependent on both the underlying |
| 110 | + * hardware - mainly the number of channel windows implemented by the platform, |
| 111 | + * as well as the selected transport protocols. |
| 112 | + * |
| 113 | + * The MHUv2 controller can work both as a sender and receiver, but the driver |
| 114 | + * and the DT bindings support unidirectional transfers for better allocation of |
| 115 | + * the channels. That is, this driver will be probed for two separate devices |
| 116 | + * for each mailbox controller, a sender device and a receiver device. |
| 117 | + */ |
| 118 | + |
| 119 | +#include <linux/amba/bus.h> |
| 120 | +#include <linux/interrupt.h> |
| 121 | +#include <linux/mailbox_controller.h> |
| 122 | +#include <linux/mailbox/arm_mhuv2_message.h> |
| 123 | +#include <linux/module.h> |
| 124 | +#include <linux/of_address.h> |
| 125 | +#include <linux/spinlock.h> |
| 126 | + |
| 127 | +/* ====== MHUv2 Registers ====== */ |
| 128 | + |
| 129 | +/* Maximum number of channel windows */ |
| 130 | +#define MHUV2_CH_WN_MAX 124 |
| 131 | +/* Number of combined interrupt status registers */ |
| 132 | +#define MHUV2_CMB_INT_ST_REG_CNT 4 |
| 133 | +#define MHUV2_STAT_BYTES (sizeof(u32)) |
| 134 | +#define MHUV2_STAT_BITS (MHUV2_STAT_BYTES * __CHAR_BIT__) |
| 135 | + |
| 136 | +#define LSB_MASK(n) ((1 << (n * __CHAR_BIT__)) - 1) |
| 137 | +#define MHUV2_PROTOCOL_PROP "arm,mhuv2-protocols" |
| 138 | + |
| 139 | +/* Register Message Handling Unit Configuration fields */ |
| 140 | +struct mhu_cfg_t { |
| 141 | + u32 num_ch : 7; |
| 142 | + u32 pad : 25; |
| 143 | +} __packed; |
| 144 | + |
| 145 | +/* register Interrupt Status fields */ |
| 146 | +struct int_st_t { |
| 147 | + u32 nr2r : 1; |
| 148 | + u32 r2nr : 1; |
| 149 | + u32 pad : 30; |
| 150 | +} __packed; |
| 151 | + |
| 152 | +/* Register Interrupt Clear fields */ |
| 153 | +struct int_clr_t { |
| 154 | + u32 nr2r : 1; |
| 155 | + u32 r2nr : 1; |
| 156 | + u32 pad : 30; |
| 157 | +} __packed; |
| 158 | + |
| 159 | +/* Register Interrupt Enable fields */ |
| 160 | +struct int_en_t { |
| 161 | + u32 r2nr : 1; |
| 162 | + u32 nr2r : 1; |
| 163 | + u32 chcomb : 1; |
| 164 | + u32 pad : 29; |
| 165 | +} __packed; |
| 166 | + |
| 167 | +/* Register Implementer Identification fields */ |
| 168 | +struct iidr_t { |
| 169 | + u32 implementer : 12; |
| 170 | + u32 revision : 4; |
| 171 | + u32 variant : 4; |
| 172 | + u32 product_id : 12; |
| 173 | +} __packed; |
| 174 | + |
| 175 | +/* Register Architecture Identification Register fields */ |
| 176 | +struct aidr_t { |
| 177 | + u32 arch_minor_rev : 4; |
| 178 | + u32 arch_major_rev : 4; |
| 179 | + u32 pad : 24; |
| 180 | +} __packed; |
| 181 | + |
| 182 | +/* Sender Channel Window fields */ |
| 183 | +struct mhu2_send_ch_wn_reg { |
| 184 | + u32 stat; |
| 185 | + u8 pad1[0x0C - 0x04]; |
| 186 | + u32 stat_set; |
| 187 | + u32 int_st; |
| 188 | + u32 int_clr; |
| 189 | + u32 int_en; |
| 190 | + u8 pad2[0x20 - 0x1C]; |
| 191 | +} __packed; |
| 192 | + |
| 193 | +/* Sender frame register fields */ |
| 194 | +struct mhu2_send_frame_reg { |
| 195 | + struct mhu2_send_ch_wn_reg ch_wn[MHUV2_CH_WN_MAX]; |
| 196 | + struct mhu_cfg_t mhu_cfg; |
| 197 | + u32 resp_cfg; |
| 198 | + u32 access_request; |
| 199 | + u32 access_ready; |
| 200 | + struct int_st_t int_st; |
| 201 | + struct int_clr_t int_clr; |
| 202 | + struct int_en_t int_en; |
| 203 | + u32 reserved0; |
| 204 | + u32 chcomb_int_st[MHUV2_CMB_INT_ST_REG_CNT]; |
| 205 | + u8 pad[0xFC8 - 0xFB0]; |
| 206 | + struct iidr_t iidr; |
| 207 | + struct aidr_t aidr; |
| 208 | +} __packed; |
| 209 | + |
| 210 | +/* Receiver Channel Window fields */ |
| 211 | +struct mhu2_recv_ch_wn_reg { |
| 212 | + u32 stat; |
| 213 | + u32 stat_masked; |
| 214 | + u32 stat_clear; |
| 215 | + u8 reserved0[0x10 - 0x0C]; |
| 216 | + u32 mask; |
| 217 | + u32 mask_set; |
| 218 | + u32 mask_clear; |
| 219 | + u8 pad[0x20 - 0x1C]; |
| 220 | +} __packed; |
| 221 | + |
| 222 | +/* Receiver frame register fields */ |
| 223 | +struct mhu2_recv_frame_reg { |
| 224 | + struct mhu2_recv_ch_wn_reg ch_wn[MHUV2_CH_WN_MAX]; |
| 225 | + struct mhu_cfg_t mhu_cfg; |
| 226 | + u8 reserved0[0xF90 - 0xF84]; |
| 227 | + struct int_st_t int_st; |
| 228 | + struct int_clr_t int_clr; |
| 229 | + struct int_en_t int_en; |
| 230 | + u32 pad; |
| 231 | + u32 chcomb_int_st[MHUV2_CMB_INT_ST_REG_CNT]; |
| 232 | + u8 reserved2[0xFC8 - 0xFB0]; |
| 233 | + struct iidr_t iidr; |
| 234 | + struct aidr_t aidr; |
| 235 | +} __packed; |
| 236 | + |
| 237 | + |
| 238 | +/* ====== MHUv2 data structures ====== */ |
| 239 | + |
| 240 | +enum mhuv2_transport_protocol { |
| 241 | + DOORBELL = 0, |
| 242 | + DATA_TRANSFER = 1 |
| 243 | +}; |
| 244 | + |
| 245 | +enum mhuv2_frame { |
| 246 | + RECEIVER_FRAME, |
| 247 | + SENDER_FRAME |
| 248 | +}; |
| 249 | + |
| 250 | +/** |
| 251 | + * struct mhuv2 - MHUv2 mailbox controller data |
| 252 | + * |
| 253 | + * @mbox: Mailbox controller belonging to the MHU frame. |
| 254 | + * @send/recv: Base address of the register mapping region. |
| 255 | + * @frame: Frame type: RECEIVER_FRAME or SENDER_FRAME. |
| 256 | + * @irq: Interrupt. |
| 257 | + * @windows: Channel windows implemented by the platform. |
| 258 | + * @minor: Minor version of the controller. |
| 259 | + * @length: Length of the protocols array in bytes. |
| 260 | + * @protocols: Raw protocol information, derived from device tree. |
| 261 | + * @doorbell_pending_lock: spinlock required for correct operation of Tx |
| 262 | + * interrupt for doorbells. |
| 263 | + */ |
| 264 | +struct mhuv2 { |
| 265 | + struct mbox_controller mbox; |
| 266 | + union { |
| 267 | + struct mhu2_send_frame_reg __iomem *send; |
| 268 | + struct mhu2_recv_frame_reg __iomem *recv; |
| 269 | + }; |
| 270 | + enum mhuv2_frame frame; |
| 271 | + unsigned int irq; |
| 272 | + unsigned int windows; |
| 273 | + unsigned int minor; |
| 274 | + unsigned int length; |
| 275 | + u32 *protocols; |
| 276 | + |
| 277 | + spinlock_t doorbell_pending_lock; |
| 278 | +}; |
| 279 | + |
| 280 | +#define mhu_from_mbox(_mbox) container_of(_mbox, struct mhuv2, mbox) |
| 281 | + |
| 282 | +/** |
| 283 | + * struct mhuv2_protocol_ops - MHUv2 operations |
| 284 | + * |
| 285 | + * Each transport protocol must provide an implementation of the operations |
| 286 | + * provided here. |
| 287 | + * |
| 288 | + * @rx_startup: Startup callback for receiver. |
| 289 | + * @rx_shutdown: Shutdown callback for receiver. |
| 290 | + * @read_data: Reads and clears newly available data. |
| 291 | + * @tx_startup: Startup callback for receiver. |
| 292 | + * @tx_shutdown: Shutdown callback for receiver. |
| 293 | + * @last_tx_done: Report back if the last tx is completed or not. |
| 294 | + * @send_data: Send data to the receiver. |
| 295 | + */ |
| 296 | +struct mhuv2_protocol_ops { |
| 297 | + int (*rx_startup)(struct mhuv2 *mhu, struct mbox_chan *chan); |
| 298 | + void (*rx_shutdown)(struct mhuv2 *mhu, struct mbox_chan *chan); |
| 299 | + void *(*read_data)(struct mhuv2 *mhu, struct mbox_chan *chan); |
| 300 | + |
| 301 | + void (*tx_startup)(struct mhuv2 *mhu, struct mbox_chan *chan); |
| 302 | + void (*tx_shutdown)(struct mhuv2 *mhu, struct mbox_chan *chan); |
| 303 | + int (*last_tx_done)(struct mhuv2 *mhu, struct mbox_chan *chan); |
| 304 | + int (*send_data)(struct mhuv2 *mhu, struct mbox_chan *chan, void *arg); |
| 305 | +}; |
| 306 | + |
| 307 | +/* |
| 308 | + * MHUv2 mailbox channel's private information |
| 309 | + * |
| 310 | + * @ops: protocol specific ops for the channel. |
| 311 | + * @ch_wn_idx: Channel window index allocated to the channel. |
| 312 | + * @windows: Total number of windows consumed by the channel, only relevant |
| 313 | + * in DATA_TRANSFER protocol. |
| 314 | + * @doorbell: Doorbell bit number within the ch_wn_idx window, only relevant |
| 315 | + * in DOORBELL protocol. |
| 316 | + * @pending: Flag indicating pending doorbell interrupt, only relevant in |
| 317 | + * DOORBELL protocol. |
| 318 | + */ |
| 319 | +struct mhuv2_mbox_chan_priv { |
| 320 | + const struct mhuv2_protocol_ops *ops; |
| 321 | + u32 ch_wn_idx; |
| 322 | + union { |
| 323 | + u32 windows; |
| 324 | + struct { |
| 325 | + u32 doorbell; |
| 326 | + u32 pending; |
| 327 | + }; |
| 328 | + }; |
| 329 | +}; |
| 330 | + |
| 331 | +/* Macro for reading a bitfield within a physically mapped packed struct */ |
| 332 | +#define readl_relaxed_bitfield(_regptr, _field) \ |
| 333 | + ({ \ |
| 334 | + u32 _regval; \ |
| 335 | + _regval = readl_relaxed((_regptr)); \ |
| 336 | + (*(typeof((_regptr)))(&_regval))._field; \ |
| 337 | + }) |
| 338 | + |
| 339 | +/* Macro for writing a bitfield within a physically mapped packed struct */ |
| 340 | +#define writel_relaxed_bitfield(_value, _regptr, _field) \ |
| 341 | + ({ \ |
| 342 | + u32 _regval; \ |
| 343 | + _regval = readl_relaxed(_regptr); \ |
| 344 | + (*(typeof(_regptr))(&_regval))._field = _value; \ |
| 345 | + writel_relaxed(_regval, _regptr); \ |
| 346 | + }) |
| 347 | + |
| 348 | + |
| 349 | +/* =================== Doorbell transport protocol operations =============== */ |
| 350 | + |
| 351 | +static int mhuv2_doorbell_rx_startup(struct mhuv2 *mhu, struct mbox_chan *chan) |
| 352 | +{ |
| 353 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 354 | + |
| 355 | + writel_relaxed(BIT(priv->doorbell), |
| 356 | + &mhu->recv->ch_wn[priv->ch_wn_idx].mask_clear); |
| 357 | + return 0; |
| 358 | +} |
| 359 | + |
| 360 | +static void mhuv2_doorbell_rx_shutdown(struct mhuv2 *mhu, |
| 361 | + struct mbox_chan *chan) |
| 362 | +{ |
| 363 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 364 | + |
| 365 | + writel_relaxed(BIT(priv->doorbell), |
| 366 | + &mhu->recv->ch_wn[priv->ch_wn_idx].mask_set); |
| 367 | +} |
| 368 | + |
| 369 | +static void *mhuv2_doorbell_read_data(struct mhuv2 *mhu, struct mbox_chan *chan) |
| 370 | +{ |
| 371 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 372 | + |
| 373 | + writel_relaxed(BIT(priv->doorbell), |
| 374 | + &mhu->recv->ch_wn[priv->ch_wn_idx].stat_clear); |
| 375 | + return NULL; |
| 376 | +} |
| 377 | + |
| 378 | +static int mhuv2_doorbell_last_tx_done(struct mhuv2 *mhu, |
| 379 | + struct mbox_chan *chan) |
| 380 | +{ |
| 381 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 382 | + |
| 383 | + return !(readl_relaxed(&mhu->send->ch_wn[priv->ch_wn_idx].stat) & |
| 384 | + BIT(priv->doorbell)); |
| 385 | +} |
| 386 | + |
| 387 | +static int mhuv2_doorbell_send_data(struct mhuv2 *mhu, struct mbox_chan *chan, |
| 388 | + void *arg) |
| 389 | +{ |
| 390 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 391 | + unsigned long flags; |
| 392 | + |
| 393 | + spin_lock_irqsave(&mhu->doorbell_pending_lock, flags); |
| 394 | + |
| 395 | + priv->pending = 1; |
| 396 | + writel_relaxed(BIT(priv->doorbell), |
| 397 | + &mhu->send->ch_wn[priv->ch_wn_idx].stat_set); |
| 398 | + |
| 399 | + spin_unlock_irqrestore(&mhu->doorbell_pending_lock, flags); |
| 400 | + |
| 401 | + return 0; |
| 402 | +} |
| 403 | + |
| 404 | +static const struct mhuv2_protocol_ops mhuv2_doorbell_ops = { |
| 405 | + .rx_startup = mhuv2_doorbell_rx_startup, |
| 406 | + .rx_shutdown = mhuv2_doorbell_rx_shutdown, |
| 407 | + .read_data = mhuv2_doorbell_read_data, |
| 408 | + .last_tx_done = mhuv2_doorbell_last_tx_done, |
| 409 | + .send_data = mhuv2_doorbell_send_data, |
| 410 | +}; |
| 411 | +#define IS_PROTOCOL_DOORBELL(_priv) (_priv->ops == &mhuv2_doorbell_ops) |
| 412 | + |
| 413 | +/* ============= Data transfer transport protocol operations ================ */ |
| 414 | + |
| 415 | +static int mhuv2_data_transfer_rx_startup(struct mhuv2 *mhu, |
| 416 | + struct mbox_chan *chan) |
| 417 | +{ |
| 418 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 419 | + int i = priv->ch_wn_idx + priv->windows - 1; |
| 420 | + |
| 421 | + /* |
| 422 | + * The protocol mandates that all but the last status register must be |
| 423 | + * masked. |
| 424 | + */ |
| 425 | + writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_clear); |
| 426 | + return 0; |
| 427 | +} |
| 428 | + |
| 429 | +static void mhuv2_data_transfer_rx_shutdown(struct mhuv2 *mhu, |
| 430 | + struct mbox_chan *chan) |
| 431 | +{ |
| 432 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 433 | + int i = priv->ch_wn_idx + priv->windows - 1; |
| 434 | + |
| 435 | + writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_set); |
| 436 | +} |
| 437 | + |
| 438 | +static void *mhuv2_data_transfer_read_data(struct mhuv2 *mhu, |
| 439 | + struct mbox_chan *chan) |
| 440 | +{ |
| 441 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 442 | + const int windows = priv->windows; |
| 443 | + struct arm_mhuv2_mbox_msg *msg; |
| 444 | + u32 *data; |
| 445 | + int i, idx; |
| 446 | + |
| 447 | + msg = kzalloc(sizeof(*msg) + windows * MHUV2_STAT_BYTES, GFP_KERNEL); |
| 448 | + if (!msg) |
| 449 | + return ERR_PTR(-ENOMEM); |
| 450 | + |
| 451 | + data = msg->data = msg + 1; |
| 452 | + msg->len = windows * MHUV2_STAT_BYTES; |
| 453 | + |
| 454 | + /* |
| 455 | + * Messages are expected in order of most significant word to least |
| 456 | + * significant word. Refer mhuv2_data_transfer_send_data() for more |
| 457 | + * details. |
| 458 | + * |
| 459 | + * We also need to read the stat register instead of stat_masked, as we |
| 460 | + * masked all but the last window. |
| 461 | + * |
| 462 | + * Last channel window must be cleared as the final operation. Upon |
| 463 | + * clearing the last channel window register, which is unmasked in |
| 464 | + * data-transfer protocol, the interrupt is de-asserted. |
| 465 | + */ |
| 466 | + for (i = 0; i < windows; i++) { |
| 467 | + idx = priv->ch_wn_idx + i; |
| 468 | + data[windows - 1 - i] = readl_relaxed(&mhu->recv->ch_wn[idx].stat); |
| 469 | + writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[idx].stat_clear); |
| 470 | + } |
| 471 | + |
| 472 | + return msg; |
| 473 | +} |
| 474 | + |
| 475 | +static void mhuv2_data_transfer_tx_startup(struct mhuv2 *mhu, |
| 476 | + struct mbox_chan *chan) |
| 477 | +{ |
| 478 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 479 | + int i = priv->ch_wn_idx + priv->windows - 1; |
| 480 | + |
| 481 | + /* Enable interrupts only for the last window */ |
| 482 | + if (mhu->minor) { |
| 483 | + writel_relaxed(0x1, &mhu->send->ch_wn[i].int_clr); |
| 484 | + writel_relaxed(0x1, &mhu->send->ch_wn[i].int_en); |
| 485 | + } |
| 486 | +} |
| 487 | + |
| 488 | +static void mhuv2_data_transfer_tx_shutdown(struct mhuv2 *mhu, |
| 489 | + struct mbox_chan *chan) |
| 490 | +{ |
| 491 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 492 | + int i = priv->ch_wn_idx + priv->windows - 1; |
| 493 | + |
| 494 | + if (mhu->minor) |
| 495 | + writel_relaxed(0x0, &mhu->send->ch_wn[i].int_en); |
| 496 | +} |
| 497 | + |
| 498 | +static int mhuv2_data_transfer_last_tx_done(struct mhuv2 *mhu, |
| 499 | + struct mbox_chan *chan) |
| 500 | +{ |
| 501 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 502 | + int i = priv->ch_wn_idx + priv->windows - 1; |
| 503 | + |
| 504 | + /* Just checking the last channel window should be enough */ |
| 505 | + return !readl_relaxed(&mhu->send->ch_wn[i].stat); |
| 506 | +} |
| 507 | + |
| 508 | +/* |
| 509 | + * Message will be transmitted from most significant to least significant word. |
| 510 | + * This is to allow for messages shorter than channel windows to still trigger |
| 511 | + * the receiver interrupt which gets activated when the last stat register is |
| 512 | + * written. As an example, a 6-word message is to be written on a 4-channel MHU |
| 513 | + * connection: Registers marked with '*' are masked, and will not generate an |
| 514 | + * interrupt on the receiver side once written. |
| 515 | + * |
| 516 | + * u32 *data = [0x00000001], [0x00000002], [0x00000003], [0x00000004], |
| 517 | + * [0x00000005], [0x00000006] |
| 518 | + * |
| 519 | + * ROUND 1: |
| 520 | + * stat reg To write Write sequence |
| 521 | + * [ stat 3 ] <- [0x00000001] 4 <- triggers interrupt on receiver |
| 522 | + * [ stat 2 ] <- [0x00000002] 3 |
| 523 | + * [ stat 1 ] <- [0x00000003] 2 |
| 524 | + * [ stat 0 ] <- [0x00000004] 1 |
| 525 | + * |
| 526 | + * data += 4 // Increment data pointer by number of stat regs |
| 527 | + * |
| 528 | + * ROUND 2: |
| 529 | + * stat reg To write Write sequence |
| 530 | + * [ stat 3 ] <- [0x00000005] 2 <- triggers interrupt on receiver |
| 531 | + * [ stat 2 ] <- [0x00000006] 1 |
| 532 | + * [ stat 1 ] <- [0x00000000] |
| 533 | + * [ stat 0 ] <- [0x00000000] |
| 534 | + */ |
| 535 | +static int mhuv2_data_transfer_send_data(struct mhuv2 *mhu, |
| 536 | + struct mbox_chan *chan, void *arg) |
| 537 | +{ |
| 538 | + const struct arm_mhuv2_mbox_msg *msg = arg; |
| 539 | + int bytes_left = msg->len, bytes_to_send, bytes_in_round, i; |
| 540 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 541 | + int windows = priv->windows; |
| 542 | + u32 *data = msg->data, word; |
| 543 | + |
| 544 | + while (bytes_left) { |
| 545 | + if (!data[0]) { |
| 546 | + dev_err(mhu->mbox.dev, "Data aligned at first window can't be zero to guarantee interrupt generation at receiver"); |
| 547 | + return -EINVAL; |
| 548 | + } |
| 549 | + |
| 550 | + while(!mhuv2_data_transfer_last_tx_done(mhu, chan)) |
| 551 | + continue; |
| 552 | + |
| 553 | + bytes_in_round = min(bytes_left, (int)(windows * MHUV2_STAT_BYTES)); |
| 554 | + |
| 555 | + for (i = windows - 1; i >= 0; i--) { |
| 556 | + /* Data less than windows can transfer ? */ |
| 557 | + if (unlikely(bytes_in_round <= i * MHUV2_STAT_BYTES)) |
| 558 | + continue; |
| 559 | + |
| 560 | + word = data[i]; |
| 561 | + bytes_to_send = bytes_in_round & (MHUV2_STAT_BYTES - 1); |
| 562 | + if (unlikely(bytes_to_send)) |
| 563 | + word &= LSB_MASK(bytes_to_send); |
| 564 | + else |
| 565 | + bytes_to_send = MHUV2_STAT_BYTES; |
| 566 | + |
| 567 | + writel_relaxed(word, &mhu->send->ch_wn[priv->ch_wn_idx + windows - 1 - i].stat_set); |
| 568 | + bytes_left -= bytes_to_send; |
| 569 | + bytes_in_round -= bytes_to_send; |
| 570 | + } |
| 571 | + |
| 572 | + data += windows; |
| 573 | + } |
| 574 | + |
| 575 | + return 0; |
| 576 | +} |
| 577 | + |
| 578 | +static const struct mhuv2_protocol_ops mhuv2_data_transfer_ops = { |
| 579 | + .rx_startup = mhuv2_data_transfer_rx_startup, |
| 580 | + .rx_shutdown = mhuv2_data_transfer_rx_shutdown, |
| 581 | + .read_data = mhuv2_data_transfer_read_data, |
| 582 | + .tx_startup = mhuv2_data_transfer_tx_startup, |
| 583 | + .tx_shutdown = mhuv2_data_transfer_tx_shutdown, |
| 584 | + .last_tx_done = mhuv2_data_transfer_last_tx_done, |
| 585 | + .send_data = mhuv2_data_transfer_send_data, |
| 586 | +}; |
| 587 | + |
| 588 | +/* Interrupt handlers */ |
| 589 | + |
| 590 | +static struct mbox_chan *get_irq_chan_comb(struct mhuv2 *mhu, u32 *reg) |
| 591 | +{ |
| 592 | + struct mbox_chan *chans = mhu->mbox.chans; |
| 593 | + int channel = 0, i, offset = 0, windows, protocol, ch_wn; |
| 594 | + u32 stat; |
| 595 | + |
| 596 | + for (i = 0; i < MHUV2_CMB_INT_ST_REG_CNT; i++) { |
| 597 | + stat = readl_relaxed(reg + i); |
| 598 | + if (!stat) |
| 599 | + continue; |
| 600 | + |
| 601 | + ch_wn = i * MHUV2_STAT_BITS + __builtin_ctz(stat); |
| 602 | + |
| 603 | + for (i = 0; i < mhu->length; i += 2) { |
| 604 | + protocol = mhu->protocols[i]; |
| 605 | + windows = mhu->protocols[i + 1]; |
| 606 | + |
| 607 | + if (ch_wn >= offset + windows) { |
| 608 | + if (protocol == DOORBELL) |
| 609 | + channel += MHUV2_STAT_BITS * windows; |
| 610 | + else |
| 611 | + channel++; |
| 612 | + |
| 613 | + offset += windows; |
| 614 | + continue; |
| 615 | + } |
| 616 | + |
| 617 | + /* Return first chan of the window in doorbell mode */ |
| 618 | + if (protocol == DOORBELL) |
| 619 | + channel += MHUV2_STAT_BITS * (ch_wn - offset); |
| 620 | + |
| 621 | + return &chans[channel]; |
| 622 | + } |
| 623 | + } |
| 624 | + |
| 625 | + return ERR_PTR(-EIO); |
| 626 | +} |
| 627 | + |
| 628 | +static irqreturn_t mhuv2_sender_interrupt(int irq, void *data) |
| 629 | +{ |
| 630 | + struct mhuv2 *mhu = data; |
| 631 | + struct device *dev = mhu->mbox.dev; |
| 632 | + struct mhuv2_mbox_chan_priv *priv; |
| 633 | + struct mbox_chan *chan; |
| 634 | + unsigned long flags; |
| 635 | + int i, found = 0; |
| 636 | + u32 stat; |
| 637 | + |
| 638 | + chan = get_irq_chan_comb(mhu, mhu->send->chcomb_int_st); |
| 639 | + if (IS_ERR(chan)) { |
| 640 | + dev_warn(dev, "Failed to find channel for the Tx interrupt\n"); |
| 641 | + return IRQ_NONE; |
| 642 | + } |
| 643 | + priv = chan->con_priv; |
| 644 | + |
| 645 | + if (!IS_PROTOCOL_DOORBELL(priv)) { |
| 646 | + writel_relaxed(1, &mhu->send->ch_wn[priv->ch_wn_idx + priv->windows - 1].int_clr); |
| 647 | + |
| 648 | + if (chan->cl) { |
| 649 | + mbox_chan_txdone(chan, 0); |
| 650 | + return IRQ_HANDLED; |
| 651 | + } |
| 652 | + |
| 653 | + dev_warn(dev, "Tx interrupt Received on channel (%u) not currently attached to a mailbox client\n", |
| 654 | + priv->ch_wn_idx); |
| 655 | + return IRQ_NONE; |
| 656 | + } |
| 657 | + |
| 658 | + /* Clear the interrupt first, so we don't miss any doorbell later */ |
| 659 | + writel_relaxed(1, &mhu->send->ch_wn[priv->ch_wn_idx].int_clr); |
| 660 | + |
| 661 | + /* |
| 662 | + * In Doorbell mode, make sure no new transitions happen while the |
| 663 | + * interrupt handler is trying to find the finished doorbell tx |
| 664 | + * operations, else we may think few of the transfers were complete |
| 665 | + * before they actually were. |
| 666 | + */ |
| 667 | + spin_lock_irqsave(&mhu->doorbell_pending_lock, flags); |
| 668 | + |
| 669 | + /* |
| 670 | + * In case of doorbell mode, the first channel of the window is returned |
| 671 | + * by get_irq_chan_comb(). Find all the pending channels here. |
| 672 | + */ |
| 673 | + stat = readl_relaxed(&mhu->send->ch_wn[priv->ch_wn_idx].stat); |
| 674 | + |
| 675 | + for (i = 0; i < MHUV2_STAT_BITS; i++) { |
| 676 | + priv = chan[i].con_priv; |
| 677 | + |
| 678 | + /* Find cases where pending was 1, but stat's bit is cleared */ |
| 679 | + if (priv->pending ^ ((stat >> i) & 0x1)) { |
| 680 | + BUG_ON(!priv->pending); |
| 681 | + |
| 682 | + if (!chan->cl) { |
| 683 | + dev_warn(dev, "Tx interrupt received on doorbell (%u : %u) channel not currently attached to a mailbox client\n", |
| 684 | + priv->ch_wn_idx, i); |
| 685 | + continue; |
| 686 | + } |
| 687 | + |
| 688 | + mbox_chan_txdone(&chan[i], 0); |
| 689 | + priv->pending = 0; |
| 690 | + found++; |
| 691 | + } |
| 692 | + } |
| 693 | + |
| 694 | + spin_unlock_irqrestore(&mhu->doorbell_pending_lock, flags); |
| 695 | + |
| 696 | + if (!found) { |
| 697 | + /* |
| 698 | + * We may have already processed the doorbell in the previous |
| 699 | + * iteration if the interrupt came right after we cleared it but |
| 700 | + * before we read the stat register. |
| 701 | + */ |
| 702 | + dev_dbg(dev, "Couldn't find the doorbell (%u) for the Tx interrupt interrupt\n", |
| 703 | + priv->ch_wn_idx); |
| 704 | + return IRQ_NONE; |
| 705 | + } |
| 706 | + |
| 707 | + return IRQ_HANDLED; |
| 708 | +} |
| 709 | + |
| 710 | +static struct mbox_chan *get_irq_chan_comb_rx(struct mhuv2 *mhu) |
| 711 | +{ |
| 712 | + struct mhuv2_mbox_chan_priv *priv; |
| 713 | + struct mbox_chan *chan; |
| 714 | + u32 stat; |
| 715 | + |
| 716 | + chan = get_irq_chan_comb(mhu, mhu->recv->chcomb_int_st); |
| 717 | + if (IS_ERR(chan)) |
| 718 | + return chan; |
| 719 | + |
| 720 | + priv = chan->con_priv; |
| 721 | + if (!IS_PROTOCOL_DOORBELL(priv)) |
| 722 | + return chan; |
| 723 | + |
| 724 | + /* |
| 725 | + * In case of doorbell mode, the first channel of the window is returned |
| 726 | + * by the routine. Find the exact channel here. |
| 727 | + */ |
| 728 | + stat = readl_relaxed(&mhu->recv->ch_wn[priv->ch_wn_idx].stat_masked); |
| 729 | + BUG_ON(!stat); |
| 730 | + |
| 731 | + return chan + __builtin_ctz(stat); |
| 732 | +} |
| 733 | + |
| 734 | +static struct mbox_chan *get_irq_chan_stat_rx(struct mhuv2 *mhu) |
| 735 | +{ |
| 736 | + struct mbox_chan *chans = mhu->mbox.chans; |
| 737 | + struct mhuv2_mbox_chan_priv *priv; |
| 738 | + u32 stat; |
| 739 | + int i = 0; |
| 740 | + |
| 741 | + while (i < mhu->mbox.num_chans) { |
| 742 | + priv = chans[i].con_priv; |
| 743 | + stat = readl_relaxed(&mhu->recv->ch_wn[priv->ch_wn_idx].stat_masked); |
| 744 | + |
| 745 | + if (stat) { |
| 746 | + if (IS_PROTOCOL_DOORBELL(priv)) |
| 747 | + i += __builtin_ctz(stat); |
| 748 | + return &chans[i]; |
| 749 | + } |
| 750 | + |
| 751 | + i += IS_PROTOCOL_DOORBELL(priv) ? MHUV2_STAT_BITS : 1; |
| 752 | + } |
| 753 | + |
| 754 | + return ERR_PTR(-EIO); |
| 755 | +} |
| 756 | + |
| 757 | +static struct mbox_chan *get_irq_chan_rx(struct mhuv2 *mhu) |
| 758 | +{ |
| 759 | + if (!mhu->minor) |
| 760 | + return get_irq_chan_stat_rx(mhu); |
| 761 | + |
| 762 | + return get_irq_chan_comb_rx(mhu); |
| 763 | +} |
| 764 | + |
| 765 | +static irqreturn_t mhuv2_receiver_interrupt(int irq, void *arg) |
| 766 | +{ |
| 767 | + struct mhuv2 *mhu = arg; |
| 768 | + struct mbox_chan *chan = get_irq_chan_rx(mhu); |
| 769 | + struct device *dev = mhu->mbox.dev; |
| 770 | + struct mhuv2_mbox_chan_priv *priv; |
| 771 | + int ret = IRQ_NONE; |
| 772 | + void *data; |
| 773 | + |
| 774 | + if (IS_ERR(chan)) { |
| 775 | + dev_warn(dev, "Failed to find channel for the rx interrupt\n"); |
| 776 | + return IRQ_NONE; |
| 777 | + } |
| 778 | + priv = chan->con_priv; |
| 779 | + |
| 780 | + /* Read and clear the data first */ |
| 781 | + data = priv->ops->read_data(mhu, chan); |
| 782 | + |
| 783 | + if (!chan->cl) { |
| 784 | + dev_warn(dev, "Received data on channel (%u) not currently attached to a mailbox client\n", |
| 785 | + priv->ch_wn_idx); |
| 786 | + } else if (IS_ERR(data)) { |
| 787 | + dev_err(dev, "Failed to read data: %lu\n", PTR_ERR(data)); |
| 788 | + } else { |
| 789 | + mbox_chan_received_data(chan, data); |
| 790 | + ret = IRQ_HANDLED; |
| 791 | + } |
| 792 | + |
| 793 | + kfree(data); |
| 794 | + return ret; |
| 795 | +} |
| 796 | + |
| 797 | +/* Sender and receiver ops */ |
| 798 | +static bool mhuv2_sender_last_tx_done(struct mbox_chan *chan) |
| 799 | +{ |
| 800 | + struct mhuv2 *mhu = mhu_from_mbox(chan->mbox); |
| 801 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 802 | + |
| 803 | + return priv->ops->last_tx_done(mhu, chan); |
| 804 | +} |
| 805 | + |
| 806 | +static int mhuv2_sender_send_data(struct mbox_chan *chan, void *data) |
| 807 | +{ |
| 808 | + struct mhuv2 *mhu = mhu_from_mbox(chan->mbox); |
| 809 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 810 | + |
| 811 | + if (!priv->ops->last_tx_done(mhu, chan)) |
| 812 | + return -EBUSY; |
| 813 | + |
| 814 | + return priv->ops->send_data(mhu, chan, data); |
| 815 | +} |
| 816 | + |
| 817 | +static int mhuv2_sender_startup(struct mbox_chan *chan) |
| 818 | +{ |
| 819 | + struct mhuv2 *mhu = mhu_from_mbox(chan->mbox); |
| 820 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 821 | + |
| 822 | + if (priv->ops->tx_startup) |
| 823 | + priv->ops->tx_startup(mhu, chan); |
| 824 | + return 0; |
| 825 | +} |
| 826 | + |
| 827 | +static void mhuv2_sender_shutdown(struct mbox_chan *chan) |
| 828 | +{ |
| 829 | + struct mhuv2 *mhu = mhu_from_mbox(chan->mbox); |
| 830 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 831 | + |
| 832 | + if (priv->ops->tx_shutdown) |
| 833 | + priv->ops->tx_shutdown(mhu, chan); |
| 834 | +} |
| 835 | + |
| 836 | +static const struct mbox_chan_ops mhuv2_sender_ops = { |
| 837 | + .send_data = mhuv2_sender_send_data, |
| 838 | + .startup = mhuv2_sender_startup, |
| 839 | + .shutdown = mhuv2_sender_shutdown, |
| 840 | + .last_tx_done = mhuv2_sender_last_tx_done, |
| 841 | +}; |
| 842 | + |
| 843 | +static int mhuv2_receiver_startup(struct mbox_chan *chan) |
| 844 | +{ |
| 845 | + struct mhuv2 *mhu = mhu_from_mbox(chan->mbox); |
| 846 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 847 | + |
| 848 | + return priv->ops->rx_startup(mhu, chan); |
| 849 | +} |
| 850 | + |
| 851 | +static void mhuv2_receiver_shutdown(struct mbox_chan *chan) |
| 852 | +{ |
| 853 | + struct mhuv2 *mhu = mhu_from_mbox(chan->mbox); |
| 854 | + struct mhuv2_mbox_chan_priv *priv = chan->con_priv; |
| 855 | + |
| 856 | + priv->ops->rx_shutdown(mhu, chan); |
| 857 | +} |
| 858 | + |
| 859 | +static int mhuv2_receiver_send_data(struct mbox_chan *chan, void *data) |
| 860 | +{ |
| 861 | + dev_err(chan->mbox->dev, |
| 862 | + "Trying to transmit on a receiver MHU frame\n"); |
| 863 | + return -EIO; |
| 864 | +} |
| 865 | + |
| 866 | +static bool mhuv2_receiver_last_tx_done(struct mbox_chan *chan) |
| 867 | +{ |
| 868 | + dev_err(chan->mbox->dev, "Trying to Tx poll on a receiver MHU frame\n"); |
| 869 | + return true; |
| 870 | +} |
| 871 | + |
| 872 | +static const struct mbox_chan_ops mhuv2_receiver_ops = { |
| 873 | + .send_data = mhuv2_receiver_send_data, |
| 874 | + .startup = mhuv2_receiver_startup, |
| 875 | + .shutdown = mhuv2_receiver_shutdown, |
| 876 | + .last_tx_done = mhuv2_receiver_last_tx_done, |
| 877 | +}; |
| 878 | + |
| 879 | +static struct mbox_chan *mhuv2_mbox_of_xlate(struct mbox_controller *mbox, |
| 880 | + const struct of_phandle_args *pa) |
| 881 | +{ |
| 882 | + struct mhuv2 *mhu = mhu_from_mbox(mbox); |
| 883 | + struct mbox_chan *chans = mbox->chans; |
| 884 | + int channel = 0, i, offset, doorbell, protocol, windows; |
| 885 | + |
| 886 | + if (pa->args_count != 2) |
| 887 | + return ERR_PTR(-EINVAL); |
| 888 | + |
| 889 | + offset = pa->args[0]; |
| 890 | + doorbell = pa->args[1]; |
| 891 | + if (doorbell >= MHUV2_STAT_BITS) |
| 892 | + goto out; |
| 893 | + |
| 894 | + for (i = 0; i < mhu->length; i += 2) { |
| 895 | + protocol = mhu->protocols[i]; |
| 896 | + windows = mhu->protocols[i + 1]; |
| 897 | + |
| 898 | + if (protocol == DOORBELL) { |
| 899 | + if (offset < windows) |
| 900 | + return &chans[channel + MHUV2_STAT_BITS * offset + doorbell]; |
| 901 | + |
| 902 | + channel += MHUV2_STAT_BITS * windows; |
| 903 | + offset -= windows; |
| 904 | + } else { |
| 905 | + if (offset == 0) { |
| 906 | + if (doorbell) |
| 907 | + goto out; |
| 908 | + |
| 909 | + return &chans[channel]; |
| 910 | + } |
| 911 | + |
| 912 | + channel++; |
| 913 | + offset--; |
| 914 | + } |
| 915 | + } |
| 916 | + |
| 917 | +out: |
| 918 | + dev_err(mbox->dev, "Couldn't xlate to a valid channel (%d: %d)\n", |
| 919 | + pa->args[0], doorbell); |
| 920 | + return ERR_PTR(-ENODEV); |
| 921 | +} |
| 922 | + |
| 923 | +static int mhuv2_verify_protocol(struct mhuv2 *mhu) |
| 924 | +{ |
| 925 | + struct device *dev = mhu->mbox.dev; |
| 926 | + int protocol, windows, channels = 0, total_windows = 0, i; |
| 927 | + |
| 928 | + for (i = 0; i < mhu->length; i += 2) { |
| 929 | + protocol = mhu->protocols[i]; |
| 930 | + windows = mhu->protocols[i + 1]; |
| 931 | + |
| 932 | + if (!windows) { |
| 933 | + dev_err(dev, "Window size can't be zero (%d)\n", i); |
| 934 | + return -EINVAL; |
| 935 | + } |
| 936 | + total_windows += windows; |
| 937 | + |
| 938 | + if (protocol == DOORBELL) { |
| 939 | + channels += MHUV2_STAT_BITS * windows; |
| 940 | + } else if (protocol == DATA_TRANSFER) { |
| 941 | + channels++; |
| 942 | + } else { |
| 943 | + dev_err(dev, "Invalid protocol (%d) present in %s property at index %d\n", |
| 944 | + protocol, MHUV2_PROTOCOL_PROP, i); |
| 945 | + return -EINVAL; |
| 946 | + } |
| 947 | + } |
| 948 | + |
| 949 | + if (total_windows > mhu->windows) { |
| 950 | + dev_err(dev, "Channel windows can't be more than what's implemented by the hardware ( %d: %d)\n", |
| 951 | + total_windows, mhu->windows); |
| 952 | + return -EINVAL; |
| 953 | + } |
| 954 | + |
| 955 | + mhu->mbox.num_chans = channels; |
| 956 | + return 0; |
| 957 | +} |
| 958 | + |
| 959 | +static int mhuv2_allocate_channels(struct mhuv2 *mhu) |
| 960 | +{ |
| 961 | + struct mbox_controller *mbox = &mhu->mbox; |
| 962 | + struct mhuv2_mbox_chan_priv *priv; |
| 963 | + struct device *dev = mbox->dev; |
| 964 | + struct mbox_chan *chans; |
| 965 | + int protocol, windows = 0, next_window = 0, i, j, k; |
| 966 | + |
| 967 | + chans = devm_kcalloc(dev, mbox->num_chans, sizeof(*chans), GFP_KERNEL); |
| 968 | + if (!chans) |
| 969 | + return -ENOMEM; |
| 970 | + |
| 971 | + mbox->chans = chans; |
| 972 | + |
| 973 | + for (i = 0; i < mhu->length; i += 2) { |
| 974 | + next_window += windows; |
| 975 | + |
| 976 | + protocol = mhu->protocols[i]; |
| 977 | + windows = mhu->protocols[i + 1]; |
| 978 | + |
| 979 | + if (protocol == DATA_TRANSFER) { |
| 980 | + priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL); |
| 981 | + if (!priv) |
| 982 | + return -ENOMEM; |
| 983 | + |
| 984 | + priv->ch_wn_idx = next_window; |
| 985 | + priv->ops = &mhuv2_data_transfer_ops; |
| 986 | + priv->windows = windows; |
| 987 | + chans++->con_priv = priv; |
| 988 | + continue; |
| 989 | + } |
| 990 | + |
| 991 | + for (j = 0; j < windows; j++) { |
| 992 | + for (k = 0; k < MHUV2_STAT_BITS; k++) { |
| 993 | + priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL); |
| 994 | + if (!priv) |
| 995 | + return -ENOMEM; |
| 996 | + |
| 997 | + priv->ch_wn_idx = next_window + j; |
| 998 | + priv->ops = &mhuv2_doorbell_ops; |
| 999 | + priv->doorbell = k; |
| 1000 | + chans++->con_priv = priv; |
| 1001 | + } |
| 1002 | + |
| 1003 | + /* |
| 1004 | + * Permanently enable interrupt as we can't |
| 1005 | + * control it per doorbell. |
| 1006 | + */ |
| 1007 | + if (mhu->frame == SENDER_FRAME && mhu->minor) |
| 1008 | + writel_relaxed(0x1, &mhu->send->ch_wn[priv->ch_wn_idx].int_en); |
| 1009 | + } |
| 1010 | + } |
| 1011 | + |
| 1012 | + /* Make sure we have initialized all channels */ |
| 1013 | + BUG_ON(chans - mbox->chans != mbox->num_chans); |
| 1014 | + |
| 1015 | + return 0; |
| 1016 | +} |
| 1017 | + |
| 1018 | +static int mhuv2_parse_channels(struct mhuv2 *mhu) |
| 1019 | +{ |
| 1020 | + struct device *dev = mhu->mbox.dev; |
| 1021 | + const struct device_node *np = dev->of_node; |
| 1022 | + int ret, count; |
| 1023 | + u32 *protocols; |
| 1024 | + |
| 1025 | + count = of_property_count_u32_elems(np, MHUV2_PROTOCOL_PROP); |
| 1026 | + if (count <= 0 || count % 2) { |
| 1027 | + dev_err(dev, "Invalid %s property (%d)\n", MHUV2_PROTOCOL_PROP, |
| 1028 | + count); |
| 1029 | + return -EINVAL; |
| 1030 | + } |
| 1031 | + |
| 1032 | + protocols = devm_kmalloc_array(dev, count, sizeof(*protocols), GFP_KERNEL); |
| 1033 | + if (!protocols) |
| 1034 | + return -ENOMEM; |
| 1035 | + |
| 1036 | + ret = of_property_read_u32_array(np, MHUV2_PROTOCOL_PROP, protocols, count); |
| 1037 | + if (ret) { |
| 1038 | + dev_err(dev, "Failed to read %s property: %d\n", |
| 1039 | + MHUV2_PROTOCOL_PROP, ret); |
| 1040 | + return ret; |
| 1041 | + } |
| 1042 | + |
| 1043 | + mhu->protocols = protocols; |
| 1044 | + mhu->length = count; |
| 1045 | + |
| 1046 | + ret = mhuv2_verify_protocol(mhu); |
| 1047 | + if (ret) |
| 1048 | + return ret; |
| 1049 | + |
| 1050 | + return mhuv2_allocate_channels(mhu); |
| 1051 | +} |
| 1052 | + |
| 1053 | +static int mhuv2_tx_init(struct amba_device *adev, struct mhuv2 *mhu, |
| 1054 | + void __iomem *reg) |
| 1055 | +{ |
| 1056 | + struct device *dev = mhu->mbox.dev; |
| 1057 | + int ret, i; |
| 1058 | + |
| 1059 | + mhu->frame = SENDER_FRAME; |
| 1060 | + mhu->mbox.ops = &mhuv2_sender_ops; |
| 1061 | + mhu->send = reg; |
| 1062 | + |
| 1063 | + mhu->windows = readl_relaxed_bitfield(&mhu->send->mhu_cfg, num_ch); |
| 1064 | + mhu->minor = readl_relaxed_bitfield(&mhu->send->aidr, arch_minor_rev); |
| 1065 | + |
| 1066 | + spin_lock_init(&mhu->doorbell_pending_lock); |
| 1067 | + |
| 1068 | + /* |
| 1069 | + * For minor version 1 and forward, tx interrupt is provided by |
| 1070 | + * the controller. |
| 1071 | + */ |
| 1072 | + if (mhu->minor && adev->irq[0]) { |
| 1073 | + ret = devm_request_threaded_irq(dev, adev->irq[0], NULL, |
| 1074 | + mhuv2_sender_interrupt, |
| 1075 | + IRQF_ONESHOT, "mhuv2-tx", mhu); |
| 1076 | + if (ret) { |
| 1077 | + dev_err(dev, "Failed to request tx IRQ, fallback to polling mode: %d\n", |
| 1078 | + ret); |
| 1079 | + } else { |
| 1080 | + mhu->mbox.txdone_irq = true; |
| 1081 | + mhu->mbox.txdone_poll = false; |
| 1082 | + mhu->irq = adev->irq[0]; |
| 1083 | + |
| 1084 | + writel_relaxed_bitfield(1, &mhu->send->int_en, chcomb); |
| 1085 | + |
| 1086 | + /* Disable all channel interrupts */ |
| 1087 | + for (i = 0; i < mhu->windows; i++) |
| 1088 | + writel_relaxed(0x0, &mhu->send->ch_wn[i].int_en); |
| 1089 | + |
| 1090 | + goto out; |
| 1091 | + } |
| 1092 | + } |
| 1093 | + |
| 1094 | + mhu->mbox.txdone_irq = false; |
| 1095 | + mhu->mbox.txdone_poll = true; |
| 1096 | + mhu->mbox.txpoll_period = 1; |
| 1097 | + |
| 1098 | +out: |
| 1099 | + /* Wait for receiver to be ready */ |
| 1100 | + writel_relaxed(0x1, &mhu->send->access_request); |
| 1101 | + while (!readl_relaxed(&mhu->send->access_ready)) |
| 1102 | + continue; |
| 1103 | + |
| 1104 | + return 0; |
| 1105 | +} |
| 1106 | + |
| 1107 | +static int mhuv2_rx_init(struct amba_device *adev, struct mhuv2 *mhu, |
| 1108 | + void __iomem *reg) |
| 1109 | +{ |
| 1110 | + struct device *dev = mhu->mbox.dev; |
| 1111 | + int ret, i; |
| 1112 | + |
| 1113 | + mhu->frame = RECEIVER_FRAME; |
| 1114 | + mhu->mbox.ops = &mhuv2_receiver_ops; |
| 1115 | + mhu->recv = reg; |
| 1116 | + |
| 1117 | + mhu->windows = readl_relaxed_bitfield(&mhu->recv->mhu_cfg, num_ch); |
| 1118 | + mhu->minor = readl_relaxed_bitfield(&mhu->recv->aidr, arch_minor_rev); |
| 1119 | + |
| 1120 | + mhu->irq = adev->irq[0]; |
| 1121 | + if (!mhu->irq) { |
| 1122 | + dev_err(dev, "Missing receiver IRQ\n"); |
| 1123 | + return -EINVAL; |
| 1124 | + } |
| 1125 | + |
| 1126 | + ret = devm_request_threaded_irq(dev, mhu->irq, NULL, |
| 1127 | + mhuv2_receiver_interrupt, IRQF_ONESHOT, |
| 1128 | + "mhuv2-rx", mhu); |
| 1129 | + if (ret) { |
| 1130 | + dev_err(dev, "Failed to request rx IRQ\n"); |
| 1131 | + return ret; |
| 1132 | + } |
| 1133 | + |
| 1134 | + /* Mask all the channel windows */ |
| 1135 | + for (i = 0; i < mhu->windows; i++) |
| 1136 | + writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_set); |
| 1137 | + |
| 1138 | + if (mhu->minor) |
| 1139 | + writel_relaxed_bitfield(1, &mhu->recv->int_en, chcomb); |
| 1140 | + |
| 1141 | + return 0; |
| 1142 | +} |
| 1143 | + |
| 1144 | +static int mhuv2_probe(struct amba_device *adev, const struct amba_id *id) |
| 1145 | +{ |
| 1146 | + struct device *dev = &adev->dev; |
| 1147 | + const struct device_node *np = dev->of_node; |
| 1148 | + struct mhuv2 *mhu; |
| 1149 | + void __iomem *reg; |
| 1150 | + int ret = -EINVAL; |
| 1151 | + |
| 1152 | + reg = devm_of_iomap(dev, dev->of_node, 0, NULL); |
| 1153 | + if (!reg) |
| 1154 | + return -ENOMEM; |
| 1155 | + |
| 1156 | + mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL); |
| 1157 | + if (!mhu) |
| 1158 | + return -ENOMEM; |
| 1159 | + |
| 1160 | + mhu->mbox.dev = dev; |
| 1161 | + mhu->mbox.of_xlate = mhuv2_mbox_of_xlate; |
| 1162 | + |
| 1163 | + if (of_device_is_compatible(np, "arm,mhuv2-tx")) |
| 1164 | + ret = mhuv2_tx_init(adev, mhu, reg); |
| 1165 | + else if (of_device_is_compatible(np, "arm,mhuv2-rx")) |
| 1166 | + ret = mhuv2_rx_init(adev, mhu, reg); |
| 1167 | + else |
| 1168 | + dev_err(dev, "Invalid compatible property\n"); |
| 1169 | + |
| 1170 | + if (ret) |
| 1171 | + return ret; |
| 1172 | + |
| 1173 | + /* Channel windows can't be 0 */ |
| 1174 | + BUG_ON(!mhu->windows); |
| 1175 | + |
| 1176 | + ret = mhuv2_parse_channels(mhu); |
| 1177 | + if (ret) |
| 1178 | + return ret; |
| 1179 | + |
| 1180 | + amba_set_drvdata(adev, mhu); |
| 1181 | + |
| 1182 | + ret = devm_mbox_controller_register(dev, &mhu->mbox); |
| 1183 | + if (ret) |
| 1184 | + dev_err(dev, "failed to register ARM MHUv2 driver %d\n", ret); |
| 1185 | + |
| 1186 | + return ret; |
| 1187 | +} |
| 1188 | + |
| 1189 | +static int mhuv2_remove(struct amba_device *adev) |
| 1190 | +{ |
| 1191 | + struct mhuv2 *mhu = amba_get_drvdata(adev); |
| 1192 | + |
| 1193 | + if (mhu->frame == SENDER_FRAME) |
| 1194 | + writel_relaxed(0x0, &mhu->send->access_request); |
| 1195 | + |
| 1196 | + return 0; |
| 1197 | +} |
| 1198 | + |
| 1199 | +static struct amba_id mhuv2_ids[] = { |
| 1200 | + { |
| 1201 | + /* 2.0 */ |
| 1202 | + .id = 0xbb0d1, |
| 1203 | + .mask = 0xfffff, |
| 1204 | + }, |
| 1205 | + { |
| 1206 | + /* 2.1 */ |
| 1207 | + .id = 0xbb076, |
| 1208 | + .mask = 0xfffff, |
| 1209 | + }, |
| 1210 | + { 0, 0 }, |
| 1211 | +}; |
| 1212 | +MODULE_DEVICE_TABLE(amba, mhuv2_ids); |
| 1213 | + |
| 1214 | +static struct amba_driver mhuv2_driver = { |
| 1215 | + .drv = { |
| 1216 | + .name = "arm-mhuv2", |
| 1217 | + }, |
| 1218 | + .id_table = mhuv2_ids, |
| 1219 | + .probe = mhuv2_probe, |
| 1220 | + .remove = mhuv2_remove, |
| 1221 | +}; |
| 1222 | +module_amba_driver(mhuv2_driver); |
| 1223 | + |
| 1224 | +MODULE_LICENSE("GPL v2"); |
| 1225 | +MODULE_DESCRIPTION("ARM MHUv2 Driver"); |
| 1226 | +MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>"); |
| 1227 | +MODULE_AUTHOR("Tushar Khandelwal <tushar.khandelwal@arm.com>"); |
| 1228 | diff --git a/include/linux/mailbox/arm_mhuv2_message.h b/include/linux/mailbox/arm_mhuv2_message.h |
| 1229 | new file mode 100644 |
| 1230 | index 000000000000..821b9d96daa4 |
| 1231 | --- /dev/null |
| 1232 | +++ b/include/linux/mailbox/arm_mhuv2_message.h |
| 1233 | @@ -0,0 +1,20 @@ |
| 1234 | +// SPDX-License-Identifier: GPL-2.0 |
| 1235 | +/* |
| 1236 | + * ARM MHUv2 Mailbox Message |
| 1237 | + * |
| 1238 | + * Copyright (C) 2020 Arm Ltd. |
| 1239 | + * Copyright (C) 2020 Linaro Ltd. |
| 1240 | + */ |
| 1241 | + |
| 1242 | +#ifndef _LINUX_ARM_MHUV2_MESSAGE_H_ |
| 1243 | +#define _LINUX_ARM_MHUV2_MESSAGE_H_ |
| 1244 | + |
| 1245 | +#include <linux/types.h> |
| 1246 | + |
| 1247 | +/* Data structure for data-transfer protocol */ |
| 1248 | +struct arm_mhuv2_mbox_msg { |
| 1249 | + void *data; |
| 1250 | + size_t len; |
| 1251 | +}; |
| 1252 | + |
| 1253 | +#endif /* _LINUX_ARM_MHUV2_MESSAGE_H_ */ |
| 1254 | -- |
| 1255 | 2.17.1 |
| 1256 | |