| Brad Bishop | 1932369 | 2019-04-05 15:28:33 -0400 | [diff] [blame] | 1 | From 8a156d1725ecd03f2e8cdc8874e081dda2d3b43d Mon Sep 17 00:00:00 2001 |
| 2 | From: Aurelien Jarno <aurelien@aurel32.net> |
| 3 | Date: Sun, 15 Apr 2018 00:49:55 +0200 |
| 4 | Subject: [PATCH] gstconfig.h.in: initial RISC-V support |
| 5 | |
| 6 | RISC-V supports unaligned accesses, but these might run extremely slowly |
| 7 | depending on the implementation. Therefore set GST_HAVE_UNALIGNED_ACCESS |
| 8 | to 0 on this architecture. |
| 9 | |
| 10 | https://bugzilla.gnome.org/show_bug.cgi?id=795271 |
| 11 | |
| 12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 13 | Upstream-Status: Accepted [1.15.1 - https://bugzilla.gnome.org/show_bug.cgi?id=795271] |
| 14 | --- |
| 15 | gst/gstconfig.h.in | 2 +- |
| 16 | 1 file changed, 1 insertion(+), 1 deletion(-) |
| 17 | |
| 18 | diff --git a/gst/gstconfig.h.in b/gst/gstconfig.h.in |
| 19 | index 6351c04da..33dfed1f6 100644 |
| 20 | --- a/gst/gstconfig.h.in |
| 21 | +++ b/gst/gstconfig.h.in |
| 22 | @@ -104,7 +104,7 @@ |
| 23 | * http://docs.oracle.com/cd/E19205-01/820-4155/c++_faq.html#Vers6 |
| 24 | * https://software.intel.com/en-us/node/583402 |
| 25 | */ |
| 26 | -#if defined(__alpha__) || defined(__arc__) || defined(__arm__) || defined(__aarch64__) || defined(__bfin) || defined(__hppa__) || defined(__nios2__) || defined(__MICROBLAZE__) || defined(__mips__) || defined(__or1k__) || defined(__sh__) || defined(__SH4__) || defined(__sparc__) || defined(__sparc) || defined(__ia64__) || defined(_M_ALPHA) || defined(_M_ARM) || defined(_M_IA64) || defined(__xtensa__) || defined(__e2k__) |
| 27 | +#if defined(__alpha__) || defined(__arc__) || defined(__arm__) || defined(__aarch64__) || defined(__bfin) || defined(__hppa__) || defined(__nios2__) || defined(__MICROBLAZE__) || defined(__mips__) || defined(__or1k__) || defined(__sh__) || defined(__SH4__) || defined(__sparc__) || defined(__sparc) || defined(__ia64__) || defined(_M_ALPHA) || defined(_M_ARM) || defined(_M_IA64) || defined(__xtensa__) || defined(__e2k__) || defined(__riscv) |
| 28 | # define GST_HAVE_UNALIGNED_ACCESS 0 |
| 29 | #elif defined(__i386__) || defined(__i386) || defined(__amd64__) || defined(__amd64) || defined(__x86_64__) || defined(__ppc__) || defined(__ppc64__) || defined(__powerpc__) || defined(__powerpc64__) || defined(__m68k__) || defined(_M_IX86) || defined(_M_AMD64) || defined(_M_X64) || defined(__s390__) || defined(__s390x__) || defined(__zarch__) |
| 30 | # define GST_HAVE_UNALIGNED_ACCESS 1 |