Brad Bishop | 1a4b7ee | 2018-12-16 17:11:34 -0800 | [diff] [blame] | 1 | From fdfad81006c2c964781b616f0a75578507be809c Mon Sep 17 00:00:00 2001 |
| 2 | From: Michael Jeanson <mjeanson@efficios.com> |
| 3 | Date: Wed, 21 Mar 2018 17:38:41 -0400 |
| 4 | Subject: [PATCH] Add support for the RISC-V architecture |
| 5 | |
| 6 | Tested in QEMU 2.12.0-rc0, requires --disable-compiler-tls to go |
| 7 | through the benchmarks reliably. |
| 8 | |
| 9 | Signed-off-by: Michael Jeanson <mjeanson@efficios.com> |
| 10 | Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
| 11 | Upstream-Status: Backport |
| 12 | --- |
| 13 | configure.ac | 1 + |
| 14 | include/Makefile.am | 2 ++ |
| 15 | include/urcu/arch/riscv.h | 49 ++++++++++++++++++++++++++++++++++++++++++++ |
| 16 | include/urcu/uatomic/riscv.h | 44 +++++++++++++++++++++++++++++++++++++++ |
| 17 | 4 files changed, 96 insertions(+) |
| 18 | create mode 100644 include/urcu/arch/riscv.h |
| 19 | create mode 100644 include/urcu/uatomic/riscv.h |
| 20 | |
| 21 | diff --git a/configure.ac b/configure.ac |
| 22 | index d0b4a9ac..9145081a 100644 |
| 23 | --- a/configure.ac |
| 24 | +++ b/configure.ac |
| 25 | @@ -151,6 +151,7 @@ AS_CASE([$host_cpu], |
| 26 | [tile*], [ARCHTYPE="tile"], |
| 27 | [hppa*], [ARCHTYPE="hppa"], |
| 28 | [m68k], [ARCHTYPE="m68k"], |
| 29 | + [riscv*], [ARCHTYPE="riscv"], |
| 30 | [ARCHTYPE="unknown"] |
| 31 | ) |
| 32 | |
| 33 | diff --git a/include/Makefile.am b/include/Makefile.am |
| 34 | index dcdf304b..36667b43 100644 |
| 35 | --- a/include/Makefile.am |
| 36 | +++ b/include/Makefile.am |
| 37 | @@ -27,6 +27,7 @@ EXTRA_DIST = urcu/arch/aarch64.h \ |
| 38 | urcu/arch/mips.h \ |
| 39 | urcu/arch/nios2.h \ |
| 40 | urcu/arch/ppc.h \ |
| 41 | + urcu/arch/riscv.h \ |
| 42 | urcu/arch/s390.h \ |
| 43 | urcu/arch/sparc64.h \ |
| 44 | urcu/arch/tile.h \ |
| 45 | @@ -43,6 +44,7 @@ EXTRA_DIST = urcu/arch/aarch64.h \ |
| 46 | urcu/uatomic/mips.h \ |
| 47 | urcu/uatomic/nios2.h \ |
| 48 | urcu/uatomic/ppc.h \ |
| 49 | + urcu/uatomic/riscv.h \ |
| 50 | urcu/uatomic/s390.h \ |
| 51 | urcu/uatomic/sparc64.h \ |
| 52 | urcu/uatomic/tile.h \ |
| 53 | diff --git a/include/urcu/arch/riscv.h b/include/urcu/arch/riscv.h |
| 54 | new file mode 100644 |
| 55 | index 00000000..1fd7d62b |
| 56 | --- /dev/null |
| 57 | +++ b/include/urcu/arch/riscv.h |
| 58 | @@ -0,0 +1,49 @@ |
| 59 | +#ifndef _URCU_ARCH_RISCV_H |
| 60 | +#define _URCU_ARCH_RISCV_H |
| 61 | + |
| 62 | +/* |
| 63 | + * arch/riscv.h: definitions for the RISC-V architecture |
| 64 | + * |
| 65 | + * Copyright (c) 2018 Michael Jeanson <mjeanson@efficios.com> |
| 66 | + * |
| 67 | + * This library is free software; you can redistribute it and/or |
| 68 | + * modify it under the terms of the GNU Lesser General Public |
| 69 | + * License as published by the Free Software Foundation; either |
| 70 | + * version 2.1 of the License, or (at your option) any later version. |
| 71 | + * |
| 72 | + * This library is distributed in the hope that it will be useful, |
| 73 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 74 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 75 | + * Lesser General Public License for more details. |
| 76 | + * |
| 77 | + * You should have received a copy of the GNU Lesser General Public |
| 78 | + * License along with this library; if not, write to the Free Software |
| 79 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
| 80 | + */ |
| 81 | + |
| 82 | +#include <urcu/compiler.h> |
| 83 | +#include <urcu/config.h> |
| 84 | +#include <urcu/syscall-compat.h> |
| 85 | + |
| 86 | +#ifdef __cplusplus |
| 87 | +extern "C" { |
| 88 | +#endif |
| 89 | + |
| 90 | +#include <stdlib.h> |
| 91 | +#include <sys/time.h> |
| 92 | + |
| 93 | +/* |
| 94 | + * On Linux, define the membarrier system call number if not yet available in |
| 95 | + * the system headers. |
| 96 | + */ |
| 97 | +#if (defined(__linux__) && !defined(__NR_membarrier)) |
| 98 | +#define __NR_membarrier 283 |
| 99 | +#endif |
| 100 | + |
| 101 | +#ifdef __cplusplus |
| 102 | +} |
| 103 | +#endif |
| 104 | + |
| 105 | +#include <urcu/arch/generic.h> |
| 106 | + |
| 107 | +#endif /* _URCU_ARCH_RISCV_H */ |
| 108 | diff --git a/include/urcu/uatomic/riscv.h b/include/urcu/uatomic/riscv.h |
| 109 | new file mode 100644 |
| 110 | index 00000000..a6700e17 |
| 111 | --- /dev/null |
| 112 | +++ b/include/urcu/uatomic/riscv.h |
| 113 | @@ -0,0 +1,44 @@ |
| 114 | +/* |
| 115 | + * Atomic exchange operations for the RISC-V architecture. Let GCC do it. |
| 116 | + * |
| 117 | + * Copyright (c) 2018 Michael Jeanson <mjeanson@efficios.com> |
| 118 | + * |
| 119 | + * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 120 | + * of this software and associated documentation files (the "Software"), to |
| 121 | + * deal in the Software without restriction, including without limitation the |
| 122 | + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 123 | + * sell copies of the Software, and to permit persons to whom the Software is |
| 124 | + * furnished to do so, subject to the following conditions: |
| 125 | + * |
| 126 | + * The above copyright notice and this permission notice shall be included in |
| 127 | + * all copies or substantial portions of the Software. |
| 128 | + * |
| 129 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 130 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 131 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 132 | + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 133 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 134 | + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 135 | + * IN THE SOFTWARE. |
| 136 | + */ |
| 137 | + |
| 138 | +#ifndef _URCU_ARCH_UATOMIC_RISCV_H |
| 139 | +#define _URCU_ARCH_UATOMIC_RISCV_H |
| 140 | + |
| 141 | +#include <urcu/compiler.h> |
| 142 | +#include <urcu/system.h> |
| 143 | + |
| 144 | +#ifdef __cplusplus |
| 145 | +extern "C" { |
| 146 | +#endif |
| 147 | + |
| 148 | +#define UATOMIC_HAS_ATOMIC_BYTE |
| 149 | +#define UATOMIC_HAS_ATOMIC_SHORT |
| 150 | + |
| 151 | +#ifdef __cplusplus |
| 152 | +} |
| 153 | +#endif |
| 154 | + |
| 155 | +#include <urcu/uatomic/generic.h> |
| 156 | + |
| 157 | +#endif /* _URCU_ARCH_UATOMIC_RISCV_H */ |