Andrew Geissler | 595f630 | 2022-01-24 19:11:47 +0000 | [diff] [blame] | 1 | From 809330ab8450261e05919b472783bf15e4b000f7 Mon Sep 17 00:00:00 2001 |
| 2 | From: Richard Earnshaw <rearnsha@arm.com> |
| 3 | Date: Tue, 6 Jul 2021 15:10:18 +0100 |
| 4 | Subject: [PATCH] arm: Add tests for VLLDM mitigation [PR102035] |
| 5 | |
| 6 | New tests for the erratum mitigation. |
| 7 | |
| 8 | gcc/testsuite: |
| 9 | PR target/102035 |
| 10 | * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13a.c: New test. |
| 11 | * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7a.c: Likewise. |
| 12 | * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8a.c: Likewise. |
| 13 | * gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7a.c: Likewise. |
| 14 | * gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8a.c: Likewise. |
| 15 | * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13a.c: Likewise. |
| 16 | * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7a.c: Likewise. |
| 17 | * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8a.c: Likewise. |
| 18 | |
| 19 | CVE: CVE-2021-35465 |
| 20 | Upstream-Status: Backport [https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=809330ab8450261e05919b472783bf15e4b000f7] |
| 21 | Signed-off-by: Pgowda <pgowda.cve@gmail.com> |
| 22 | |
| 23 | --- |
| 24 | .../arm/cmse/mainline/8_1m/soft/cmse-13a.c | 31 +++++++++++++++++++ |
| 25 | .../arm/cmse/mainline/8_1m/soft/cmse-7a.c | 28 +++++++++++++++++ |
| 26 | .../arm/cmse/mainline/8_1m/soft/cmse-8a.c | 30 ++++++++++++++++++ |
| 27 | .../cmse/mainline/8_1m/softfp-sp/cmse-7a.c | 27 ++++++++++++++++ |
| 28 | .../cmse/mainline/8_1m/softfp-sp/cmse-8a.c | 29 +++++++++++++++++ |
| 29 | .../arm/cmse/mainline/8_1m/softfp/cmse-13a.c | 30 ++++++++++++++++++ |
| 30 | .../arm/cmse/mainline/8_1m/softfp/cmse-7a.c | 27 ++++++++++++++++ |
| 31 | .../arm/cmse/mainline/8_1m/softfp/cmse-8a.c | 29 +++++++++++++++++ |
| 32 | 8 files changed, 231 insertions(+) |
| 33 | create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13a.c |
| 34 | create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7a.c |
| 35 | create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8a.c |
| 36 | create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7a.c |
| 37 | create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8a.c |
| 38 | create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13a.c |
| 39 | create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7a.c |
| 40 | create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8a.c |
| 41 | |
| 42 | diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13a.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13a.c |
| 43 | --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13a.c 1969-12-31 16:00:00.000000000 -0800 |
| 44 | +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13a.c 2021-11-15 02:30:37.210637445 -0800 |
| 45 | @@ -0,0 +1,31 @@ |
| 46 | +/* { dg-do compile } */ |
| 47 | +/* { dg-options "-mcmse -mfloat-abi=soft -mfix-cmse-cve-2021-35465" } */ |
| 48 | +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */ |
| 49 | + |
| 50 | +#include "../../../cmse-13.x" |
| 51 | + |
| 52 | +/* Checks for saving and clearing prior to function call. */ |
| 53 | +/* Shift on the same register as blxns. */ |
| 54 | +/* { dg-final { scan-assembler "lsrs\t(r\[1,4-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ |
| 55 | +/* { dg-final { scan-assembler "lsls\t(r\[1,4-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ |
| 56 | +/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */ |
| 57 | +/* { dg-final { scan-assembler-not "mov\tr2, r4" } } */ |
| 58 | +/* { dg-final { scan-assembler-not "mov\tr3, r4" } } */ |
| 59 | +/* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ |
| 60 | +/* { dg-final { scan-assembler "vlstm\tsp" } } */ |
| 61 | +/* Check the right registers are cleared and none appears twice. */ |
| 62 | +/* { dg-final { scan-assembler "clrm\t\{(r1, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, )?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */ |
| 63 | +/* Check that the right number of registers is cleared and thus only one |
| 64 | + register is missing. */ |
| 65 | +/* { dg-final { scan-assembler "clrm\t\{((r\[1,4-9\]|r10|fp|ip), ){9}APSR\}" } } */ |
| 66 | +/* Check that no cleared register is used for blxns. */ |
| 67 | +/* { dg-final { scan-assembler-not "clrm\t\{\[^\}\]\+(r\[1,4-9\]|r10|fp|ip),\[^\}\]\+\}.*blxns\t\\1" } } */ |
| 68 | +/* Check for v8.1-m variant of erratum work-around. */ |
| 69 | +/* { dg-final { scan-assembler "vscclrm\t\{vpr\}" } } */ |
| 70 | +/* { dg-final { scan-assembler "vlldm\tsp" } } */ |
| 71 | +/* { dg-final { scan-assembler "pop\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ |
| 72 | +/* { dg-final { scan-assembler-not "vmov" } } */ |
| 73 | +/* { dg-final { scan-assembler-not "vmsr" } } */ |
| 74 | + |
| 75 | +/* Now we check that we use the correct intrinsic to call. */ |
| 76 | +/* { dg-final { scan-assembler "blxns" } } */ |
| 77 | diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7a.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7a.c |
| 78 | --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7a.c 1969-12-31 16:00:00.000000000 -0800 |
| 79 | +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7a.c 2021-11-15 02:30:37.210637445 -0800 |
| 80 | @@ -0,0 +1,28 @@ |
| 81 | +/* { dg-do compile } */ |
| 82 | +/* { dg-options "-mcmse -mfloat-abi=soft -mfix-cmse-cve-2021-35465" } */ |
| 83 | +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */ |
| 84 | + |
| 85 | +#include "../../../cmse-7.x" |
| 86 | + |
| 87 | +/* Checks for saving and clearing prior to function call. */ |
| 88 | +/* Shift on the same register as blxns. */ |
| 89 | +/* { dg-final { scan-assembler "lsrs\t(r\[0-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ |
| 90 | +/* { dg-final { scan-assembler "lsls\t(r\[0-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ |
| 91 | +/* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ |
| 92 | +/* { dg-final { scan-assembler "vlstm\tsp" } } */ |
| 93 | +/* Check the right registers are cleared and none appears twice. */ |
| 94 | +/* { dg-final { scan-assembler "clrm\t\{(r0, )?(r1, )?(r2, )?(r3, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, )?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */ |
| 95 | +/* Check that the right number of registers is cleared and thus only one |
| 96 | + register is missing. */ |
| 97 | +/* { dg-final { scan-assembler "clrm\t\{((r\[0-9\]|r10|fp|ip), ){12}APSR\}" } } */ |
| 98 | +/* Check that no cleared register is used for blxns. */ |
| 99 | +/* { dg-final { scan-assembler-not "clrm\t\{\[^\}\]\+(r\[0-9\]|r10|fp|ip),\[^\}\]\+\}.*blxns\t\\1" } } */ |
| 100 | +/* Check for v8.1-m variant of erratum work-around. */ |
| 101 | +/* { dg-final { scan-assembler "vscclrm\t\{vpr\}" } } */ |
| 102 | +/* { dg-final { scan-assembler "vlldm\tsp" } } */ |
| 103 | +/* { dg-final { scan-assembler "pop\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ |
| 104 | +/* { dg-final { scan-assembler-not "vmov" } } */ |
| 105 | +/* { dg-final { scan-assembler-not "vmsr" } } */ |
| 106 | + |
| 107 | +/* Now we check that we use the correct intrinsic to call. */ |
| 108 | +/* { dg-final { scan-assembler "blxns" } } */ |
| 109 | diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8a.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8a.c |
| 110 | --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8a.c 1969-12-31 16:00:00.000000000 -0800 |
| 111 | +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8a.c 2021-11-15 02:30:37.210637445 -0800 |
| 112 | @@ -0,0 +1,30 @@ |
| 113 | +/* { dg-do compile } */ |
| 114 | +/* { dg-options "-mcmse -mfloat-abi=soft -mfix-cmse-cve-2021-35465" } */ |
| 115 | +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */ |
| 116 | + |
| 117 | +#include "../../../cmse-8.x" |
| 118 | + |
| 119 | +/* Checks for saving and clearing prior to function call. */ |
| 120 | +/* Shift on the same register as blxns. */ |
| 121 | +/* { dg-final { scan-assembler "lsrs\t(r\[2-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ |
| 122 | +/* { dg-final { scan-assembler "lsls\t(r\[2-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ |
| 123 | +/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */ |
| 124 | +/* { dg-final { scan-assembler-not "mov\tr1, r4" } } */ |
| 125 | +/* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ |
| 126 | +/* { dg-final { scan-assembler "vlstm\tsp" } } */ |
| 127 | +/* Check the right registers are cleared and none appears twice. */ |
| 128 | +/* { dg-final { scan-assembler "clrm\t\{(r2, )?(r3, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, )?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */ |
| 129 | +/* Check that the right number of registers is cleared and thus only one |
| 130 | + register is missing. */ |
| 131 | +/* { dg-final { scan-assembler "clrm\t\{((r\[2-9\]|r10|fp|ip), ){10}APSR\}" } } */ |
| 132 | +/* Check that no cleared register is used for blxns. */ |
| 133 | +/* { dg-final { scan-assembler-not "clrm\t\{\[^\}\]\+(r\[2-9\]|r10|fp|ip),\[^\}\]\+\}.*blxns\t\\1" } } */ |
| 134 | +/* Check for v8.1-m variant of erratum work-around. */ |
| 135 | +/* { dg-final { scan-assembler "vscclrm\t\{vpr\}" } } */ |
| 136 | +/* { dg-final { scan-assembler "vlldm\tsp" } } */ |
| 137 | +/* { dg-final { scan-assembler "pop\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ |
| 138 | +/* { dg-final { scan-assembler-not "vmov" } } */ |
| 139 | +/* { dg-final { scan-assembler-not "vmsr" } } */ |
| 140 | + |
| 141 | +/* Now we check that we use the correct intrinsic to call. */ |
| 142 | +/* { dg-final { scan-assembler "blxns" } } */ |
| 143 | diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13a.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13a.c |
| 144 | --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13a.c 1969-12-31 16:00:00.000000000 -0800 |
| 145 | +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13a.c 2021-11-15 02:30:37.210637445 -0800 |
| 146 | @@ -0,0 +1,30 @@ |
| 147 | +/* { dg-do compile } */ |
| 148 | +/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16 -mfix-cmse-cve-2021-35465" } */ |
| 149 | +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */ |
| 150 | +/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */ |
| 151 | + |
| 152 | +#include "../../../cmse-13.x" |
| 153 | + |
| 154 | +/* Checks for saving and clearing prior to function call. */ |
| 155 | +/* Shift on the same register as blxns. */ |
| 156 | +/* { dg-final { scan-assembler "lsrs\t(r\[1,4-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ |
| 157 | +/* { dg-final { scan-assembler "lsls\t(r\[1,4-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ |
| 158 | +/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */ |
| 159 | +/* { dg-final { scan-assembler-not "mov\tr2, r4" } } */ |
| 160 | +/* { dg-final { scan-assembler-not "mov\tr3, r4" } } */ |
| 161 | +/* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ |
| 162 | +/* { dg-final { scan-assembler "vlstm\tsp" } } */ |
| 163 | +/* Check the right registers are cleared and none appears twice. */ |
| 164 | +/* { dg-final { scan-assembler "clrm\t\{(r1, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, )?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */ |
| 165 | +/* Check that the right number of registers is cleared and thus only one |
| 166 | + register is missing. */ |
| 167 | +/* { dg-final { scan-assembler "clrm\t\{((r\[1,4-9\]|r10|fp|ip), ){9}APSR\}" } } */ |
| 168 | +/* Check that no cleared register is used for blxns. */ |
| 169 | +/* { dg-final { scan-assembler-not "clrm\t\{\[^\}\]\+(r\[1,4-9\]|r10|fp|ip),\[^\}\]\+\}.*blxns\t\\1" } } */ |
| 170 | +/* Check for v8.1-m variant of erratum work-around. */ |
| 171 | +/* { dg-final { scan-assembler "vscclrm\t\{vpr\}" } } */ |
| 172 | +/* { dg-final { scan-assembler "vlldm\tsp" } } */ |
| 173 | +/* { dg-final { scan-assembler "pop\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ |
| 174 | + |
| 175 | +/* Now we check that we use the correct intrinsic to call. */ |
| 176 | +/* { dg-final { scan-assembler "blxns" } } */ |
| 177 | diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7a.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7a.c |
| 178 | --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7a.c 1969-12-31 16:00:00.000000000 -0800 |
| 179 | +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7a.c 2021-11-15 02:30:37.210637445 -0800 |
| 180 | @@ -0,0 +1,27 @@ |
| 181 | +/* { dg-do compile } */ |
| 182 | +/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16 -mfix-cmse-cve-2021-35465" } */ |
| 183 | +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */ |
| 184 | +/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */ |
| 185 | + |
| 186 | +#include "../../../cmse-7.x" |
| 187 | + |
| 188 | +/* Checks for saving and clearing prior to function call. */ |
| 189 | +/* Shift on the same register as blxns. */ |
| 190 | +/* { dg-final { scan-assembler "lsrs\t(r\[0-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ |
| 191 | +/* { dg-final { scan-assembler "lsls\t(r\[0-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ |
| 192 | +/* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ |
| 193 | +/* { dg-final { scan-assembler "vlstm\tsp" } } */ |
| 194 | +/* Check the right registers are cleared and none appears twice. */ |
| 195 | +/* { dg-final { scan-assembler "clrm\t\{(r0, )?(r1, )?(r2, )?(r3, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, )?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */ |
| 196 | +/* Check that the right number of registers is cleared and thus only one |
| 197 | + register is missing. */ |
| 198 | +/* { dg-final { scan-assembler "clrm\t\{((r\[0-9\]|r10|fp|ip), ){12}APSR\}" } } */ |
| 199 | +/* Check that no cleared register is used for blxns. */ |
| 200 | +/* { dg-final { scan-assembler-not "clrm\t\{\[^\}\]\+(r\[0-9\]|r10|fp|ip),\[^\}\]\+\}.*blxns\t\\1" } } */ |
| 201 | +/* Check for v8.1-m variant of erratum work-around. */ |
| 202 | +/* { dg-final { scan-assembler "vscclrm\t\{vpr\}" } } */ |
| 203 | +/* { dg-final { scan-assembler "vlldm\tsp" } } */ |
| 204 | +/* { dg-final { scan-assembler "pop\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ |
| 205 | + |
| 206 | +/* Now we check that we use the correct intrinsic to call. */ |
| 207 | +/* { dg-final { scan-assembler "blxns" } } */ |
| 208 | diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8a.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8a.c |
| 209 | --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8a.c 1969-12-31 16:00:00.000000000 -0800 |
| 210 | +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8a.c 2021-11-15 02:30:37.210637445 -0800 |
| 211 | @@ -0,0 +1,29 @@ |
| 212 | +/* { dg-do compile } */ |
| 213 | +/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16 -mfix-cmse-cve-2021-35465" } */ |
| 214 | +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */ |
| 215 | +/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */ |
| 216 | + |
| 217 | +#include "../../../cmse-8.x" |
| 218 | + |
| 219 | +/* Checks for saving and clearing prior to function call. */ |
| 220 | +/* Shift on the same register as blxns. */ |
| 221 | +/* { dg-final { scan-assembler "lsrs\t(r\[2-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ |
| 222 | +/* { dg-final { scan-assembler "lsls\t(r\[2-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ |
| 223 | +/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */ |
| 224 | +/* { dg-final { scan-assembler-not "mov\tr1, r4" } } */ |
| 225 | +/* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ |
| 226 | +/* { dg-final { scan-assembler "vlstm\tsp" } } */ |
| 227 | +/* Check the right registers are cleared and none appears twice. */ |
| 228 | +/* { dg-final { scan-assembler "clrm\t\{(r2, )?(r3, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, )?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */ |
| 229 | +/* Check that the right number of registers is cleared and thus only one |
| 230 | + register is missing. */ |
| 231 | +/* { dg-final { scan-assembler "clrm\t\{((r\[2-9\]|r10|fp|ip), ){10}APSR\}" } } */ |
| 232 | +/* Check that no cleared register is used for blxns. */ |
| 233 | +/* { dg-final { scan-assembler-not "clrm\t\{\[^\}\]\+(r\[2-9\]|r10|fp|ip),\[^\}\]\+\}.*blxns\t\\1" } } */ |
| 234 | +/* Check for v8.1-m variant of erratum work-around. */ |
| 235 | +/* { dg-final { scan-assembler "vscclrm\t\{vpr\}" } } */ |
| 236 | +/* { dg-final { scan-assembler "vlldm\tsp" } } */ |
| 237 | +/* { dg-final { scan-assembler "pop\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ |
| 238 | + |
| 239 | +/* Now we check that we use the correct intrinsic to call. */ |
| 240 | +/* { dg-final { scan-assembler "blxns" } } */ |
| 241 | diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7a.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7a.c |
| 242 | --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7a.c 1969-12-31 16:00:00.000000000 -0800 |
| 243 | +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7a.c 2021-11-15 02:30:37.210637445 -0800 |
| 244 | @@ -0,0 +1,27 @@ |
| 245 | +/* { dg-do compile } */ |
| 246 | +/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16 -mfix-cmse-cve-2021-35465" } */ |
| 247 | +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */ |
| 248 | +/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */ |
| 249 | + |
| 250 | +#include "../../../cmse-7.x" |
| 251 | + |
| 252 | +/* Checks for saving and clearing prior to function call. */ |
| 253 | +/* Shift on the same register as blxns. */ |
| 254 | +/* { dg-final { scan-assembler "lsrs\t(r\[0-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ |
| 255 | +/* { dg-final { scan-assembler "lsls\t(r\[0-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ |
| 256 | +/* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ |
| 257 | +/* { dg-final { scan-assembler "vlstm\tsp" } } */ |
| 258 | +/* Check the right registers are cleared and none appears twice. */ |
| 259 | +/* { dg-final { scan-assembler "clrm\t\{(r0, )?(r1, )?(r2, )?(r3, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, )?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */ |
| 260 | +/* Check that the right number of registers is cleared and thus only one |
| 261 | + register is missing. */ |
| 262 | +/* { dg-final { scan-assembler "clrm\t\{((r\[0-9\]|r10|fp|ip), ){12}APSR\}" } } */ |
| 263 | +/* Check that no cleared register is used for blxns. */ |
| 264 | +/* { dg-final { scan-assembler-not "clrm\t\{\[^\}\]\+(r\[0-9\]|r10|fp|ip),\[^\}\]\+\}.*blxns\t\\1" } } */ |
| 265 | +/* Check for v8.1-m variant of erratum work-around. */ |
| 266 | +/* { dg-final { scan-assembler "vscclrm\t\{vpr\}" } } */ |
| 267 | +/* { dg-final { scan-assembler "vlldm\tsp" } } */ |
| 268 | +/* { dg-final { scan-assembler "pop\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ |
| 269 | + |
| 270 | +/* Now we check that we use the correct intrinsic to call. */ |
| 271 | +/* { dg-final { scan-assembler "blxns" } } */ |
| 272 | diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8a.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8a.c |
| 273 | --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8a.c 1969-12-31 16:00:00.000000000 -0800 |
| 274 | +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8a.c 2021-11-15 02:30:37.210637445 -0800 |
| 275 | @@ -0,0 +1,29 @@ |
| 276 | +/* { dg-do compile } */ |
| 277 | +/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16 -mfix-cmse-cve-2021-35465" } */ |
| 278 | +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */ |
| 279 | +/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */ |
| 280 | + |
| 281 | +#include "../../../cmse-8.x" |
| 282 | + |
| 283 | +/* Checks for saving and clearing prior to function call. */ |
| 284 | +/* Shift on the same register as blxns. */ |
| 285 | +/* { dg-final { scan-assembler "lsrs\t(r\[2-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ |
| 286 | +/* { dg-final { scan-assembler "lsls\t(r\[2-9\]|r10|fp|ip), \\1, #1.*blxns\t\\1" } } */ |
| 287 | +/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */ |
| 288 | +/* { dg-final { scan-assembler-not "mov\tr1, r4" } } */ |
| 289 | +/* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ |
| 290 | +/* { dg-final { scan-assembler "vlstm\tsp" } } */ |
| 291 | +/* Check the right registers are cleared and none appears twice. */ |
| 292 | +/* { dg-final { scan-assembler "clrm\t\{(r2, )?(r3, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, )?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */ |
| 293 | +/* Check that the right number of registers is cleared and thus only one |
| 294 | + register is missing. */ |
| 295 | +/* { dg-final { scan-assembler "clrm\t\{((r\[2-9\]|r10|fp|ip), ){10}APSR\}" } } */ |
| 296 | +/* Check that no cleared register is used for blxns. */ |
| 297 | +/* { dg-final { scan-assembler-not "clrm\t\{\[^\}\]\+(r\[2-9\]|r10|fp|ip),\[^\}\]\+\}.*blxns\t\\1" } } */ |
| 298 | +/* Check for v8.1-m variant of erratum work-around. */ |
| 299 | +/* { dg-final { scan-assembler "vscclrm\t\{vpr\}" } } */ |
| 300 | +/* { dg-final { scan-assembler "vlldm\tsp" } } */ |
| 301 | +/* { dg-final { scan-assembler "pop\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } } */ |
| 302 | + |
| 303 | +/* Now we check that we use the correct intrinsic to call. */ |
| 304 | +/* { dg-final { scan-assembler "blxns" } } */ |