blob: 293ea7d0ce8f165dae4b03d68feaddc7b5240ce8 [file] [log] [blame]
Brad Bishopbec4ebc2022-08-03 09:55:16 -04001From 7fb6d720a285b6135a9247b2adde833ea90e2549 Mon Sep 17 00:00:00 2001
2From: Usama Arif <usama.arif@arm.com>
3Date: Mon, 27 Sep 2021 19:58:56 +0100
4Subject: [PATCH] plat-totalcompute: add support for higher DRAM
5
6The new 6GB DRAM bank starts at 0x8080000000.
7
8Signed-off-by: Usama Arif <usama.arif@arm.com>
9Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
10
11Upstream-Status: Backport [https://github.com/OP-TEE/optee_os/commit/6d8430f943e091282849b188fbc0847c159e5de4]
12Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
13---
14 core/arch/arm/plat-totalcompute/conf.mk | 2 ++
15 core/arch/arm/plat-totalcompute/main.c | 1 +
16 core/arch/arm/plat-totalcompute/platform_config.h | 3 +++
17 3 files changed, 6 insertions(+)
18
19diff --git a/core/arch/arm/plat-totalcompute/conf.mk b/core/arch/arm/plat-totalcompute/conf.mk
20index 558b7889..e894b1e1 100644
21--- a/core/arch/arm/plat-totalcompute/conf.mk
22+++ b/core/arch/arm/plat-totalcompute/conf.mk
23@@ -24,6 +24,8 @@ platform-cflags-debug-info = -gdwarf-2
24 platform-aflags-debug-info = -gdwarf-2
25 endif
26
27+$(call force,CFG_CORE_ARM64_PA_BITS,40)
28+
29 ifneq (,$(filter ${PLATFORM_FLAVOR},tc0 tc1))
30 CFG_TEE_CORE_NB_CORE = 8
31
32diff --git a/core/arch/arm/plat-totalcompute/main.c b/core/arch/arm/plat-totalcompute/main.c
33index 42acf8dd..eab237bf 100644
34--- a/core/arch/arm/plat-totalcompute/main.c
35+++ b/core/arch/arm/plat-totalcompute/main.c
36@@ -27,6 +27,7 @@ register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
37 #endif
38
39 register_ddr(DRAM0_BASE, DRAM0_SIZE);
40+register_ddr(DRAM1_BASE, DRAM1_SIZE);
41
42 #ifndef CFG_CORE_SEL2_SPMC
43 void main_init_gic(void)
44diff --git a/core/arch/arm/plat-totalcompute/platform_config.h b/core/arch/arm/plat-totalcompute/platform_config.h
45index 4255abca..b474a899 100644
46--- a/core/arch/arm/plat-totalcompute/platform_config.h
47+++ b/core/arch/arm/plat-totalcompute/platform_config.h
48@@ -26,6 +26,9 @@
49 #define DRAM0_BASE 0x80000000
50 #define DRAM0_SIZE 0x7d000000
51
52+#define DRAM1_BASE 0x8080000000ULL
53+#define DRAM1_SIZE 0x180000000ULL
54+
55 #define TZCDRAM_BASE 0xff000000
56 #define TZCDRAM_SIZE 0x01000000
57
58--
592.30.2
60