Andrew Geissler | ea144b03 | 2023-01-27 16:03:57 -0600 | [diff] [blame^] | 1 | From 584e4952dca726c3dc9df319dffb37a518b65c14 Mon Sep 17 00:00:00 2001 |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame] | 2 | From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> |
| 3 | Date: Fri, 29 Jul 2022 13:06:19 +0100 |
Andrew Geissler | ea144b03 | 2023-01-27 16:03:57 -0600 | [diff] [blame^] | 4 | Subject: [PATCH 01/25] arm64: smccc: add support for SMCCCv1.2 x0-x17 |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame] | 5 | registers |
| 6 | |
| 7 | add support for x0-x17 registers used by the SMC calls |
| 8 | |
| 9 | In SMCCC v1.2 [1] arguments are passed in registers x1-x17. |
| 10 | Results are returned in x0-x17. |
| 11 | |
| 12 | This work is inspired from the following kernel commit: |
| 13 | |
| 14 | arm64: smccc: Add support for SMCCCv1.2 extended input/output registers |
| 15 | |
| 16 | [1]: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6?token= |
| 17 | |
| 18 | Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> |
Andrew Geissler | ea144b03 | 2023-01-27 16:03:57 -0600 | [diff] [blame^] | 19 | Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> |
| 20 | Cc: Tom Rini <trini@konsulko.com> |
| 21 | Cc: Simon Glass <sjg@chromium.org> |
| 22 | Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org> |
| 23 | Upstream-Status: Submitted [cover letter: https://lore.kernel.org/all/20221122131751.22747-1-abdellatif.elkhlifi@arm.com/] |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame] | 24 | |
| 25 | Changelog: |
| 26 | =============== |
| 27 | |
Andrew Geissler | ea144b03 | 2023-01-27 16:03:57 -0600 | [diff] [blame^] | 28 | v7: |
| 29 | |
| 30 | * improve indentation of ARM_SMCCC_1_2_REGS_Xn_OFFS |
| 31 | |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame] | 32 | v4: |
| 33 | |
| 34 | * rename the commit title and improve description |
| 35 | new commit title: the current |
| 36 | |
| 37 | v3: |
| 38 | |
| 39 | * port x0-x17 registers support from linux kernel as defined by SMCCCv1.2 |
| 40 | commit title: |
| 41 | arm64: smccc: add Xn registers support used by SMC calls |
Andrew Geissler | ea144b03 | 2023-01-27 16:03:57 -0600 | [diff] [blame^] | 42 | --- |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame] | 43 | arch/arm/cpu/armv8/smccc-call.S | 53 +++++++++++++++++++++++++++++++++ |
Andrew Geissler | ea144b03 | 2023-01-27 16:03:57 -0600 | [diff] [blame^] | 44 | arch/arm/lib/asm-offsets.c | 14 +++++++++ |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame] | 45 | include/linux/arm-smccc.h | 43 ++++++++++++++++++++++++++ |
Andrew Geissler | ea144b03 | 2023-01-27 16:03:57 -0600 | [diff] [blame^] | 46 | 3 files changed, 110 insertions(+) |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame] | 47 | |
| 48 | diff --git a/arch/arm/cpu/armv8/smccc-call.S b/arch/arm/cpu/armv8/smccc-call.S |
| 49 | index dc92b28777..ec6f299bc9 100644 |
| 50 | --- a/arch/arm/cpu/armv8/smccc-call.S |
| 51 | +++ b/arch/arm/cpu/armv8/smccc-call.S |
| 52 | @@ -1,6 +1,8 @@ |
| 53 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 54 | /* |
| 55 | * Copyright (c) 2015, Linaro Limited |
| 56 | + * (C) Copyright 2022 ARM Limited |
| 57 | + * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> |
| 58 | */ |
| 59 | #include <linux/linkage.h> |
| 60 | #include <linux/arm-smccc.h> |
| 61 | @@ -45,3 +47,54 @@ ENDPROC(__arm_smccc_smc) |
| 62 | ENTRY(__arm_smccc_hvc) |
| 63 | SMCCC hvc |
| 64 | ENDPROC(__arm_smccc_hvc) |
| 65 | + |
| 66 | +#ifdef CONFIG_ARM64 |
| 67 | + |
| 68 | + .macro SMCCC_1_2 instr |
| 69 | + /* Save `res` and free a GPR that won't be clobbered */ |
| 70 | + stp x1, x19, [sp, #-16]! |
| 71 | + |
| 72 | + /* Ensure `args` won't be clobbered while loading regs in next step */ |
| 73 | + mov x19, x0 |
| 74 | + |
| 75 | + /* Load the registers x0 - x17 from the struct arm_smccc_1_2_regs */ |
| 76 | + ldp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS] |
| 77 | + ldp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS] |
| 78 | + ldp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS] |
| 79 | + ldp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS] |
| 80 | + ldp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS] |
| 81 | + ldp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS] |
| 82 | + ldp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS] |
| 83 | + ldp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS] |
| 84 | + ldp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS] |
| 85 | + |
| 86 | + \instr #0 |
| 87 | + |
| 88 | + /* Load the `res` from the stack */ |
| 89 | + ldr x19, [sp] |
| 90 | + |
| 91 | + /* Store the registers x0 - x17 into the result structure */ |
| 92 | + stp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS] |
| 93 | + stp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS] |
| 94 | + stp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS] |
| 95 | + stp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS] |
| 96 | + stp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS] |
| 97 | + stp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS] |
| 98 | + stp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS] |
| 99 | + stp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS] |
| 100 | + stp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS] |
| 101 | + |
| 102 | + /* Restore original x19 */ |
| 103 | + ldp xzr, x19, [sp], #16 |
| 104 | + ret |
| 105 | + .endm |
| 106 | + |
| 107 | +/* |
| 108 | + * void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args, |
| 109 | + * struct arm_smccc_1_2_regs *res); |
| 110 | + */ |
| 111 | +ENTRY(arm_smccc_1_2_smc) |
| 112 | + SMCCC_1_2 smc |
| 113 | +ENDPROC(arm_smccc_1_2_smc) |
| 114 | + |
| 115 | +#endif |
| 116 | diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c |
Andrew Geissler | ea144b03 | 2023-01-27 16:03:57 -0600 | [diff] [blame^] | 117 | index 22fd541f9a..db6d7ed234 100644 |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame] | 118 | --- a/arch/arm/lib/asm-offsets.c |
| 119 | +++ b/arch/arm/lib/asm-offsets.c |
Andrew Geissler | ea144b03 | 2023-01-27 16:03:57 -0600 | [diff] [blame^] | 120 | @@ -9,6 +9,9 @@ |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame] | 121 | * generate asm statements containing #defines, |
| 122 | * compile this file to assembler, and then extract the |
| 123 | * #defines from the assembly-language output. |
| 124 | + * |
| 125 | + * (C) Copyright 2022 ARM Limited |
Andrew Geissler | ea144b03 | 2023-01-27 16:03:57 -0600 | [diff] [blame^] | 126 | + * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame] | 127 | */ |
| 128 | |
| 129 | #include <common.h> |
Andrew Geissler | ea144b03 | 2023-01-27 16:03:57 -0600 | [diff] [blame^] | 130 | @@ -117,6 +120,17 @@ int main(void) |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame] | 131 | DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2)); |
| 132 | DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id)); |
| 133 | DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state)); |
Andrew Geissler | ea144b03 | 2023-01-27 16:03:57 -0600 | [diff] [blame^] | 134 | +#ifdef CONFIG_ARM64 |
| 135 | + DEFINE(ARM_SMCCC_1_2_REGS_X0_OFFS, offsetof(struct arm_smccc_1_2_regs, a0)); |
| 136 | + DEFINE(ARM_SMCCC_1_2_REGS_X2_OFFS, offsetof(struct arm_smccc_1_2_regs, a2)); |
| 137 | + DEFINE(ARM_SMCCC_1_2_REGS_X4_OFFS, offsetof(struct arm_smccc_1_2_regs, a4)); |
| 138 | + DEFINE(ARM_SMCCC_1_2_REGS_X6_OFFS, offsetof(struct arm_smccc_1_2_regs, a6)); |
| 139 | + DEFINE(ARM_SMCCC_1_2_REGS_X8_OFFS, offsetof(struct arm_smccc_1_2_regs, a8)); |
| 140 | + DEFINE(ARM_SMCCC_1_2_REGS_X10_OFFS, offsetof(struct arm_smccc_1_2_regs, a10)); |
| 141 | + DEFINE(ARM_SMCCC_1_2_REGS_X12_OFFS, offsetof(struct arm_smccc_1_2_regs, a12)); |
| 142 | + DEFINE(ARM_SMCCC_1_2_REGS_X14_OFFS, offsetof(struct arm_smccc_1_2_regs, a14)); |
| 143 | + DEFINE(ARM_SMCCC_1_2_REGS_X16_OFFS, offsetof(struct arm_smccc_1_2_regs, a16)); |
| 144 | +#endif |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame] | 145 | #endif |
| 146 | |
| 147 | return 0; |
| 148 | diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h |
Andrew Geissler | ea144b03 | 2023-01-27 16:03:57 -0600 | [diff] [blame^] | 149 | index e1d09884a1..9105031d55 100644 |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame] | 150 | --- a/include/linux/arm-smccc.h |
| 151 | +++ b/include/linux/arm-smccc.h |
| 152 | @@ -1,6 +1,8 @@ |
| 153 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 154 | /* |
| 155 | * Copyright (c) 2015, Linaro Limited |
| 156 | + * (C) Copyright 2022 ARM Limited |
| 157 | + * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> |
| 158 | */ |
| 159 | #ifndef __LINUX_ARM_SMCCC_H |
| 160 | #define __LINUX_ARM_SMCCC_H |
Andrew Geissler | ea144b03 | 2023-01-27 16:03:57 -0600 | [diff] [blame^] | 161 | @@ -70,6 +72,47 @@ struct arm_smccc_res { |
Patrick Williams | 8dd6848 | 2022-10-04 07:57:18 -0500 | [diff] [blame] | 162 | unsigned long a3; |
| 163 | }; |
| 164 | |
| 165 | +#ifdef CONFIG_ARM64 |
| 166 | +/** |
| 167 | + * struct arm_smccc_1_2_regs - Arguments for or Results from SMC call |
| 168 | + * @a0-a17 argument values from registers 0 to 17 |
| 169 | + */ |
| 170 | +struct arm_smccc_1_2_regs { |
| 171 | + unsigned long a0; |
| 172 | + unsigned long a1; |
| 173 | + unsigned long a2; |
| 174 | + unsigned long a3; |
| 175 | + unsigned long a4; |
| 176 | + unsigned long a5; |
| 177 | + unsigned long a6; |
| 178 | + unsigned long a7; |
| 179 | + unsigned long a8; |
| 180 | + unsigned long a9; |
| 181 | + unsigned long a10; |
| 182 | + unsigned long a11; |
| 183 | + unsigned long a12; |
| 184 | + unsigned long a13; |
| 185 | + unsigned long a14; |
| 186 | + unsigned long a15; |
| 187 | + unsigned long a16; |
| 188 | + unsigned long a17; |
| 189 | +}; |
| 190 | + |
| 191 | +/** |
| 192 | + * arm_smccc_1_2_smc() - make SMC calls |
| 193 | + * @args: arguments passed via struct arm_smccc_1_2_regs |
| 194 | + * @res: result values via struct arm_smccc_1_2_regs |
| 195 | + * |
| 196 | + * This function is used to make SMC calls following SMC Calling Convention |
| 197 | + * v1.2 or above. The content of the supplied param are copied from the |
| 198 | + * structure to registers prior to the SMC instruction. The return values |
| 199 | + * are updated with the content from registers on return from the SMC |
| 200 | + * instruction. |
| 201 | + */ |
| 202 | +asmlinkage void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args, |
| 203 | + struct arm_smccc_1_2_regs *res); |
| 204 | +#endif |
| 205 | + |
| 206 | /** |
| 207 | * struct arm_smccc_quirk - Contains quirk information |
| 208 | * @id: quirk identification |
| 209 | -- |
| 210 | 2.17.1 |
| 211 | |