| Andrew Geissler | ea144b03 | 2023-01-27 16:03:57 -0600 | [diff] [blame^] | 1 | From 59fb813f9742b349f48250bd7793279cafe2752c Mon Sep 17 00:00:00 2001 |
| 2 | From: Pierre Gondois <pierre.gondois@arm.com> |
| 3 | Date: Mon, 7 Nov 2022 16:56:58 +0100 |
| 4 | Subject: [PATCH] arm64: dts: Update cache properties for Arm Ltd platforms |
| 5 | |
| 6 | The DeviceTree Specification v0.3 specifies that the cache node |
| 7 | "compatible" and "cache-level" properties are required. |
| 8 | |
| 9 | Cf. s3.8 Multi-level and Shared Cache Nodes |
| 10 | The 'cache-unified' property should be present if one of the properties |
| 11 | for unified cache is present ('cache-size', ...). |
| 12 | |
| 13 | Update the relevant device trees nodes accordingly. |
| 14 | |
| 15 | Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> |
| 16 | Link: https://lore.kernel.org/r/20221107155825.1644604-6-pierre.gondois@arm.com |
| 17 | Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> |
| 18 | |
| 19 | Signed-off-by: Jon Mason <jon.mason@arm.com> |
| 20 | Upstream-Status: Backport |
| 21 | --- |
| 22 | arch/arm64/boot/dts/arm/corstone1000.dtsi | 1 + |
| 23 | arch/arm64/boot/dts/arm/foundation-v8.dtsi | 1 + |
| 24 | arch/arm64/boot/dts/arm/juno-r1.dts | 2 ++ |
| 25 | arch/arm64/boot/dts/arm/juno-r2.dts | 2 ++ |
| 26 | arch/arm64/boot/dts/arm/juno.dts | 2 ++ |
| 27 | arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 1 + |
| 28 | arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 1 + |
| 29 | 7 files changed, 10 insertions(+) |
| 30 | |
| 31 | diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi |
| 32 | index 4e46826f883a..21f1f952e985 100644 |
| 33 | --- a/arch/arm64/boot/dts/arm/corstone1000.dtsi |
| 34 | +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi |
| 35 | @@ -53,6 +53,7 @@ gic: interrupt-controller@1c000000 { |
| 36 | |
| 37 | L2_0: l2-cache0 { |
| 38 | compatible = "cache"; |
| 39 | + cache-unified; |
| 40 | cache-level = <2>; |
| 41 | cache-size = <0x80000>; |
| 42 | cache-line-size = <64>; |
| 43 | diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi |
| 44 | index 83e3e7e3984f..c8bd23b1a7ba 100644 |
| 45 | --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi |
| 46 | +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi |
| 47 | @@ -58,6 +58,7 @@ cpu3: cpu@3 { |
| 48 | |
| 49 | L2_0: l2-cache0 { |
| 50 | compatible = "cache"; |
| 51 | + cache-level = <2>; |
| 52 | }; |
| 53 | }; |
| 54 | |
| 55 | diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts |
| 56 | index 6451c62146fd..1d90eeebb37d 100644 |
| 57 | --- a/arch/arm64/boot/dts/arm/juno-r1.dts |
| 58 | +++ b/arch/arm64/boot/dts/arm/juno-r1.dts |
| 59 | @@ -189,6 +189,7 @@ A53_3: cpu@103 { |
| 60 | |
| 61 | A57_L2: l2-cache0 { |
| 62 | compatible = "cache"; |
| 63 | + cache-unified; |
| 64 | cache-size = <0x200000>; |
| 65 | cache-line-size = <64>; |
| 66 | cache-sets = <2048>; |
| 67 | @@ -197,6 +198,7 @@ A57_L2: l2-cache0 { |
| 68 | |
| 69 | A53_L2: l2-cache1 { |
| 70 | compatible = "cache"; |
| 71 | + cache-unified; |
| 72 | cache-size = <0x100000>; |
| 73 | cache-line-size = <64>; |
| 74 | cache-sets = <1024>; |
| 75 | diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts |
| 76 | index 438cd1ff4bd0..d2ada69b0a43 100644 |
| 77 | --- a/arch/arm64/boot/dts/arm/juno-r2.dts |
| 78 | +++ b/arch/arm64/boot/dts/arm/juno-r2.dts |
| 79 | @@ -195,6 +195,7 @@ A53_3: cpu@103 { |
| 80 | |
| 81 | A72_L2: l2-cache0 { |
| 82 | compatible = "cache"; |
| 83 | + cache-unified; |
| 84 | cache-size = <0x200000>; |
| 85 | cache-line-size = <64>; |
| 86 | cache-sets = <2048>; |
| 87 | @@ -203,6 +204,7 @@ A72_L2: l2-cache0 { |
| 88 | |
| 89 | A53_L2: l2-cache1 { |
| 90 | compatible = "cache"; |
| 91 | + cache-unified; |
| 92 | cache-size = <0x100000>; |
| 93 | cache-line-size = <64>; |
| 94 | cache-sets = <1024>; |
| 95 | diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts |
| 96 | index cf4a58211399..5e48a01a5b9f 100644 |
| 97 | --- a/arch/arm64/boot/dts/arm/juno.dts |
| 98 | +++ b/arch/arm64/boot/dts/arm/juno.dts |
| 99 | @@ -194,6 +194,7 @@ A53_3: cpu@103 { |
| 100 | |
| 101 | A57_L2: l2-cache0 { |
| 102 | compatible = "cache"; |
| 103 | + cache-unified; |
| 104 | cache-size = <0x200000>; |
| 105 | cache-line-size = <64>; |
| 106 | cache-sets = <2048>; |
| 107 | @@ -202,6 +203,7 @@ A57_L2: l2-cache0 { |
| 108 | |
| 109 | A53_L2: l2-cache1 { |
| 110 | compatible = "cache"; |
| 111 | + cache-unified; |
| 112 | cache-size = <0x100000>; |
| 113 | cache-line-size = <64>; |
| 114 | cache-sets = <1024>; |
| 115 | diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts |
| 116 | index 258991ad7cc0..ef68f5aae7dd 100644 |
| 117 | --- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts |
| 118 | +++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts |
| 119 | @@ -71,6 +71,7 @@ cpu@3 { |
| 120 | |
| 121 | L2_0: l2-cache0 { |
| 122 | compatible = "cache"; |
| 123 | + cache-level = <2>; |
| 124 | }; |
| 125 | }; |
| 126 | |
| 127 | diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts |
| 128 | index 5b6d9d8e934d..796cd7d02eb5 100644 |
| 129 | --- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts |
| 130 | +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts |
| 131 | @@ -57,6 +57,7 @@ cpu@1 { |
| 132 | |
| 133 | L2_0: l2-cache0 { |
| 134 | compatible = "cache"; |
| 135 | + cache-level = <2>; |
| 136 | }; |
| 137 | }; |
| 138 | |
| 139 | -- |
| 140 | 2.30.2 |
| 141 | |