| Andrew Geissler | ea144b03 | 2023-01-27 16:03:57 -0600 | [diff] [blame^] | 1 | From b2d5025e129289d9b914c696646e64495a7453c0 Mon Sep 17 00:00:00 2001 |
| 2 | From: Sudeep Holla <sudeep.holla@arm.com> |
| 3 | Date: Fri, 18 Nov 2022 15:10:17 +0000 |
| 4 | Subject: [PATCH] arm64: dts: fvp: Add information about L1 and L2 caches |
| 5 | |
| 6 | Add the information about L1 and L2 caches on FVP RevC platform. |
| 7 | Though the cache size is configurable through the model parameters, |
| 8 | having default values in the device tree helps to exercise and debug |
| 9 | any code utilising the cache information without the need of real |
| 10 | hardware. |
| 11 | |
| 12 | Link: https://lore.kernel.org/r/20221118151017.704716-1-sudeep.holla@arm.com |
| 13 | Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> |
| 14 | |
| 15 | Signed-off-by: Jon Mason <jon.mason@arm.com> |
| 16 | Upstream-Status: Backport |
| 17 | --- |
| 18 | arch/arm64/boot/dts/arm/fvp-base-revc.dts | 73 +++++++++++++++++++++++ |
| 19 | 1 file changed, 73 insertions(+) |
| 20 | |
| 21 | diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts |
| 22 | index 5f6f30c801a7..60472d65a355 100644 |
| 23 | --- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts |
| 24 | +++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts |
| 25 | @@ -47,48 +47,121 @@ cpu0: cpu@0 { |
| 26 | compatible = "arm,armv8"; |
| 27 | reg = <0x0 0x000>; |
| 28 | enable-method = "psci"; |
| 29 | + i-cache-size = <0x8000>; |
| 30 | + i-cache-line-size = <64>; |
| 31 | + i-cache-sets = <256>; |
| 32 | + d-cache-size = <0x8000>; |
| 33 | + d-cache-line-size = <64>; |
| 34 | + d-cache-sets = <256>; |
| 35 | + next-level-cache = <&C0_L2>; |
| 36 | }; |
| 37 | cpu1: cpu@100 { |
| 38 | device_type = "cpu"; |
| 39 | compatible = "arm,armv8"; |
| 40 | reg = <0x0 0x100>; |
| 41 | enable-method = "psci"; |
| 42 | + i-cache-size = <0x8000>; |
| 43 | + i-cache-line-size = <64>; |
| 44 | + i-cache-sets = <256>; |
| 45 | + d-cache-size = <0x8000>; |
| 46 | + d-cache-line-size = <64>; |
| 47 | + d-cache-sets = <256>; |
| 48 | + next-level-cache = <&C0_L2>; |
| 49 | }; |
| 50 | cpu2: cpu@200 { |
| 51 | device_type = "cpu"; |
| 52 | compatible = "arm,armv8"; |
| 53 | reg = <0x0 0x200>; |
| 54 | enable-method = "psci"; |
| 55 | + i-cache-size = <0x8000>; |
| 56 | + i-cache-line-size = <64>; |
| 57 | + i-cache-sets = <256>; |
| 58 | + d-cache-size = <0x8000>; |
| 59 | + d-cache-line-size = <64>; |
| 60 | + d-cache-sets = <256>; |
| 61 | + next-level-cache = <&C0_L2>; |
| 62 | }; |
| 63 | cpu3: cpu@300 { |
| 64 | device_type = "cpu"; |
| 65 | compatible = "arm,armv8"; |
| 66 | reg = <0x0 0x300>; |
| 67 | enable-method = "psci"; |
| 68 | + i-cache-size = <0x8000>; |
| 69 | + i-cache-line-size = <64>; |
| 70 | + i-cache-sets = <256>; |
| 71 | + d-cache-size = <0x8000>; |
| 72 | + d-cache-line-size = <64>; |
| 73 | + d-cache-sets = <256>; |
| 74 | + next-level-cache = <&C0_L2>; |
| 75 | }; |
| 76 | cpu4: cpu@10000 { |
| 77 | device_type = "cpu"; |
| 78 | compatible = "arm,armv8"; |
| 79 | reg = <0x0 0x10000>; |
| 80 | enable-method = "psci"; |
| 81 | + i-cache-size = <0x8000>; |
| 82 | + i-cache-line-size = <64>; |
| 83 | + i-cache-sets = <256>; |
| 84 | + d-cache-size = <0x8000>; |
| 85 | + d-cache-line-size = <64>; |
| 86 | + d-cache-sets = <256>; |
| 87 | + next-level-cache = <&C1_L2>; |
| 88 | }; |
| 89 | cpu5: cpu@10100 { |
| 90 | device_type = "cpu"; |
| 91 | compatible = "arm,armv8"; |
| 92 | reg = <0x0 0x10100>; |
| 93 | enable-method = "psci"; |
| 94 | + i-cache-size = <0x8000>; |
| 95 | + i-cache-line-size = <64>; |
| 96 | + i-cache-sets = <256>; |
| 97 | + d-cache-size = <0x8000>; |
| 98 | + d-cache-line-size = <64>; |
| 99 | + d-cache-sets = <256>; |
| 100 | + next-level-cache = <&C1_L2>; |
| 101 | }; |
| 102 | cpu6: cpu@10200 { |
| 103 | device_type = "cpu"; |
| 104 | compatible = "arm,armv8"; |
| 105 | reg = <0x0 0x10200>; |
| 106 | enable-method = "psci"; |
| 107 | + i-cache-size = <0x8000>; |
| 108 | + i-cache-line-size = <64>; |
| 109 | + i-cache-sets = <256>; |
| 110 | + d-cache-size = <0x8000>; |
| 111 | + d-cache-line-size = <64>; |
| 112 | + d-cache-sets = <256>; |
| 113 | + next-level-cache = <&C1_L2>; |
| 114 | }; |
| 115 | cpu7: cpu@10300 { |
| 116 | device_type = "cpu"; |
| 117 | compatible = "arm,armv8"; |
| 118 | reg = <0x0 0x10300>; |
| 119 | enable-method = "psci"; |
| 120 | + i-cache-size = <0x8000>; |
| 121 | + i-cache-line-size = <64>; |
| 122 | + i-cache-sets = <256>; |
| 123 | + d-cache-size = <0x8000>; |
| 124 | + d-cache-line-size = <64>; |
| 125 | + d-cache-sets = <256>; |
| 126 | + next-level-cache = <&C1_L2>; |
| 127 | + }; |
| 128 | + C0_L2: l2-cache0 { |
| 129 | + compatible = "cache"; |
| 130 | + cache-size = <0x80000>; |
| 131 | + cache-line-size = <64>; |
| 132 | + cache-sets = <512>; |
| 133 | + cache-level = <2>; |
| 134 | + cache-unified; |
| 135 | + }; |
| 136 | + |
| 137 | + C1_L2: l2-cache1 { |
| 138 | + compatible = "cache"; |
| 139 | + cache-size = <0x80000>; |
| 140 | + cache-line-size = <64>; |
| 141 | + cache-sets = <512>; |
| 142 | + cache-level = <2>; |
| 143 | + cache-unified; |
| 144 | }; |
| 145 | }; |
| 146 | |
| 147 | -- |
| 148 | 2.30.2 |
| 149 | |