Andrew Geissler | a9ff2b3 | 2020-10-16 10:11:54 -0500 | [diff] [blame] | 1 | From fa85df88dc229f7f8f0bc09cd0995d05f49c03b7 Mon Sep 17 00:00:00 2001 |
Brad Bishop | 26bdd44 | 2019-08-16 17:08:17 -0400 | [diff] [blame] | 2 | From: Nagaraju Mekala <nmekala@xilix.com> |
| 3 | Date: Mon, 18 Jan 2016 12:28:21 +0530 |
Andrew Geissler | a9ff2b3 | 2020-10-16 10:11:54 -0500 | [diff] [blame] | 4 | Subject: [PATCH 09/40] Added Address extension instructions |
Brad Bishop | 286d45c | 2018-10-02 15:21:57 -0400 | [diff] [blame] | 5 | |
| 6 | This patch adds the support of new instructions which are required |
| 7 | for supporting Address extension feature. |
| 8 | |
Brad Bishop | 26bdd44 | 2019-08-16 17:08:17 -0400 | [diff] [blame] | 9 | Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> |
Brad Bishop | 286d45c | 2018-10-02 15:21:57 -0400 | [diff] [blame] | 10 | |
Brad Bishop | 26bdd44 | 2019-08-16 17:08:17 -0400 | [diff] [blame] | 11 | ChangeLog: |
| 12 | 2016-01-18 Nagaraju Mekala <nmekala@xilix.com> |
Brad Bishop | 286d45c | 2018-10-02 15:21:57 -0400 | [diff] [blame] | 13 | |
Brad Bishop | 26bdd44 | 2019-08-16 17:08:17 -0400 | [diff] [blame] | 14 | *microblaze-opc.h (op_code_struct): Update |
| 15 | Added new instructions |
Andrew Geissler | a9ff2b3 | 2020-10-16 10:11:54 -0500 | [diff] [blame] | 16 | Set MAX_OPCODES to matching value |
Brad Bishop | 26bdd44 | 2019-08-16 17:08:17 -0400 | [diff] [blame] | 17 | *microblaze-opcm.h (microblaze_instr): Update |
| 18 | Added new instructions |
Brad Bishop | 286d45c | 2018-10-02 15:21:57 -0400 | [diff] [blame] | 19 | --- |
Andrew Geissler | a9ff2b3 | 2020-10-16 10:11:54 -0500 | [diff] [blame] | 20 | opcodes/microblaze-opc.h | 13 ++++++++++++- |
Brad Bishop | 286d45c | 2018-10-02 15:21:57 -0400 | [diff] [blame] | 21 | opcodes/microblaze-opcm.h | 10 +++++----- |
Andrew Geissler | a9ff2b3 | 2020-10-16 10:11:54 -0500 | [diff] [blame] | 22 | 2 files changed, 17 insertions(+), 6 deletions(-) |
Brad Bishop | 286d45c | 2018-10-02 15:21:57 -0400 | [diff] [blame] | 23 | |
| 24 | diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h |
Andrew Geissler | a9ff2b3 | 2020-10-16 10:11:54 -0500 | [diff] [blame] | 25 | index b6c5016e4d2..c7a506b845a 100644 |
Brad Bishop | 286d45c | 2018-10-02 15:21:57 -0400 | [diff] [blame] | 26 | --- a/opcodes/microblaze-opc.h |
| 27 | +++ b/opcodes/microblaze-opc.h |
Andrew Geissler | a9ff2b3 | 2020-10-16 10:11:54 -0500 | [diff] [blame] | 28 | @@ -102,7 +102,7 @@ |
| 29 | #define DELAY_SLOT 1 |
| 30 | #define NO_DELAY_SLOT 0 |
| 31 | |
| 32 | -#define MAX_OPCODES 291 |
| 33 | +#define MAX_OPCODES 299 |
| 34 | |
| 35 | struct op_code_struct |
| 36 | { |
Brad Bishop | 286d45c | 2018-10-02 15:21:57 -0400 | [diff] [blame] | 37 | @@ -178,8 +178,11 @@ struct op_code_struct |
| 38 | {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst }, |
| 39 | {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst }, |
| 40 | {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst }, |
| 41 | + {"wdc.clear.ea", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E6, OPCODE_MASK_H34B, wdcclearea, special_inst }, |
| 42 | {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst }, |
| 43 | + {"mtse", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9500C000, OPCODE_MASK_H13S, mtse,special_inst }, |
| 44 | {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst }, |
| 45 | + {"mfse", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94088000, OPCODE_MASK_H23S, mfse, special_inst }, |
| 46 | {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst }, |
| 47 | {"brd", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst }, |
| 48 | {"brld", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst }, |
| 49 | @@ -229,18 +232,24 @@ struct op_code_struct |
| 50 | {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst }, |
| 51 | {"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst }, |
| 52 | {"lbur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst }, |
| 53 | + {"lbuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000080, OPCODE_MASK_H4, lbuea, memory_load_inst }, |
| 54 | {"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst }, |
| 55 | {"lhur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst }, |
| 56 | + {"lhuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000080, OPCODE_MASK_H4, lhuea, memory_load_inst }, |
| 57 | {"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst }, |
| 58 | {"lwr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst }, |
| 59 | {"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst }, |
| 60 | + {"lwea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000080, OPCODE_MASK_H4, lwea, memory_load_inst }, |
| 61 | {"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst }, |
| 62 | {"sbr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst }, |
| 63 | + {"sbea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000080, OPCODE_MASK_H4, sbea, memory_store_inst }, |
| 64 | {"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst }, |
| 65 | {"shr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst }, |
| 66 | + {"shea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000080, OPCODE_MASK_H4, shea, memory_store_inst }, |
| 67 | {"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst }, |
| 68 | {"swr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst }, |
| 69 | {"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst }, |
| 70 | + {"swea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000080, OPCODE_MASK_H4, swea, memory_store_inst }, |
| 71 | {"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst }, |
| 72 | {"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst }, |
| 73 | {"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst }, |
| 74 | @@ -405,6 +414,8 @@ struct op_code_struct |
| 75 | {"clz", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34, clz, special_inst }, |
| 76 | {"mbar", INST_TYPE_IMM5, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN, mbar, special_inst }, |
| 77 | {"sleep", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 16. */ |
| 78 | + {"hibernate", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB9020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 8. */ |
| 79 | + {"suspend", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 24. */ |
| 80 | {"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst }, |
| 81 | {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst }, |
| 82 | {"", 0, 0, 0, 0, 0, 0, 0, 0}, |
| 83 | diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h |
Andrew Geissler | a9ff2b3 | 2020-10-16 10:11:54 -0500 | [diff] [blame] | 84 | index 795c57b5ff6..b05e319862e 100644 |
Brad Bishop | 286d45c | 2018-10-02 15:21:57 -0400 | [diff] [blame] | 85 | --- a/opcodes/microblaze-opcm.h |
| 86 | +++ b/opcodes/microblaze-opcm.h |
| 87 | @@ -33,13 +33,13 @@ enum microblaze_instr |
| 88 | /* 'or/and/xor' are C++ keywords. */ |
| 89 | microblaze_or, microblaze_and, microblaze_xor, |
| 90 | andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, |
| 91 | - wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br, |
| 92 | - brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt, |
| 93 | - bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, |
| 94 | + wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse, |
| 95 | + mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, |
| 96 | + bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, |
| 97 | imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid, |
| 98 | brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti, |
| 99 | - bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh, |
| 100 | - shr, sw, swr, swx, lbui, lhui, lwi, |
| 101 | + bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx, |
| 102 | + sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, |
Andrew Geissler | a9ff2b3 | 2020-10-16 10:11:54 -0500 | [diff] [blame] | 103 | sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv, |
Brad Bishop | 286d45c | 2018-10-02 15:21:57 -0400 | [diff] [blame] | 104 | fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, |
| 105 | fint, fsqrt, |
Andrew Geissler | 84ad7c5 | 2020-06-27 00:00:16 -0500 | [diff] [blame] | 106 | -- |
| 107 | 2.17.1 |
| 108 | |