| Manikandan Elumalai | 9fba388 | 2020-06-10 21:01:15 +0530 | [diff] [blame] | 1 | From ca2c08a7e710e4beff2fdf17bba5a74adff13db8 Mon Sep 17 00:00:00 2001 |
| 2 | From: Manikandan Elumalai <manikandan.hcl.ers.epl@gmail.com> |
| 3 | Date: Wed, 10 Jun 2020 17:53:59 +0530 |
| 4 | Subject: [PATCH] spl-host-console-handle |
| 5 | |
| 6 | This patch adds four 1S server console through debug card |
| 7 | connected to YosemiteV2 during boot. |
| 8 | |
| 9 | Handswitch in the adaptor card connected to AST2500 GPIOs as below, |
| 10 | GPIOAA7 ---SW_ID8 |
| 11 | GPIOAA6 ---SW_ID4 |
| 12 | GPIOAA5 ---SW_ID2 |
| 13 | GPIOAA4 ---SW_ID1 |
| 14 | |
| 15 | SW_ID8 SW_ID4 SW_ID2 SW_ID1 Position Descritpion |
| 16 | L L L L 1 1s server slot1 select |
| 17 | |
| 18 | L L H 2 1s server slot2 select |
| 19 | |
| 20 | L L H L 3 1s server slot3 select |
| 21 | |
| 22 | L L H H 4 1s server slot4 select |
| 23 | |
| 24 | L H L L 5 BMC Debug port select |
| 25 | |
| 26 | L H L H 6 1s server slot1 select |
| 27 | |
| 28 | L H H L 7 1s server slot2 select |
| 29 | |
| 30 | L H H H 8 1s server slot3 select |
| 31 | |
| 32 | H L L L 9 1s server slot4 select |
| 33 | |
| 34 | H L L H 10 BMC Debug port select |
| 35 | |
| 36 | BMC and Hosts UART control flow |
| 37 | GPIOE0 --- DEBUG_UART_SEL_0 |
| 38 | GPIOE1 --- DEBUG_UART_SEL_1 |
| 39 | GPIOE2 --- DEBUG_UART_SEL_2 |
| 40 | GPIOE2 --- DEBUG_UART_RX_SEL_N |
| 41 | |
| 42 | SEL_2 SEL_1 SEL_0 RX_SEL_N CONSOLE |
| 43 | 0 0 0 0 SLOT1 |
| 44 | 0 0 1 0 SLOT2 |
| 45 | 0 1 0 0 SLOT3 |
| 46 | 0 1 1 0 SLOT4 |
| 47 | 1 0 0 1 BMC Debug |
| 48 | |
| 49 | Signed-off-by: Manikandan Elumalai <manikandan.hcl.ers.epl@gmail.com> |
| 50 | --- |
| 51 | arch/arm/mach-aspeed/platform_g5.S | 68 +++++++++++++++++++++++++++++++++----- |
| 52 | 1 file changed, 60 insertions(+), 8 deletions(-) |
| 53 | |
| 54 | diff --git a/arch/arm/mach-aspeed/platform_g5.S b/arch/arm/mach-aspeed/platform_g5.S |
| 55 | index c3ce077..29daa7a 100644 |
| 56 | --- a/arch/arm/mach-aspeed/platform_g5.S |
| 57 | +++ b/arch/arm/mach-aspeed/platform_g5.S |
| 58 | @@ -315,6 +315,58 @@ orr r1, r1, #0xC |
| 59 | str r1, [r0] |
| 60 | .endm |
| 61 | |
| 62 | + .macro console_slot1 |
| 63 | + ldr r0, =0x1e780024 |
| 64 | + ldr r1, [r0] |
| 65 | + orr r1, r1, #0xF |
| 66 | + str r1, [r0] |
| 67 | + |
| 68 | + ldr r0, =0x1e780020 |
| 69 | + ldr r1, [r0] |
| 70 | + and r1, r1, #0xFFFFFFF0 |
| 71 | + orr r1, r1, #0x0 |
| 72 | + str r1, [r0] |
| 73 | + .endm |
| 74 | + |
| 75 | + .macro console_slot2 |
| 76 | + ldr r0, =0x1e780024 |
| 77 | + ldr r1, [r0] |
| 78 | + orr r1, r1, #0xF |
| 79 | + str r1, [r0] |
| 80 | + |
| 81 | + ldr r0, =0x1e780020 |
| 82 | + ldr r1, [r0] |
| 83 | + and r1, r1, #0xFFFFFFF0 |
| 84 | + orr r1, r1, #0x1 |
| 85 | + str r1, [r0] |
| 86 | + .endm |
| 87 | + |
| 88 | + .macro console_slot3 |
| 89 | + ldr r0, =0x1e780024 |
| 90 | + ldr r1, [r0] |
| 91 | + orr r1, r1, #0xF |
| 92 | + str r1, [r0] |
| 93 | + |
| 94 | + ldr r0, =0x1e780020 |
| 95 | + ldr r1, [r0] |
| 96 | + and r1, r1, #0xFFFFFFF0 |
| 97 | + orr r1, r1, #0x2 |
| 98 | + str r1, [r0] |
| 99 | + .endm |
| 100 | + |
| 101 | + .macro console_slot4 |
| 102 | + ldr r0, =0x1e780024 |
| 103 | + ldr r1, [r0] |
| 104 | + orr r1, r1, #0xF |
| 105 | + str r1, [r0] |
| 106 | + |
| 107 | + ldr r0, =0x1e780020 |
| 108 | + ldr r1, [r0] |
| 109 | + and r1, r1, #0xFFFFFFF0 |
| 110 | + orr r1, r1, #0x3 |
| 111 | + str r1, [r0] |
| 112 | + .endm |
| 113 | + |
| 114 | .macro console_sel |
| 115 | |
| 116 | // Disable SoL UARTs[1-4] |
| 117 | @@ -354,28 +406,28 @@ dbg_card_pres\@: |
| 118 | ldr r1, =0x00 |
| 119 | cmp r0, r1 |
| 120 | bne case_pos2\@ |
| 121 | - console_bmc |
| 122 | + console_slot1 |
| 123 | b case_end\@ |
| 124 | case_pos2\@: |
| 125 | //Test for position#2 |
| 126 | ldr r1, =0x01 |
| 127 | cmp r0, r1 |
| 128 | bne case_pos3\@ |
| 129 | - console_bmc |
| 130 | + console_slot2 |
| 131 | b case_end\@ |
| 132 | case_pos3\@: |
| 133 | //Test for position#3 |
| 134 | ldr r1, =0x02 |
| 135 | cmp r0, r1 |
| 136 | bne case_pos4\@ |
| 137 | - console_bmc |
| 138 | + console_slot3 |
| 139 | b case_end\@ |
| 140 | case_pos4\@: |
| 141 | //Test for position#4 |
| 142 | ldr r1, =0x03 |
| 143 | cmp r0, r1 |
| 144 | bne case_pos5\@ |
| 145 | - console_bmc |
| 146 | + console_slot4 |
| 147 | b case_end\@ |
| 148 | case_pos5\@: |
| 149 | //Test for position#5 |
| 150 | @@ -389,28 +441,28 @@ case_pos6\@: |
| 151 | ldr r1, =0x05 |
| 152 | cmp r0, r1 |
| 153 | bne case_pos7\@ |
| 154 | - console_bmc |
| 155 | + console_slot1 |
| 156 | b case_end\@ |
| 157 | case_pos7\@: |
| 158 | //Test for position#7 |
| 159 | ldr r1, =0x06 |
| 160 | cmp r0, r1 |
| 161 | bne case_pos8\@ |
| 162 | - console_bmc |
| 163 | + console_slot2 |
| 164 | b case_end\@ |
| 165 | case_pos8\@: |
| 166 | //Test for position#8 |
| 167 | ldr r1, =0x07 |
| 168 | cmp r0, r1 |
| 169 | bne case_pos9\@ |
| 170 | - console_bmc |
| 171 | + console_slot3 |
| 172 | b case_end\@ |
| 173 | case_pos9\@: |
| 174 | //Test for position#9 |
| 175 | ldr r1, =0x08 |
| 176 | cmp r0, r1 |
| 177 | bne case_pos10\@ |
| 178 | - console_bmc |
| 179 | + console_slot4 |
| 180 | b case_end\@ |
| 181 | case_pos10\@: |
| 182 | //Test for position#10 |
| 183 | -- |
| 184 | 2.7.4 |