blob: cedac06189f898cd7f34f4f01ac7bf267c9f322a [file] [log] [blame]
Patrick Williams8dd68482022-10-04 07:57:18 -05001From 83f9da30247c2d021658bc1b595c59ecc35eadf5 Mon Sep 17 00:00:00 2001
2From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
3Date: Fri, 29 Jul 2022 13:07:43 +0100
4Subject: [PATCH 07/26] arm64: smccc: clear the Xn registers after SMC calls
5
6set to zero the x0-x17 registers
7
8As per the SMCCC v1.2 spec, unused result and scratch registers can leak
9information after an SMC call. We can mitigate against this risk by
10returning zero in each register.
11
12Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
13Upstream-Status: Submitted [cover letter: https://lore.kernel.org/all/20220926101723.9965-1-abdellatif.elkhlifi@arm.com/]
14---
15
16Changelog:
17===============
18
19v4:
20
21* move the clearing code into a new macro: clear_gp_regs
22
23v3:
24
25* clear the Xn registers after SMC calls
26
27 arch/arm/cpu/armv8/smccc-call.S | 9 +++++++++
28 1 file changed, 9 insertions(+)
29
30diff --git a/arch/arm/cpu/armv8/smccc-call.S b/arch/arm/cpu/armv8/smccc-call.S
31index ec6f299bc9..32f3eb8eeb 100644
32--- a/arch/arm/cpu/armv8/smccc-call.S
33+++ b/arch/arm/cpu/armv8/smccc-call.S
34@@ -50,6 +50,12 @@ ENDPROC(__arm_smccc_hvc)
35
36 #ifdef CONFIG_ARM64
37
38+ .macro clear_gp_regs
39+ .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17
40+ mov x\n, xzr
41+ .endr
42+ .endm
43+
44 .macro SMCCC_1_2 instr
45 /* Save `res` and free a GPR that won't be clobbered */
46 stp x1, x19, [sp, #-16]!
47@@ -84,6 +90,9 @@ ENDPROC(__arm_smccc_hvc)
48 stp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
49 stp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
50
51+ /* x0-x17 registers can leak information after an SMC or HVC call. Let's clear them */
52+ clear_gp_regs
53+
54 /* Restore original x19 */
55 ldp xzr, x19, [sp], #16
56 ret
57--
582.17.1
59