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gerrit.openbmc.org / openbmc / openpower-hw-diags / c62813d4de33804c7ba5d82fe8ddc4a0f722c5ed / . / analyzer / ras-data / data / ras-data-odyssey-10.json
blob: e870eb543270da6acda21bb922047b8607a12a7b [file] [log] [blame]
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1{
2 "actions": {
3 "TBD": [
4 {
5 "name": "level2_M_th1",
6 "type": "action"
7 }
8 ],
9 "dimm0_H_mem_port0_L_th1": [
10 {
11 "guard": true,
12 "name": "dimm0",
13 "priority": "HIGH",
14 "type": "callout_unit"
15 },
16 {
17 "guard": false,
18 "name": "mem_port0",
19 "priority": "LOW",
20 "type": "callout_unit"
21 },
22 {
23 "name": "th_1",
24 "type": "action"
25 }
26 ],
27 "dimm0_H_mem_port0_L_th_32perDay": [
28 {
29 "guard": true,
30 "name": "dimm0",
31 "priority": "HIGH",
32 "type": "callout_unit"
33 },
34 {
35 "guard": false,
36 "name": "mem_port0",
37 "priority": "LOW",
38 "type": "callout_unit"
39 },
40 {
41 "name": "th_32perDay",
42 "type": "action"
43 }
44 ],
45 "dimm0_M": [
46 {
47 "guard": true,
48 "name": "dimm0",
49 "priority": "MED",
50 "type": "callout_unit"
51 }
52 ],
53 "dimm0_M_th1": [
54 {
55 "name": "dimm0_M",
56 "type": "action"
57 },
58 {
59 "name": "th_1",
60 "type": "action"
61 }
62 ],
63 "dimm1_H_mem_port1_L_th1": [
64 {
65 "guard": true,
66 "name": "dimm1",
67 "priority": "HIGH",
68 "type": "callout_unit"
69 },
70 {
71 "guard": false,
72 "name": "mem_port1",
73 "priority": "LOW",
74 "type": "callout_unit"
75 },
76 {
77 "name": "th_1",
78 "type": "action"
79 }
80 ],
81 "dimm1_H_mem_port1_L_th_32perDay": [
82 {
83 "guard": true,
84 "name": "dimm1",
85 "priority": "HIGH",
86 "type": "callout_unit"
87 },
88 {
89 "guard": false,
90 "name": "mem_port1",
91 "priority": "LOW",
92 "type": "callout_unit"
93 },
94 {
95 "name": "th_32perDay",
96 "type": "action"
97 }
98 ],
99 "dimm1_M": [
100 {
101 "guard": true,
102 "name": "dimm1",
103 "priority": "MED",
104 "type": "callout_unit"
105 }
106 ],
107 "dimm1_M_th1": [
108 {
109 "name": "dimm1_M",
110 "type": "action"
111 },
112 {
113 "name": "th_1",
114 "type": "action"
115 }
116 ],
117 "downstream_attn": [
118 {
119 "name": "level2_M_th1",
120 "type": "action"
121 }
122 ],
123 "level2_M": [
124 {
125 "name": "LEVEL2",
126 "priority": "MED",
127 "type": "callout_procedure"
128 }
129 ],
130 "level2_M_ocmb_L_th1": [
131 {
132 "name": "level2_M",
133 "type": "action"
134 },
135 {
136 "guard": false,
137 "priority": "LOW",
138 "type": "callout_self"
139 },
140 {
141 "name": "th_1",
142 "type": "action"
143 }
144 ],
145 "level2_M_th1": [
146 {
147 "name": "level2_M",
148 "type": "action"
149 },
150 {
151 "name": "th_1",
152 "type": "action"
153 }
154 ],
155 "mainline_iue_handling_0": [
156 {
157 "name": "dimm0_M_th1",
158 "type": "action"
159 }
160 ],
161 "mainline_iue_handling_1": [
162 {
163 "name": "dimm1_M_th1",
164 "type": "action"
165 }
166 ],
167 "mainline_nce_tce_handling": [
168 {
169 "name": "ocmb_M_th1",
170 "type": "action"
171 }
172 ],
173 "mainline_ue_handling_0": [
174 {
175 "name": "dimm0_M_th1",
176 "type": "action"
177 }
178 ],
179 "mainline_ue_handling_1": [
180 {
181 "name": "dimm1_M_th1",
182 "type": "action"
183 }
184 ],
185 "maintenance_aue_handling_0": [
186 {
187 "name": "dimm0_H_mem_port0_L_th1",
188 "type": "action"
189 }
190 ],
191 "maintenance_aue_handling_1": [
192 {
193 "name": "dimm1_H_mem_port1_L_th1",
194 "type": "action"
195 }
196 ],
197 "maintenance_iue_handling_0": [
198 {
199 "name": "dimm0_M_th1",
200 "type": "action"
201 }
202 ],
203 "maintenance_iue_handling_1": [
204 {
205 "name": "dimm1_M_th1",
206 "type": "action"
207 }
208 ],
209 "mcbist_program_complete": [
210 {
211 "name": "level2_M_th1",
212 "type": "action"
213 }
214 ],
215 "mem_port0_M": [
216 {
217 "guard": true,
218 "name": "mem_port0",
219 "priority": "MED",
220 "type": "callout_unit"
221 }
222 ],
223 "mem_port0_M_info_only": [
224 {
225 "name": "mem_port0_M_th_32perDay",
226 "type": "action"
227 },
228 {
229 "name": "informational_only",
230 "type": "flag"
231 }
232 ],
233 "mem_port0_M_th1": [
234 {
235 "name": "mem_port0_M",
236 "type": "action"
237 },
238 {
239 "name": "th_1",
240 "type": "action"
241 }
242 ],
243 "mem_port0_M_th_32perDay": [
244 {
245 "name": "mem_port0_M",
246 "type": "action"
247 },
248 {
249 "name": "th_32perDay",
250 "type": "action"
251 }
252 ],
253 "mem_port1_M": [
254 {
255 "guard": true,
256 "name": "mem_port1",
257 "priority": "MED",
258 "type": "callout_unit"
259 }
260 ],
261 "mem_port1_M_info_only": [
262 {
263 "name": "mem_port1_M_th_32perDay",
264 "type": "action"
265 },
266 {
267 "name": "informational_only",
268 "type": "flag"
269 }
270 ],
271 "mem_port1_M_th1": [
272 {
273 "name": "mem_port1_M",
274 "type": "action"
275 },
276 {
277 "name": "th_1",
278 "type": "action"
279 }
280 ],
281 "mem_port1_M_th_32perDay": [
282 {
283 "name": "mem_port1_M",
284 "type": "action"
285 },
286 {
287 "name": "th_32perDay",
288 "type": "action"
289 }
290 ],
291 "memory_impe_handling_0": [
292 {
293 "name": "dimm0_M_th1",
294 "type": "action"
295 }
296 ],
297 "memory_impe_handling_1": [
298 {
299 "name": "dimm1_M_th1",
300 "type": "action"
301 }
302 ],
303 "ocmb_H_omi_L_th1": [
304 {
305 "guard": true,
306 "priority": "HIGH",
307 "type": "callout_self"
308 },
309 {
310 "guard": false,
311 "name": "omi_bus",
312 "priority": "LOW",
313 "type": "callout_connected"
314 },
315 {
316 "name": "th_1",
317 "type": "action"
318 }
319 ],
320 "ocmb_M": [
321 {
322 "guard": true,
323 "priority": "MED",
324 "type": "callout_self"
325 }
326 ],
327 "ocmb_M_info_only": [
328 {
329 "name": "ocmb_M_th_32perDay",
330 "type": "action"
331 },
332 {
333 "name": "informational_only",
334 "type": "flag"
335 }
336 ],
337 "ocmb_M_info_only_th1": [
338 {
339 "name": "ocmb_M_th1",
340 "type": "action"
341 },
342 {
343 "name": "informational_only",
344 "type": "flag"
345 }
346 ],
347 "ocmb_M_level2_L_th1": [
348 {
349 "name": "ocmb_M",
350 "type": "action"
351 },
352 {
353 "name": "LEVEL2",
354 "priority": "LOW",
355 "type": "callout_procedure"
356 },
357 {
358 "name": "th_1",
359 "type": "action"
360 }
361 ],
362 "ocmb_M_th1": [
363 {
364 "name": "ocmb_M",
365 "type": "action"
366 },
367 {
368 "name": "th_1",
369 "type": "action"
370 }
371 ],
372 "ocmb_M_th_32perDay": [
373 {
374 "name": "ocmb_M",
375 "type": "action"
376 },
377 {
378 "name": "th_32perDay",
379 "type": "action"
380 }
381 ],
382 "omi_M": [
383 {
384 "guard": true,
385 "name": "omi_bus",
386 "priority": "MED",
387 "type": "callout_connected"
388 }
389 ],
390 "omi_M_th1": [
391 {
392 "name": "omi_M",
393 "type": "action"
394 },
395 {
396 "name": "th_1",
397 "type": "action"
398 }
399 ],
400 "omi_M_th_32perDay": [
401 {
402 "name": "omi_M",
403 "type": "action"
404 },
405 {
406 "name": "th_32perDay",
407 "type": "action"
408 }
409 ],
410 "omi_bus": [
411 {
412 "guard": true,
413 "priority": "MED_A",
414 "type": "callout_self"
415 },
416 {
417 "guard": true,
418 "name": "omi_bus",
419 "priority": "MED_A",
420 "type": "callout_connected"
421 },
422 {
423 "guard": false,
424 "name": "omi_bus",
425 "priority": "LOW",
426 "type": "callout_bus"
427 }
428 ],
429 "omi_bus_info_only": [
430 {
431 "name": "omi_bus_th_32perDay",
432 "type": "action"
433 },
434 {
435 "name": "informational_only",
436 "type": "flag"
437 }
438 ],
439 "omi_bus_th1": [
440 {
441 "name": "omi_bus",
442 "type": "action"
443 },
444 {
445 "name": "th_1",
446 "type": "action"
447 }
448 ],
449 "omi_bus_th_32perDay": [
450 {
451 "name": "omi_bus",
452 "type": "action"
453 },
454 {
455 "name": "th_32perDay",
456 "type": "action"
457 }
458 ],
459 "omi_degraded_mode": [
460 {
461 "name": "omi_bus_th1",
462 "type": "action"
463 }
464 ],
Zane Shelley06fb4032023-08-22 14:16:43 -0500[diff] [blame]465 "pcb_slave_parity": [
466 {
467 "name": "ocmb_M",
468 "type": "action"
469 },
470 {
471 "name": "th_1",
472 "type": "action"
473 }
474 ],
475 "pll_unlock": [
476 {
477 "instance": 0,
478 "name": "pll_unlock",
479 "type": "plugin"
480 }
481 ],
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]482 "srq_rcd_parity_error_0": [
483 {
484 "name": "dimm0_H_mem_port0_L_th1",
485 "type": "action"
486 }
487 ],
488 "srq_rcd_parity_error_1": [
489 {
490 "name": "dimm1_H_mem_port1_L_th1",
491 "type": "action"
492 }
493 ],
494 "srq_recov_parity_error": [
495 {
496 "name": "ocmb_M_th1",
497 "type": "action"
498 }
499 ],
500 "th_1": [],
501 "th_32perDay": [
502 {
503 "name": "recovered_error",
504 "type": "flag"
505 }
506 ],
507 "verify_chip_mark_0": [
508 {
509 "name": "ocmb_M_th1",
510 "type": "action"
511 }
512 ],
513 "verify_chip_mark_1": [
514 {
515 "name": "ocmb_M_th1",
516 "type": "action"
517 }
518 ],
519 "verify_chip_mark_2": [
520 {
521 "name": "ocmb_M_th1",
522 "type": "action"
523 }
524 ],
525 "verify_chip_mark_3": [
526 {
527 "name": "ocmb_M_th1",
528 "type": "action"
529 }
530 ],
531 "verify_chip_mark_4": [
532 {
533 "name": "ocmb_M_th1",
534 "type": "action"
535 }
536 ],
537 "verify_chip_mark_5": [
538 {
539 "name": "ocmb_M_th1",
540 "type": "action"
541 }
542 ],
543 "verify_chip_mark_6": [
544 {
545 "name": "ocmb_M_th1",
546 "type": "action"
547 }
548 ],
549 "verify_chip_mark_7": [
550 {
551 "name": "ocmb_M_th1",
552 "type": "action"
553 }
554 ]
555 },
556 "buses": {
557 "omi_bus": {
558 "type": "OMI_BUS"
559 }
560 },
561 "model_ec": "60c00010",
562 "signatures": {
563 "0cbf": {
564 "00": {
565 "00": "level2_M_th1",
566 "01": "level2_M_th1"
567 },
568 "01": {
569 "00": "mem_port0_M_th1",
570 "01": "mem_port1_M_th1"
571 },
572 "02": {
573 "00": "mem_port0_M_th1",
574 "01": "mem_port1_M_th1"
575 },
576 "03": {
577 "00": "mem_port0_M_th1",
578 "01": "mem_port1_M_th1"
579 },
580 "04": {
581 "00": "mem_port0_M_th1",
582 "01": "mem_port1_M_th1"
583 },
584 "05": {
585 "00": "level2_M_th1",
586 "01": "level2_M_th1"
587 },
588 "06": {
589 "00": "mem_port0_M_th1",
590 "01": "mem_port1_M_th1",
591 "flags": ["odp_data_corrupt_root_cause", "mask_but_dont_clear"]
592 },
593 "07": {
594 "00": "level2_M_th1",
595 "01": "level2_M_th1"
596 },
597 "08": {
598 "00": "level2_M_th1",
599 "01": "level2_M_th1"
600 },
601 "09": {
602 "00": "mem_port0_M_th1",
603 "01": "mem_port1_M_th1",
604 "flags": ["odp_data_corrupt_root_cause", "mask_but_dont_clear"]
605 },
606 "0a": {
607 "00": "mem_port0_M_th1",
608 "01": "mem_port1_M_th1",
609 "flags": ["odp_data_corrupt_root_cause", "mask_but_dont_clear"]
610 },
611 "0b": {
612 "00": "mem_port0_M_th1",
613 "01": "mem_port1_M_th1",
614 "flags": ["odp_data_corrupt_root_cause", "mask_but_dont_clear"]
615 },
616 "0c": {
617 "00": "mem_port0_M_th1",
618 "01": "mem_port1_M_th1",
619 "flags": ["odp_data_corrupt_root_cause", "mask_but_dont_clear"]
620 },
621 "0d": {
622 "00": "mem_port0_M_th1",
623 "01": "mem_port1_M_th1",
624 "flags": ["odp_data_corrupt_root_cause", "mask_but_dont_clear"]
625 },
626 "0e": {
627 "00": "level2_M_th1",
628 "01": "level2_M_th1"
629 },
630 "0f": {
631 "00": "level2_M_th1",
632 "01": "level2_M_th1"
633 },
634 "10": {
635 "00": "level2_M_th1",
636 "01": "level2_M_th1"
637 },
638 "11": {
639 "00": "level2_M_th1",
640 "01": "level2_M_th1"
641 },
642 "12": {
643 "00": "level2_M_th1",
644 "01": "level2_M_th1"
645 },
646 "13": {
647 "00": "level2_M_th1",
648 "01": "level2_M_th1"
649 },
650 "14": {
651 "00": "level2_M_th1",
652 "01": "level2_M_th1"
653 },
654 "15": {
655 "00": "level2_M_th1",
656 "01": "level2_M_th1"
657 }
658 },
659 "18ff": {
660 "00": {
661 "00": "level2_M_th1"
662 },
663 "01": {
664 "00": "level2_M_th1"
665 },
666 "02": {
667 "00": "level2_M_th1"
668 },
669 "03": {
670 "00": "level2_M_th1"
671 },
672 "04": {
673 "00": "ocmb_M_th1",
674 "flags": ["sue_source"]
675 },
676 "05": {
677 "00": "ocmb_M_th1",
678 "flags": ["sue_source"]
679 },
680 "06": {
681 "00": "ocmb_M_th1",
682 "flags": ["sue_source"]
683 },
684 "07": {
685 "00": "ocmb_M_th1"
686 },
687 "08": {
688 "00": "level2_M_th1"
689 },
690 "09": {
691 "00": "level2_M_th1"
692 },
693 "0a": {
694 "00": "level2_M_th1"
695 },
696 "0b": {
697 "00": "level2_M_th1"
698 },
699 "0c": {
700 "00": "level2_M_th1"
701 }
702 },
703 "1ff7": {
704 "00": {
705 "00": "level2_M_th1"
706 },
707 "01": {
708 "00": "ocmb_M_th1",
709 "flags": ["sue_source"]
710 },
711 "02": {
712 "00": "mem_port0_M_th_32perDay"
713 },
714 "03": {
715 "00": "level2_M_th1"
716 },
717 "04": {
718 "00": "srq_rcd_parity_error_0"
719 },
720 "05": {
721 "00": "ocmb_M_th1",
722 "flags": ["sue_source"]
723 },
724 "06": {
725 "00": "level2_M_th1"
726 },
727 "07": {
728 "00": "mem_port0_M_th1",
729 "flags": ["sue_source"]
730 },
731 "08": {
732 "00": "level2_M_th1"
733 },
734 "09": {
735 "00": "mem_port0_M_th1"
736 },
737 "0a": {
738 "00": "mem_port0_M_th1",
739 "flags": ["sue_source"]
740 },
741 "0b": {
742 "00": "mem_port0_M_th1",
743 "flags": ["sue_source"]
744 },
745 "0c": {
746 "00": "mem_port0_M_th1",
747 "flags": ["sue_source"]
748 },
749 "0d": {
750 "00": "dimm0_H_mem_port0_L_th1",
751 "flags": ["sue_source"]
752 },
753 "0e": {
754 "00": "ocmb_M_info_only"
755 },
756 "0f": {
757 "00": "level2_M_th1"
758 },
759 "10": {
760 "00": "ocmb_M_th1",
761 "flags": ["sue_source"]
762 },
763 "11": {
764 "00": "ocmb_M_th1",
765 "flags": ["sue_source"]
766 },
767 "12": {
768 "00": "ocmb_M_th1",
769 "flags": ["sue_source"]
770 },
771 "13": {
772 "00": "ocmb_M_th1",
773 "flags": ["sue_source"]
774 },
775 "14": {
776 "00": "ocmb_M_th1",
777 "flags": ["sue_source"]
778 },
779 "15": {
780 "00": "ocmb_M_th1"
781 },
782 "16": {
783 "00": "ocmb_M_th1",
784 "flags": ["sue_source"]
785 },
786 "17": {
787 "00": "ocmb_M_th_32perDay"
788 },
789 "18": {
790 "00": "mem_port0_M_th_32perDay"
791 },
792 "19": {
793 "00": "mem_port0_M_th_32perDay"
794 },
795 "1a": {
796 "00": "mem_port0_M_th1",
797 "flags": ["sue_source"]
798 },
799 "1b": {
800 "00": "mem_port1_M_th1",
801 "flags": ["sue_source"]
802 },
803 "1c": {
804 "00": "level2_M_th1"
805 },
806 "1d": {
807 "00": "srq_recov_parity_error"
808 },
809 "1e": {
810 "00": "mem_port0_M_th1"
811 },
812 "1f": {
813 "00": "mem_port0_M_th1",
814 "flags": ["sue_source"]
815 },
816 "20": {
817 "00": "mem_port1_M_th_32perDay"
818 },
819 "21": {
820 "00": "srq_rcd_parity_error_1"
821 },
822 "22": {
823 "00": "mem_port1_M_th1"
824 },
825 "23": {
826 "00": "level2_M_th1"
827 },
828 "24": {
829 "00": "mem_port1_M_th1"
830 },
831 "25": {
832 "00": "mem_port1_M_th1",
833 "flags": ["sue_source"]
834 },
835 "26": {
836 "00": "mem_port1_M_th1",
837 "flags": ["sue_source"]
838 },
839 "27": {
840 "00": "mem_port1_M_th1",
841 "flags": ["sue_source"]
842 },
843 "28": {
844 "00": "dimm1_H_mem_port1_L_th1",
845 "flags": ["sue_source"]
846 },
847 "29": {
848 "00": "mem_port1_M_th_32perDay"
849 },
850 "2a": {
851 "00": "mem_port1_M_th_32perDay"
852 },
853 "2b": {
854 "00": "mem_port1_M_th1",
855 "flags": ["sue_source"]
856 },
857 "2c": {
858 "00": "ocmb_M_th1",
859 "flags": ["sue_source"]
860 },
861 "2d": {
862 "00": "mem_port1_M_th1",
863 "flags": ["sue_source"]
Caleb Palmer7ad677a2023-06-14 10:39:53 -0500[diff] [blame]864 },
865 "2e": {
866 "00": "level2_M_th1"
867 },
868 "2f": {
869 "00": "level2_M_th1"
870 },
871 "30": {
872 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]873 }
874 },
875 "38df": {
876 "00": {
877 "00": "level2_M_th1"
878 },
879 "01": {
880 "00": "ocmb_M_th1",
881 "flags": ["sue_source"]
882 },
883 "02": {
884 "00": "omi_bus_th1",
885 "flags": ["sue_source"]
886 },
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982 "00": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]983 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]984 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]987 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]990 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1002 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1005 },
1006 "08": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1008 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1011 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1014 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1017 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1020 },
1021 "0d": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1023 },
1024 "0e": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1026 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1029 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1032 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1035 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1038 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1041 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1044 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1047 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1050 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1053 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1056 },
1057 "19": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1059 },
1060 "1a": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1062 },
1063 "1b": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1065 },
1066 "1c": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1068 },
1069 "1d": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1071 },
1072 "1e": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1074 },
1075 "1f": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1077 },
1078 "20": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1080 },
1081 "21": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1083 },
1084 "22": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1086 },
1087 "23": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1089 },
1090 "24": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1092 },
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1095 },
1096 "26": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1098 },
1099 "27": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1101 },
1102 "28": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1104 },
1105 "29": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1107 },
1108 "2a": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1110 },
1111 "2b": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1112 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1113 },
1114 "2c": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1116 },
1117 "2d": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1119 },
1120 "2e": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1122 },
1123 "2f": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1125 },
1126 "30": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1128 },
1129 "31": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1131 },
1132 "32": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1134 },
1135 "33": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1136 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1137 },
1138 "34": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1139 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1140 },
1141 "35": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1142 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1143 },
1144 "36": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1145 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1146 },
1147 "37": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1148 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1149 },
1150 "38": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1151 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1152 },
1153 "39": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1154 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1155 },
1156 "3a": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1157 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1158 },
1159 "3b": {
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Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1161 },
1162 "3c": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1163 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1164 },
1165 "3d": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1166 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1167 },
1168 "3e": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1169 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1170 },
1171 "3f": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1172 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1173 }
1174 },
1175 "58a8": {
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1176 "34": {
1177 "00": "ocmb_M_th1",
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1180 "35": {
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1191 },
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1200 "3a": {
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1207 },
1208 "3c": {
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1211 },
1212 "3d": {
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1215 },
1216 "3e": {
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1219 },
1220 "3f": {
1221 "00": "ocmb_M_th1",
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1223 }
1224 },
1225 "8d4d": {
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1227 "00": "level2_M_th1"
1228 },
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1234 },
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1238 },
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1241 "flags": ["sue_source"]
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1248 },
1249 "07": {
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1252 "08": {
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1254 },
1255 "09": {
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1257 },
1258 "0a": {
1259 "00": "level2_M_th1"
1260 },
1261 "0b": {
1262 "00": "mcbist_program_complete"
1263 },
1264 "0c": {
1265 "00": "level2_M_th1"
1266 },
1267 "0d": {
1268 "00": "level2_M_th1"
1269 },
1270 "0e": {
1271 "00": "ocmb_M_th1"
1272 },
1273 "0f": {
1274 "00": "ocmb_M_th1",
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1276 },
1277 "10": {
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1280 "11": {
1281 "00": "level2_M_th1"
1282 },
1283 "12": {
1284 "00": "level2_M_th1"
1285 }
1286 },
Zane Shelley06fb4032023-08-22 14:16:43 -0500[diff] [blame]1287 "9ecb": {
1288 "00": {
1289 "00": "pll_unlock"
1290 }
1291 },
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1292 "bc05": {
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1294 "00": "level2_M_th1"
1295 },
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1300 "02": {
1301 "00": "level2_M_th1"
1302 },
1303 "03": {
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1305 },
1306 "04": {
1307 "00": "level2_M_th1"
1308 },
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1312 },
1313 "06": {
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1316 "07": {
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1333 },
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1336 "flags": ["crc_root_cause", "mask_but_dont_clear"]
1337 },
1338 "0e": {
1339 "00": "ocmb_M_th1",
1340 "flags": ["crc_root_cause", "mask_but_dont_clear"]
1341 },
1342 "0f": {
1343 "00": "ocmb_M_level2_L_th1",
1344 "flags": ["crc_root_cause", "mask_but_dont_clear"]
1345 },
1346 "10": {
1347 "00": "level2_M_ocmb_L_th1",
1348 "flags": ["crc_root_cause", "mask_but_dont_clear"]
1349 },
1350 "11": {
1351 "00": "ocmb_M_level2_L_th1",
1352 "flags": ["crc_root_cause", "mask_but_dont_clear"]
1353 },
1354 "12": {
1355 "00": "ocmb_M_level2_L_th1",
1356 "flags": ["crc_root_cause", "mask_but_dont_clear"]
1357 },
1358 "13": {
1359 "00": "ocmb_M_info_only"
1360 },
1361 "14": {
1362 "00": "ocmb_M_th1",
1363 "flags": ["crc_root_cause", "mask_but_dont_clear"]
1364 },
1365 "15": {
1366 "00": "ocmb_M_th_32perDay"
1367 },
1368 "16": {
1369 "00": "level2_M_th1"
1370 },
1371 "17": {
1372 "00": "level2_M_ocmb_L_th1",
1373 "flags": ["crc_root_cause", "mask_but_dont_clear"]
1374 },
1375 "18": {
1376 "00": "ocmb_M_th_32perDay",
Caleb Palmera6830272023-06-12 16:05:58 -0500[diff] [blame]1377 "flags": ["mnfg_informational_only"]
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1378 },
1379 "19": {
1380 "00": "level2_M_th1"
1381 },
1382 "1a": {
1383 "00": "level2_M_ocmb_L_th1",
1384 "flags": ["crc_root_cause", "mask_but_dont_clear"]
1385 },
1386 "1b": {
1387 "00": "level2_M_ocmb_L_th1",
1388 "flags": ["crc_root_cause", "mask_but_dont_clear"]
1389 },
1390 "1c": {
1391 "00": "level2_M_th1"
1392 },
1393 "1d": {
1394 "00": "level2_M_th1"
1395 }
1396 },
1397 "df2a": {
1398 "00": {
1399 "00": "level2_M_th1"
1400 },
1401 "01": {
1402 "00": "ocmb_M_info_only"
1403 },
1404 "02": {
1405 "00": "ocmb_M_info_only"
1406 },
1407 "03": {
1408 "00": "ocmb_M_th_32perDay"
1409 },
1410 "04": {
1411 "00": "ocmb_M_th_32perDay"
1412 },
1413 "05": {
1414 "00": "ocmb_M_th_32perDay"
1415 },
1416 "06": {
1417 "00": "ocmb_M_info_only"
1418 },
1419 "07": {
1420 "00": "ocmb_M_info_only"
1421 },
1422 "08": {
1423 "00": "level2_M_th1"
1424 },
1425 "09": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1426 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1427 },
1428 "0a": {
1429 "00": "ocmb_M_info_only"
1430 },
1431 "0b": {
1432 "00": "ocmb_M_info_only"
1433 },
1434 "0c": {
1435 "00": "ocmb_M_info_only"
1436 },
1437 "0d": {
1438 "00": "ocmb_M_info_only"
1439 },
1440 "0e": {
1441 "00": "ocmb_M_info_only"
1442 },
1443 "0f": {
1444 "00": "level2_M_th1"
1445 },
1446 "10": {
1447 "00": "level2_M_th1"
1448 },
1449 "11": {
1450 "00": "level2_M_th1"
1451 },
1452 "12": {
Zane Shelley06fb4032023-08-22 14:16:43 -0500[diff] [blame]1453 "00": "pcb_slave_parity"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1454 },
1455 "13": {
1456 "00": "ocmb_M_th1"
1457 },
1458 "14": {
1459 "00": "ocmb_M_th1"
1460 },
1461 "15": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1462 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1463 },
1464 "16": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1465 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1466 },
1467 "17": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1468 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1469 },
1470 "18": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1471 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1472 },
1473 "19": {
1474 "00": "level2_M_th1"
1475 },
1476 "1a": {
1477 "00": "level2_M_th1"
1478 },
1479 "1b": {
Caleb Palmer100c7a22023-03-03 16:33:44 -0600[diff] [blame]1480 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1481 },
1482 "1c": {
1483 "00": "level2_M_th1"
1484 },
1485 "1d": {
1486 "00": "level2_M_th1"
1487 },
1488 "1e": {
1489 "00": "level2_M_ocmb_L_th1"
1490 },
1491 "1f": {
1492 "00": "ocmb_M_th1"
1493 },
1494 "20": {
1495 "00": "level2_M_th1"
1496 },
1497 "21": {
1498 "00": "level2_M_th1"
1499 },
1500 "22": {
1501 "00": "level2_M_th1"
1502 },
1503 "23": {
1504 "00": "level2_M_th1"
1505 },
1506 "24": {
1507 "00": "ocmb_M_th1"
1508 },
1509 "25": {
1510 "00": "ocmb_M_th1"
1511 },
1512 "26": {
1513 "00": "level2_M_th1"
1514 },
1515 "27": {
1516 "00": "level2_M_th1"
1517 },
1518 "28": {
1519 "00": "level2_M_th1"
1520 },
1521 "29": {
1522 "00": "level2_M_th1"
1523 },
1524 "2a": {
1525 "00": "level2_M_th1"
1526 },
1527 "2b": {
1528 "00": "level2_M_th1"
1529 },
1530 "2c": {
1531 "00": "level2_M_th1"
1532 },
1533 "2d": {
1534 "00": "ocmb_M_th1"
1535 },
1536 "2e": {
1537 "00": "level2_M_th1"
1538 },
1539 "2f": {
1540 "00": "level2_M_th1"
1541 },
1542 "30": {
1543 "00": "level2_M_th1"
1544 },
1545 "31": {
1546 "00": "level2_M_th1"
1547 },
1548 "32": {
1549 "00": "level2_M_th1"
1550 },
1551 "33": {
1552 "00": "level2_M_th1"
1553 },
1554 "34": {
1555 "00": "level2_M_th1"
1556 },
1557 "35": {
1558 "00": "level2_M_th1"
1559 },
1560 "36": {
1561 "00": "level2_M_th1"
1562 },
1563 "37": {
1564 "00": "level2_M_th1"
1565 },
1566 "38": {
1567 "00": "level2_M_th1"
1568 },
1569 "39": {
1570 "00": "level2_M_th1"
1571 },
1572 "3a": {
1573 "00": "level2_M_th1"
1574 },
1575 "3b": {
1576 "00": "level2_M_th1"
1577 },
1578 "3c": {
1579 "00": "level2_M_th1"
1580 },
1581 "3d": {
1582 "00": "level2_M_th1"
1583 },
1584 "3e": {
1585 "00": "level2_M_th1"
1586 },
1587 "3f": {
1588 "00": "level2_M_th1"
1589 }
1590 },
1591 "f8df": {
1592 "00": {
1593 "00": "level2_M_th1"
1594 },
1595 "01": {
1596 "00": "downstream_attn",
1597 "flags": ["sue_source"]
1598 },
1599 "02": {
1600 "00": "ocmb_M_th1",
1601 "flags": ["sue_source"]
1602 },
1603 "03": {
1604 "00": "ocmb_M_th_32perDay"
1605 },
1606 "04": {
Caleb Palmer9a649682023-08-16 09:50:46 -0500[diff] [blame]1607 "00": "omi_bus_info_only",
1608 "flags": ["crc_related_err"]
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1609 },
1610 "05": {
1611 "00": "level2_M_th1"
1612 },
1613 "06": {
1614 "00": "omi_degraded_mode",
1615 "flags": ["crc_related_err"]
1616 },
1617 "07": {
Caleb Palmer9a649682023-08-16 09:50:46 -0500[diff] [blame]1618 "00": "omi_bus_info_only",
1619 "flags": ["crc_related_err"]
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1620 },
1621 "08": {
Caleb Palmer9a649682023-08-16 09:50:46 -0500[diff] [blame]1622 "00": "omi_bus_th_32perDay",
1623 "flags": ["crc_related_err"]
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1624 },
1625 "09": {
1626 "00": "level2_M_th1"
1627 },
1628 "0a": {
1629 "00": "omi_bus_th_32perDay"
1630 },
1631 "0b": {
Caleb Palmer9a649682023-08-16 09:50:46 -0500[diff] [blame]1632 "00": "omi_bus_th_32perDay",
1633 "flags": ["crc_related_err"]
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1634 },
1635 "0c": {
1636 "00": "level2_M_th1"
1637 },
1638 "0d": {
1639 "00": "level2_M_th1"
1640 },
1641 "0e": {
1642 "00": "level2_M_th1"
1643 },
1644 "0f": {
1645 "00": "level2_M_th1"
1646 },
1647 "10": {
1648 "00": "level2_M_th1"
1649 },
1650 "11": {
1651 "00": "level2_M_th1"
1652 },
1653 "12": {
1654 "00": "level2_M_th1"
1655 },
1656 "13": {
1657 "00": "level2_M_th1"
1658 },
1659 "14": {
1660 "00": "level2_M_th1"
1661 },
1662 "15": {
1663 "00": "ocmb_M_info_only_th1",
1664 "flags": ["crc_root_cause", "mask_but_dont_clear"]
1665 },
1666 "16": {
1667 "00": "omi_bus_th_32perDay"
1668 },
1669 "17": {
1670 "00": "level2_M_th1"
1671 },
1672 "18": {
1673 "00": "level2_M_th1"
1674 },
1675 "19": {
1676 "00": "level2_M_th1"
1677 },
1678 "1a": {
1679 "00": "level2_M_th1"
1680 },
1681 "1b": {
1682 "00": "level2_M_th1"
1683 },
1684 "1c": {
1685 "00": "level2_M_th1"
1686 },
1687 "1d": {
1688 "00": "level2_M_th1"
1689 },
1690 "1e": {
1691 "00": "level2_M_th1"
1692 },
1693 "1f": {
1694 "00": "level2_M_th1"
1695 },
1696 "20": {
1697 "00": "level2_M_th1"
1698 },
1699 "21": {
1700 "00": "level2_M_th1"
1701 },
1702 "22": {
1703 "00": "level2_M_th1"
1704 },
1705 "23": {
1706 "00": "level2_M_th1"
1707 },
1708 "24": {
1709 "00": "level2_M_th1"
1710 },
1711 "25": {
1712 "00": "level2_M_th1"
1713 },
1714 "26": {
1715 "00": "level2_M_th1"
1716 },
1717 "27": {
1718 "00": "level2_M_th1"
1719 },
1720 "28": {
1721 "00": "level2_M_th1"
1722 },
1723 "29": {
1724 "00": "level2_M_th1"
1725 },
1726 "2a": {
1727 "00": "level2_M_th1"
1728 },
1729 "2b": {
1730 "00": "level2_M_th1"
1731 },
1732 "2c": {
1733 "00": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1734 }
1735 },
1736 "fabf": {
1737 "00": {
1738 "00": "level2_M_th1",
1739 "01": "level2_M_th1"
1740 },
1741 "01": {
1742 "00": "verify_chip_mark_0",
1743 "01": "verify_chip_mark_0"
1744 },
1745 "02": {
1746 "00": "verify_chip_mark_1",
1747 "01": "verify_chip_mark_1"
1748 },
1749 "03": {
1750 "00": "verify_chip_mark_2",
1751 "01": "verify_chip_mark_2"
1752 },
1753 "04": {
1754 "00": "verify_chip_mark_3",
1755 "01": "verify_chip_mark_3"
1756 },
1757 "05": {
1758 "00": "verify_chip_mark_4",
1759 "01": "verify_chip_mark_4"
1760 },
1761 "06": {
1762 "00": "verify_chip_mark_5",
1763 "01": "verify_chip_mark_5"
1764 },
1765 "07": {
1766 "00": "verify_chip_mark_6",
1767 "01": "verify_chip_mark_6"
1768 },
1769 "08": {
1770 "00": "verify_chip_mark_7",
1771 "01": "verify_chip_mark_7"
1772 },
1773 "09": {
1774 "00": "mainline_nce_tce_handling",
1775 "01": "mainline_nce_tce_handling"
1776 },
1777 "0a": {
1778 "00": "mainline_nce_tce_handling",
1779 "01": "mainline_nce_tce_handling"
1780 },
1781 "0b": {
1782 "00": "level2_M_th1",
1783 "01": "level2_M_th1"
1784 },
1785 "0c": {
1786 "00": "level2_M_th1",
1787 "01": "level2_M_th1"
1788 },
1789 "0d": {
1790 "00": "level2_M_th1",
1791 "01": "level2_M_th1"
1792 },
1793 "0e": {
1794 "00": "dimm0_H_mem_port0_L_th1",
1795 "01": "dimm1_H_mem_port1_L_th1",
1796 "flags": ["odp_data_corrupt_side_effect", "sue_source"]
1797 },
1798 "0f": {
1799 "00": "mainline_ue_handling_0",
1800 "01": "mainline_ue_handling_1",
1801 "flags": ["odp_data_corrupt_side_effect"]
1802 },
1803 "10": {
1804 "00": "dimm0_H_mem_port0_L_th1",
1805 "01": "dimm1_H_mem_port1_L_th1",
1806 "flags": ["sue_source"]
1807 },
1808 "11": {
1809 "00": "dimm0_H_mem_port0_L_th1",
1810 "01": "dimm1_H_mem_port1_L_th1",
1811 "flags": ["odp_data_corrupt_side_effect", "sue_source"]
1812 },
1813 "12": {
1814 "00": "mainline_iue_handling_0",
1815 "01": "mainline_iue_handling_1",
1816 "flags": ["sue_source", "odp_data_corrupt_side_effect"]
1817 },
1818 "13": {
1819 "00": "dimm0_H_mem_port0_L_th_32perDay",
1820 "01": "dimm1_H_mem_port1_L_th_32perDay"
1821 },
1822 "14": {
1823 "00": "memory_impe_handling_0",
1824 "01": "memory_impe_handling_1"
1825 },
1826 "15": {
1827 "00": "level2_M_th1",
1828 "01": "level2_M_th1"
1829 },
1830 "16": {
1831 "00": "level2_M_th1",
1832 "01": "level2_M_th1"
1833 },
1834 "17": {
1835 "00": "level2_M_th1",
1836 "01": "level2_M_th1"
1837 },
1838 "18": {
1839 "00": "level2_M_th1",
1840 "01": "level2_M_th1"
1841 },
1842 "19": {
1843 "00": "level2_M_th1",
1844 "01": "level2_M_th1"
1845 },
1846 "1a": {
1847 "00": "level2_M_th1",
1848 "01": "level2_M_th1"
1849 },
1850 "1b": {
1851 "00": "level2_M_th1",
1852 "01": "level2_M_th1"
1853 },
1854 "1c": {
1855 "00": "level2_M_th1",
1856 "01": "level2_M_th1"
1857 },
1858 "1d": {
1859 "00": "level2_M_th1",
1860 "01": "level2_M_th1"
1861 },
1862 "1e": {
1863 "00": "level2_M_th1",
1864 "01": "level2_M_th1"
1865 },
1866 "1f": {
1867 "00": "level2_M_th1",
1868 "01": "level2_M_th1"
1869 },
1870 "20": {
1871 "00": "level2_M_th1",
1872 "01": "level2_M_th1"
1873 },
1874 "21": {
1875 "00": "level2_M_th1",
1876 "01": "level2_M_th1"
1877 },
1878 "22": {
1879 "00": "dimm0_H_mem_port0_L_th1",
1880 "01": "dimm1_H_mem_port1_L_th1",
1881 "flags": ["odp_data_corrupt_side_effect", "sue_source"]
1882 },
1883 "23": {
1884 "00": "level2_M_th1",
1885 "01": "level2_M_th1"
1886 },
1887 "24": {
1888 "00": "dimm0_H_mem_port0_L_th1",
1889 "01": "dimm1_H_mem_port1_L_th1"
1890 },
1891 "25": {
1892 "00": "dimm0_H_mem_port0_L_th1",
1893 "01": "dimm1_H_mem_port1_L_th1",
1894 "flags": ["odp_data_corrupt_side_effect", "sue_source"]
1895 },
1896 "26": {
1897 "00": "maintenance_iue_handling_0",
1898 "01": "maintenance_iue_handling_1",
1899 "flags": ["sue_source", "odp_data_corrupt_side_effect"]
1900 },
1901 "27": {
1902 "00": "dimm0_H_mem_port0_L_th_32perDay",
1903 "01": "dimm1_H_mem_port1_L_th_32perDay"
1904 },
1905 "28": {
1906 "00": "memory_impe_handling_0",
1907 "01": "memory_impe_handling_1"
1908 },
1909 "29": {
1910 "00": "mem_port0_M_th_32perDay",
1911 "01": "mem_port1_M_th_32perDay"
1912 },
1913 "2a": {
1914 "00": "mem_port0_M_info_only",
1915 "01": "mem_port1_M_info_only"
1916 },
1917 "2b": {
1918 "00": "mem_port0_M_th1",
1919 "01": "mem_port1_M_th1"
1920 },
1921 "2c": {
1922 "00": "mem_port0_M_th1",
1923 "01": "mem_port1_M_th1",
1924 "flags": ["sue_source"]
1925 },
1926 "2d": {
1927 "00": "mem_port0_M_th1",
1928 "01": "mem_port1_M_th1",
1929 "flags": ["sue_source"]
1930 },
1931 "2e": {
1932 "00": "mem_port0_M_th_32perDay",
1933 "01": "mem_port1_M_th_32perDay"
1934 },
1935 "2f": {
Caleb Palmera6830272023-06-12 16:05:58 -0500[diff] [blame]1936 "00": "mem_port0_M_th_32perDay",
1937 "01": "mem_port1_M_th_32perDay"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1938 },
1939 "30": {
1940 "00": "mem_port0_M_th1",
1941 "01": "mem_port1_M_th1",
1942 "flags": ["sue_source"]
1943 },
1944 "31": {
Caleb Palmera6830272023-06-12 16:05:58 -0500[diff] [blame]1945 "00": "mem_port0_M_th1",
1946 "01": "mem_port1_M_th1",
1947 "flags": ["sue_source"]
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1948 },
1949 "32": {
1950 "00": "level2_M_th1",
1951 "01": "level2_M_th1"
1952 },
1953 "33": {
Caleb Palmera6830272023-06-12 16:05:58 -0500[diff] [blame]1954 "00": "level2_M_th1",
1955 "01": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1956 },
1957 "34": {
1958 "00": "level2_M_th1",
1959 "01": "level2_M_th1"
1960 },
1961 "35": {
Caleb Palmera6830272023-06-12 16:05:58 -0500[diff] [blame]1962 "00": "level2_M_th1",
1963 "01": "level2_M_th1"
Caleb Palmerd5fa9582023-02-27 16:12:41 -0600[diff] [blame]1964 },
1965 "36": {
1966 "00": "mem_port0_M_th1",
1967 "01": "mem_port1_M_th1",
1968 "flags": ["sue_source"]
1969 },
1970 "37": {
1971 "00": "level2_M_th1",
1972 "01": "level2_M_th1"
1973 },
1974 "38": {
1975 "00": "level2_M_th1",
1976 "01": "level2_M_th1"
1977 },
1978 "39": {
1979 "00": "level2_M_th1",
1980 "01": "level2_M_th1"
1981 },
1982 "3a": {
1983 "00": "level2_M_th1",
1984 "01": "level2_M_th1"
1985 },
1986 "3b": {
1987 "00": "level2_M_th1",
1988 "01": "level2_M_th1"
1989 },
1990 "3c": {
1991 "00": "level2_M_th1",
1992 "01": "level2_M_th1"
1993 },
1994 "3d": {
1995 "00": "level2_M_th1",
1996 "01": "level2_M_th1"
1997 },
1998 "3e": {
1999 "00": "level2_M_th1",
2000 "01": "level2_M_th1"
2001 }
2002 }
2003 },
2004 "units": {
2005 "dimm0": "mem_port0/dimm0",
2006 "dimm1": "mem_port1/dimm1",
2007 "mem_port0": "mem_port0",
2008 "mem_port1": "mem_port1"
2009 },
2010 "version": 2
2011}