| <?xml version="1.0" encoding="UTF-8"?> |
| <attn_node model_ec="P10_10,P10_20" name="EQ_L3_FIR" reg_type="SCOM"> |
| <local_fir config="" name="EQ_L3_FIR"> |
| <instance addr="0x20018600" reg_inst="0"/> |
| <instance addr="0x20014600" reg_inst="1"/> |
| <instance addr="0x20012600" reg_inst="2"/> |
| <instance addr="0x20011600" reg_inst="3"/> |
| <instance addr="0x21018600" reg_inst="4"/> |
| <instance addr="0x21014600" reg_inst="5"/> |
| <instance addr="0x21012600" reg_inst="6"/> |
| <instance addr="0x21011600" reg_inst="7"/> |
| <instance addr="0x22018600" reg_inst="8"/> |
| <instance addr="0x22014600" reg_inst="9"/> |
| <instance addr="0x22012600" reg_inst="10"/> |
| <instance addr="0x22011600" reg_inst="11"/> |
| <instance addr="0x23018600" reg_inst="12"/> |
| <instance addr="0x23014600" reg_inst="13"/> |
| <instance addr="0x23012600" reg_inst="14"/> |
| <instance addr="0x23011600" reg_inst="15"/> |
| <instance addr="0x24018600" reg_inst="16"/> |
| <instance addr="0x24014600" reg_inst="17"/> |
| <instance addr="0x24012600" reg_inst="18"/> |
| <instance addr="0x24011600" reg_inst="19"/> |
| <instance addr="0x25018600" reg_inst="20"/> |
| <instance addr="0x25014600" reg_inst="21"/> |
| <instance addr="0x25012600" reg_inst="22"/> |
| <instance addr="0x25011600" reg_inst="23"/> |
| <instance addr="0x26018600" reg_inst="24"/> |
| <instance addr="0x26014600" reg_inst="25"/> |
| <instance addr="0x26012600" reg_inst="26"/> |
| <instance addr="0x26011600" reg_inst="27"/> |
| <instance addr="0x27018600" reg_inst="28"/> |
| <instance addr="0x27014600" reg_inst="29"/> |
| <instance addr="0x27012600" reg_inst="30"/> |
| <instance addr="0x27011600" reg_inst="31"/> |
| <action attn_type="CS" config="00"/> |
| <action attn_type="RE" config="01"/> |
| </local_fir> |
| <register name="L3_ERR_RPT0"> |
| <instance addr="0x20018610" reg_inst="0"/> |
| <instance addr="0x20014610" reg_inst="1"/> |
| <instance addr="0x20012610" reg_inst="2"/> |
| <instance addr="0x20011610" reg_inst="3"/> |
| <instance addr="0x21018610" reg_inst="4"/> |
| <instance addr="0x21014610" reg_inst="5"/> |
| <instance addr="0x21012610" reg_inst="6"/> |
| <instance addr="0x21011610" reg_inst="7"/> |
| <instance addr="0x22018610" reg_inst="8"/> |
| <instance addr="0x22014610" reg_inst="9"/> |
| <instance addr="0x22012610" reg_inst="10"/> |
| <instance addr="0x22011610" reg_inst="11"/> |
| <instance addr="0x23018610" reg_inst="12"/> |
| <instance addr="0x23014610" reg_inst="13"/> |
| <instance addr="0x23012610" reg_inst="14"/> |
| <instance addr="0x23011610" reg_inst="15"/> |
| <instance addr="0x24018610" reg_inst="16"/> |
| <instance addr="0x24014610" reg_inst="17"/> |
| <instance addr="0x24012610" reg_inst="18"/> |
| <instance addr="0x24011610" reg_inst="19"/> |
| <instance addr="0x25018610" reg_inst="20"/> |
| <instance addr="0x25014610" reg_inst="21"/> |
| <instance addr="0x25012610" reg_inst="22"/> |
| <instance addr="0x25011610" reg_inst="23"/> |
| <instance addr="0x26018610" reg_inst="24"/> |
| <instance addr="0x26014610" reg_inst="25"/> |
| <instance addr="0x26012610" reg_inst="26"/> |
| <instance addr="0x26011610" reg_inst="27"/> |
| <instance addr="0x27018610" reg_inst="28"/> |
| <instance addr="0x27014610" reg_inst="29"/> |
| <instance addr="0x27012610" reg_inst="30"/> |
| <instance addr="0x27011610" reg_inst="31"/> |
| </register> |
| <register name="L3_ERR_RPT1"> |
| <instance addr="0x20018617" reg_inst="0"/> |
| <instance addr="0x20014617" reg_inst="1"/> |
| <instance addr="0x20012617" reg_inst="2"/> |
| <instance addr="0x20011617" reg_inst="3"/> |
| <instance addr="0x21018617" reg_inst="4"/> |
| <instance addr="0x21014617" reg_inst="5"/> |
| <instance addr="0x21012617" reg_inst="6"/> |
| <instance addr="0x21011617" reg_inst="7"/> |
| <instance addr="0x22018617" reg_inst="8"/> |
| <instance addr="0x22014617" reg_inst="9"/> |
| <instance addr="0x22012617" reg_inst="10"/> |
| <instance addr="0x22011617" reg_inst="11"/> |
| <instance addr="0x23018617" reg_inst="12"/> |
| <instance addr="0x23014617" reg_inst="13"/> |
| <instance addr="0x23012617" reg_inst="14"/> |
| <instance addr="0x23011617" reg_inst="15"/> |
| <instance addr="0x24018617" reg_inst="16"/> |
| <instance addr="0x24014617" reg_inst="17"/> |
| <instance addr="0x24012617" reg_inst="18"/> |
| <instance addr="0x24011617" reg_inst="19"/> |
| <instance addr="0x25018617" reg_inst="20"/> |
| <instance addr="0x25014617" reg_inst="21"/> |
| <instance addr="0x25012617" reg_inst="22"/> |
| <instance addr="0x25011617" reg_inst="23"/> |
| <instance addr="0x26018617" reg_inst="24"/> |
| <instance addr="0x26014617" reg_inst="25"/> |
| <instance addr="0x26012617" reg_inst="26"/> |
| <instance addr="0x26011617" reg_inst="27"/> |
| <instance addr="0x27018617" reg_inst="28"/> |
| <instance addr="0x27014617" reg_inst="29"/> |
| <instance addr="0x27012617" reg_inst="30"/> |
| <instance addr="0x27011617" reg_inst="31"/> |
| </register> |
| <capture_group node_inst="0:31"> |
| <capture_register reg_name="L3_ERR_RPT0" reg_inst= "0:31" /> |
| <capture_register reg_name="L3_ERR_RPT1" reg_inst= "0:31" /> |
| </capture_group> |
| <bit pos="0">No members available for a CGC</bit> |
| <bit pos="1">L3 attempted to master a CP (Castout/Push) command</bit> |
| <bit pos="2">Access attempted to use invalid topology table entry</bit> |
| <bit pos="3">L3 cache CE and UE within a short period</bit> |
| <bit pos="4">CE detected on L3 cache read</bit> |
| <bit pos="5">UE detected on L3 cache read</bit> |
| <bit pos="6">SUE detected on L3 cache read</bit> |
| <bit pos="7">L3 cache write data CE from Power Bus</bit> |
| <bit pos="8">L3 cache write data UE from Power Bus</bit> |
| <bit pos="9">L3 cache write data sue from Power Bus</bit> |
| <bit pos="10">L3 cache write data CE from L2</bit> |
| <bit pos="11">L3 cache write data UE from L2</bit> |
| <bit pos="12">L3 cache write SUE from L2</bit> |
| <bit pos="13">L3 DIR read CE</bit> |
| <bit pos="14">L3 Dir read UE</bit> |
| <bit pos="15">Dir error not found during corr seq</bit> |
| <bit pos="16">Received addr_error cresp on Snoop Machine or Castout Operation</bit> |
| <bit pos="17">Received addr_error cresp for Prefetch Operation</bit> |
| <bit pos="18">L3_PB_HANG_POLL</bit> |
| <bit pos="19">Invalid LRU count error</bit> |
| <bit pos="20">Reserved</bit> |
| <bit pos="21">Reserved</bit> |
| <bit pos="22">Reserved</bit> |
| <bit pos="23">Prefetch or Write Inject machine PowerBus data hang check</bit> |
| <bit pos="24">L3 Hw control err</bit> |
| <bit pos="25">Cache inhibited op in L3 directory</bit> |
| <bit pos="26">L3 line delete CE done</bit> |
| <bit pos="27">L3 snooped an incoming LCO</bit> |
| <bit pos="28">LRU intended to victimize a line, but invalid line selected</bit> |
| <bit pos="29">L3 cache congruence class deleted</bit> |
| <bit pos="30">Incoming LCO ID mismatch</bit> |
| <bit pos="31">L3 PowerBus Master Write CRESP ack_dead</bit> |
| <bit pos="32">PB Master Read received ack_dead CRESP</bit> |
| </attn_node> |