xml/p10/node_pau_ptl_fir.xml

<?xml version="1.0" encoding="UTF-8"?>
<attn_node model_ec="P10_10,P10_20" name="PAU_PTL_FIR" reg_type="SCOM">
    <local_fir config="W" name="PAU_PTL_FIR">
        <instance addr="0x10011800" reg_inst="0"/>
        <instance addr="0x11011800" reg_inst="1"/>
        <instance addr="0x12011800" reg_inst="2"/>
        <instance addr="0x13011800" reg_inst="3"/>
        <action attn_type="CS" config="00"/>
        <action attn_type="RE" config="01"/>
        <action attn_type="SPA" config="10"/>
    </local_fir>
    <bit pos="0">fmr00 trained. Even PTL, even half.</bit>
    <bit pos="1">fmr01 trained. Even PTL, odd half.</bit>
    <bit pos="2">fmr02 trained. Odd PTL, even half.</bit>
    <bit pos="3">fmr03 trained. Odd PTL, odd half.</bit>
    <bit pos="4">dob01 ue</bit>
    <bit pos="5">dob01 ce</bit>
    <bit pos="6">dob01 sue</bit>
    <bit pos="7">data outbound switch internal error - even PTL.</bit>
    <bit pos="8">dob23 ue</bit>
    <bit pos="9">dob23 ce</bit>
    <bit pos="10">dob23 sue</bit>
    <bit pos="11">data outbound switch internal error - odd PTL.</bit>
    <bit pos="12">Even PTL, even framer internal error</bit>
    <bit pos="13">Even PTL, outbound switch cmd/presp/cresp internal error</bit>
    <bit pos="14">Even PTL, odd framer internal error</bit>
    <bit pos="15">Odd PTL, even framer internal error</bit>
    <bit pos="16">Odd PTL, outbound switch cmd/presp/cresp internal error</bit>
    <bit pos="17">Odd PTL, odd framer internal error</bit>
    <bit pos="18">Even PTL, even parser internal error</bit>
    <bit pos="19">Even PTL, odd parser internal error</bit>
    <bit pos="20">Odd PTL, even parser internal error</bit>
    <bit pos="21">Odd PTL, odd parser internal error</bit>
    <bit pos="22">Even PTL, even link down</bit>
    <bit pos="23">Even PTL, odd link down</bit>
    <bit pos="24">Odd PTL, even link down</bit>
    <bit pos="25">Odd PTL, odd link down</bit>
    <bit pos="26">Even PTL data inbound switch internal error</bit>
    <bit pos="27">Odd PTL data inbound switch internal error</bit>
    <bit pos="28">mailbox 00 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_00_REG.</bit>
    <bit pos="29">mailbox 01 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_01_REG.</bit>
    <bit pos="30">mailbox 10 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_10_REG.</bit>
    <bit pos="31">mailbox 11 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_11_REG.</bit>
    <bit pos="32">mailbox 20 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_20_REG.</bit>
    <bit pos="33">mailbox 21 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_21_REG.</bit>
    <bit pos="34">mailbox 30 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_30_REG.</bit>
    <bit pos="35">mailbox 31 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_31_REG.</bit>
    <bit pos="36">ptl0 spare</bit>
    <bit pos="37">ptl1 spare</bit>
    <bit pos="38">ptl2 spare</bit>
    <bit pos="39">ptl3 spare</bit>
</attn_node>