Fix signature descriptions for chiplet FIRs
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: Ia997666829269597ee87aa0685499badc86b83ba
diff --git a/xml/p10/node_cfir_eq_cs.xml b/xml/p10/node_cfir_eq_cs.xml
index f5b3ee3..be57835 100644
--- a/xml/p10/node_cfir_eq_cs.xml
+++ b/xml/p10/node_cfir_eq_cs.xml
@@ -29,22 +29,22 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Local FIR</bit>
- <bit child_node="EQ_L2_FIR" node_inst="0,4,8,12,16,20,24,28" pos="9">L2 FIR Register</bit>
- <bit child_node="EQ_L2_FIR" node_inst="1,5,9,13,17,21,25,29" pos="10">L2 FIR Register</bit>
- <bit child_node="EQ_L2_FIR" node_inst="2,6,10,14,18,22,26,30" pos="11">L2 FIR Register</bit>
- <bit child_node="EQ_L2_FIR" node_inst="3,7,11,15,19,23,27,31" pos="12">L2 FIR Register</bit>
- <bit child_node="EQ_L3_FIR" node_inst="0,4,8,12,16,20,24,28" pos="13">L3 FIR Register</bit>
- <bit child_node="EQ_L3_FIR" node_inst="1,5,9,13,17,21,25,29" pos="14">L3 FIR Register</bit>
- <bit child_node="EQ_L3_FIR" node_inst="2,6,10,14,18,22,26,30" pos="15">L3 FIR Register</bit>
- <bit child_node="EQ_L3_FIR" node_inst="3,7,11,15,19,23,27,31" pos="16">L3 FIR Register</bit>
- <bit child_node="EQ_NCU_FIR" node_inst="0,4,8,12,16,20,24,28" pos="17">NCU FIR Register</bit>
- <bit child_node="EQ_NCU_FIR" node_inst="1,5,9,13,17,21,25,29" pos="18">NCU FIR Register</bit>
- <bit child_node="EQ_NCU_FIR" node_inst="2,6,10,14,18,22,26,30" pos="19">NCU FIR Register</bit>
- <bit child_node="EQ_NCU_FIR" node_inst="3,7,11,15,19,23,27,31" pos="20">NCU FIR Register</bit>
- <bit child_node="EQ_QME_FIR" node_inst="0,1,2,3,4,5,6,7" pos="21">QME Local Fault Isolation Register</bit>
- <bit child_node="EQ_CORE_FIR" node_inst="0,4,8,12,16,20,24,28" pos="5">Core Fault Isolation Register</bit>
- <bit child_node="EQ_CORE_FIR" node_inst="1,5,9,13,17,21,25,29" pos="6">Core Fault Isolation Register</bit>
- <bit child_node="EQ_CORE_FIR" node_inst="2,6,10,14,18,22,26,30" pos="7">Core Fault Isolation Register</bit>
- <bit child_node="EQ_CORE_FIR" node_inst="3,7,11,15,19,23,27,31" pos="8">Core Fault Isolation Register</bit>
+ <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Attention from EQ_LOCAL_FIR</bit>
+ <bit child_node="EQ_L2_FIR" node_inst="0,4,8,12,16,20,24,28" pos="9">Attention from EQ_L2_FIR 0</bit>
+ <bit child_node="EQ_L2_FIR" node_inst="1,5,9,13,17,21,25,29" pos="10">Attention from EQ_L2_FIR 1</bit>
+ <bit child_node="EQ_L2_FIR" node_inst="2,6,10,14,18,22,26,30" pos="11">Attention from EQ_L2_FIR 2</bit>
+ <bit child_node="EQ_L2_FIR" node_inst="3,7,11,15,19,23,27,31" pos="12">Attention from EQ_L2_FIR 2</bit>
+ <bit child_node="EQ_L3_FIR" node_inst="0,4,8,12,16,20,24,28" pos="13">Attention from EQ_L3_FIR 0</bit>
+ <bit child_node="EQ_L3_FIR" node_inst="1,5,9,13,17,21,25,29" pos="14">Attention from EQ_L3_FIR 1</bit>
+ <bit child_node="EQ_L3_FIR" node_inst="2,6,10,14,18,22,26,30" pos="15">Attention from EQ_L3_FIR 2</bit>
+ <bit child_node="EQ_L3_FIR" node_inst="3,7,11,15,19,23,27,31" pos="16">Attention from EQ_L3_FIR 3</bit>
+ <bit child_node="EQ_NCU_FIR" node_inst="0,4,8,12,16,20,24,28" pos="17">Attention from EQ_NCU_FIR 0</bit>
+ <bit child_node="EQ_NCU_FIR" node_inst="1,5,9,13,17,21,25,29" pos="18">Attention from EQ_NCU_FIR 1</bit>
+ <bit child_node="EQ_NCU_FIR" node_inst="2,6,10,14,18,22,26,30" pos="19">Attention from EQ_NCU_FIR 2</bit>
+ <bit child_node="EQ_NCU_FIR" node_inst="3,7,11,15,19,23,27,31" pos="20">Attention from EQ_NCU_FIR 3</bit>
+ <bit child_node="EQ_QME_FIR" node_inst="0,1,2,3,4,5,6,7" pos="21">Attention from EQ_QME_FIR</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="0,4,8,12,16,20,24,28" pos="5">Attention from EQ_CORE_FIR 0</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="1,5,9,13,17,21,25,29" pos="6">Attention from EQ_CORE_FIR 1</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="2,6,10,14,18,22,26,30" pos="7">Attention from EQ_CORE_FIR 2</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="3,7,11,15,19,23,27,31" pos="8">Attention from EQ_CORE_FIR 3</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_eq_ha.xml b/xml/p10/node_cfir_eq_ha.xml
index 23383ee..191ef0b 100644
--- a/xml/p10/node_cfir_eq_ha.xml
+++ b/xml/p10/node_cfir_eq_ha.xml
@@ -29,5 +29,5 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Local FIR</bit>
+ <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Attention from EQ_LOCAL_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_eq_re.xml b/xml/p10/node_cfir_eq_re.xml
index b60b24c..c74572e 100644
--- a/xml/p10/node_cfir_eq_re.xml
+++ b/xml/p10/node_cfir_eq_re.xml
@@ -30,22 +30,22 @@
</expr>
</rule>
<bit pos="2">recovery with any local checkstop</bit>
- <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Local FIR</bit>
- <bit child_node="EQ_L2_FIR" node_inst="0,4,8,12,16,20,24,28" pos="9">L2 FIR Register</bit>
- <bit child_node="EQ_L2_FIR" node_inst="1,5,9,13,17,21,25,29" pos="10">L2 FIR Register</bit>
- <bit child_node="EQ_L2_FIR" node_inst="2,6,10,14,18,22,26,30" pos="11">L2 FIR Register</bit>
- <bit child_node="EQ_L2_FIR" node_inst="3,7,11,15,19,23,27,31" pos="12">L2 FIR Register</bit>
- <bit child_node="EQ_L3_FIR" node_inst="0,4,8,12,16,20,24,28" pos="13">L3 FIR Register</bit>
- <bit child_node="EQ_L3_FIR" node_inst="1,5,9,13,17,21,25,29" pos="14">L3 FIR Register</bit>
- <bit child_node="EQ_L3_FIR" node_inst="2,6,10,14,18,22,26,30" pos="15">L3 FIR Register</bit>
- <bit child_node="EQ_L3_FIR" node_inst="3,7,11,15,19,23,27,31" pos="16">L3 FIR Register</bit>
- <bit child_node="EQ_NCU_FIR" node_inst="0,4,8,12,16,20,24,28" pos="17">NCU FIR Register</bit>
- <bit child_node="EQ_NCU_FIR" node_inst="1,5,9,13,17,21,25,29" pos="18">NCU FIR Register</bit>
- <bit child_node="EQ_NCU_FIR" node_inst="2,6,10,14,18,22,26,30" pos="19">NCU FIR Register</bit>
- <bit child_node="EQ_NCU_FIR" node_inst="3,7,11,15,19,23,27,31" pos="20">NCU FIR Register</bit>
- <bit child_node="EQ_QME_FIR" node_inst="0,1,2,3,4,5,6,7" pos="21">QME Local Fault Isolation Register</bit>
- <bit child_node="EQ_CORE_FIR" node_inst="0,4,8,12,16,20,24,28" pos="5">Core Fault Isolation Register</bit>
- <bit child_node="EQ_CORE_FIR" node_inst="1,5,9,13,17,21,25,29" pos="6">Core Fault Isolation Register</bit>
- <bit child_node="EQ_CORE_FIR" node_inst="2,6,10,14,18,22,26,30" pos="7">Core Fault Isolation Register</bit>
- <bit child_node="EQ_CORE_FIR" node_inst="3,7,11,15,19,23,27,31" pos="8">Core Fault Isolation Register</bit>
+ <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Attention from EQ_LOCAL_FIR</bit>
+ <bit child_node="EQ_L2_FIR" node_inst="0,4,8,12,16,20,24,28" pos="9">Attention from EQ_L2_FIR 0</bit>
+ <bit child_node="EQ_L2_FIR" node_inst="1,5,9,13,17,21,25,29" pos="10">Attention from EQ_L2_FIR 1</bit>
+ <bit child_node="EQ_L2_FIR" node_inst="2,6,10,14,18,22,26,30" pos="11">Attention from EQ_L2_FIR 2</bit>
+ <bit child_node="EQ_L2_FIR" node_inst="3,7,11,15,19,23,27,31" pos="12">Attention from EQ_L2_FIR 3</bit>
+ <bit child_node="EQ_L3_FIR" node_inst="0,4,8,12,16,20,24,28" pos="13">Attention from EQ_L3_FIR 0</bit>
+ <bit child_node="EQ_L3_FIR" node_inst="1,5,9,13,17,21,25,29" pos="14">Attention from EQ_L3_FIR 1</bit>
+ <bit child_node="EQ_L3_FIR" node_inst="2,6,10,14,18,22,26,30" pos="15">Attention from EQ_L3_FIR 2</bit>
+ <bit child_node="EQ_L3_FIR" node_inst="3,7,11,15,19,23,27,31" pos="16">Attention from EQ_L3_FIR 3</bit>
+ <bit child_node="EQ_NCU_FIR" node_inst="0,4,8,12,16,20,24,28" pos="17">Attention from EQ_NCU_FIR 0</bit>
+ <bit child_node="EQ_NCU_FIR" node_inst="1,5,9,13,17,21,25,29" pos="18">Attention from EQ_NCU_FIR 1</bit>
+ <bit child_node="EQ_NCU_FIR" node_inst="2,6,10,14,18,22,26,30" pos="19">Attention from EQ_NCU_FIR 2</bit>
+ <bit child_node="EQ_NCU_FIR" node_inst="3,7,11,15,19,23,27,31" pos="20">Attention from EQ_NCU_FIR 3</bit>
+ <bit child_node="EQ_QME_FIR" node_inst="0,1,2,3,4,5,6,7" pos="21">Attention from EQ_QME_FIR</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="0,4,8,12,16,20,24,28" pos="5">Attention from EQ_CORE_FIR 0</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="1,5,9,13,17,21,25,29" pos="6">Attention from EQ_CORE_FIR 1</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="2,6,10,14,18,22,26,30" pos="7">Attention from EQ_CORE_FIR 2</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="3,7,11,15,19,23,27,31" pos="8">Attention from EQ_CORE_FIR 3</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_eq_spa.xml b/xml/p10/node_cfir_eq_spa.xml
index 5d01d14..82dd599 100644
--- a/xml/p10/node_cfir_eq_spa.xml
+++ b/xml/p10/node_cfir_eq_spa.xml
@@ -29,7 +29,7 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Local FIR</bit>
+ <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Attention from EQ_LOCAL_FIR</bit>
<!-- NOTE: Attentions routed to this node from the EQ_SPATTN registers
depend if the cores are configured in Normal or Fused Core mode.
Therefore the core thread state must be queried first. -->
diff --git a/xml/p10/node_cfir_eq_ucs.xml b/xml/p10/node_cfir_eq_ucs.xml
index dc54940..4d7b433 100644
--- a/xml/p10/node_cfir_eq_ucs.xml
+++ b/xml/p10/node_cfir_eq_ucs.xml
@@ -29,9 +29,9 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Local FIR</bit>
- <bit child_node="EQ_CORE_FIR" node_inst="0,4,8,12,16,20,24,28" pos="5">Core Fault Isolation Register</bit>
- <bit child_node="EQ_CORE_FIR" node_inst="1,5,9,13,17,21,25,29" pos="6">Core Fault Isolation Register</bit>
- <bit child_node="EQ_CORE_FIR" node_inst="2,6,10,14,18,22,26,30" pos="7">Core Fault Isolation Register</bit>
- <bit child_node="EQ_CORE_FIR" node_inst="3,7,11,15,19,23,27,31" pos="8">Core Fault Isolation Register</bit>
+ <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Attention from EQ_LOCAL_FIR</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="0,4,8,12,16,20,24,28" pos="5">Attention from EQ_CORE_FIR 0</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="1,5,9,13,17,21,25,29" pos="6">Attention from EQ_CORE_FIR 1</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="2,6,10,14,18,22,26,30" pos="7">Attention from EQ_CORE_FIR 2</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="3,7,11,15,19,23,27,31" pos="8">Attention from EQ_CORE_FIR 3</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_iohs_cs_re_spa.xml b/xml/p10/node_cfir_iohs_cs_re_spa.xml
index 568188e..c785f92 100644
--- a/xml/p10/node_cfir_iohs_cs_re_spa.xml
+++ b/xml/p10/node_cfir_iohs_cs_re_spa.xml
@@ -87,6 +87,6 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="IOHS_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Local FIR</bit>
- <bit child_node="IOHS_DLP_FIR" node_inst="0,1,2,3,4,5,6,7" pos="5">PowerBus OLL FIR Register</bit>
+ <bit child_node="IOHS_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Attention from IOHS_LOCAL_FIR</bit>
+ <bit child_node="IOHS_DLP_FIR" node_inst="0,1,2,3,4,5,6,7" pos="5">Attention from IOHS_DLP_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_iohs_ucs_ha.xml b/xml/p10/node_cfir_iohs_ucs_ha.xml
index 9959a20..30140bc 100644
--- a/xml/p10/node_cfir_iohs_ucs_ha.xml
+++ b/xml/p10/node_cfir_iohs_ucs_ha.xml
@@ -58,5 +58,5 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="IOHS_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Local FIR</bit>
+ <bit child_node="IOHS_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Attention from IOHS_LOCAL_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_mc_cs_re_spa.xml b/xml/p10/node_cfir_mc_cs_re_spa.xml
index 0dd2c05..bb0c066 100644
--- a/xml/p10/node_cfir_mc_cs_re_spa.xml
+++ b/xml/p10/node_cfir_mc_cs_re_spa.xml
@@ -63,13 +63,13 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="MC_LOCAL_FIR" node_inst="0,1,2,3" pos="4">Local FIR</bit>
- <bit child_node="MC_DSTL_FIR" node_inst="0,2,4,6" pos="5">MC Fault Isolation Register (DSTLFIR)</bit>
- <bit child_node="MC_USTL_FIR" node_inst="0,2,4,6" pos="6">MC Fault Isolation Register (USTLFIR)</bit>
- <bit child_node="MC_DSTL_FIR" node_inst="1,3,5,7" pos="7">MC Fault Isolation Register (DSTLFIR)</bit>
- <bit child_node="MC_USTL_FIR" node_inst="1,3,5,7" pos="8">MC Fault Isolation Register (USTLFIR)</bit>
- <bit child_node="MC_FIR" node_inst="0,1,2,3" pos="9">MC Fault Isolation Register (MCFIR)</bit>
- <bit child_node="MC_MISC_FIR" node_inst="0,1,2,3" pos="10">MISC Fault Isolation Register</bit>
- <bit child_node="MC_OMI_DL_FIR" node_inst="0,2,4,6" pos="13">OMI-DL common FIR Register</bit>
- <bit child_node="MC_OMI_DL_FIR" node_inst="1,3,5,7" pos="14">OMI-DL common FIR Register</bit>
+ <bit child_node="MC_LOCAL_FIR" node_inst="0,1,2,3" pos="4">Attention from MC_LOCAL_FIR</bit>
+ <bit child_node="MC_DSTL_FIR" node_inst="0,2,4,6" pos="5">Attention from MC_DSTL_FIR 0</bit>
+ <bit child_node="MC_USTL_FIR" node_inst="0,2,4,6" pos="6">Attention from MC_USTL_FIR 0</bit>
+ <bit child_node="MC_DSTL_FIR" node_inst="1,3,5,7" pos="7">Attention from MC_DSTL_FIR 1</bit>
+ <bit child_node="MC_USTL_FIR" node_inst="1,3,5,7" pos="8">Attention from MC_USTL_FIR 1</bit>
+ <bit child_node="MC_FIR" node_inst="0,1,2,3" pos="9">Attention from MC_FIR</bit>
+ <bit child_node="MC_MISC_FIR" node_inst="0,1,2,3" pos="10">Attention from MC_MISC_FIR</bit>
+ <bit child_node="MC_OMI_DL_FIR" node_inst="0,2,4,6" pos="13">Attention from MC_OMI_DL_FIR 0</bit>
+ <bit child_node="MC_OMI_DL_FIR" node_inst="1,3,5,7" pos="14">Attention from MC_OMI_DL_FIR 1</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_mc_ucs_ha.xml b/xml/p10/node_cfir_mc_ucs_ha.xml
index 37c27ed..08207bf 100644
--- a/xml/p10/node_cfir_mc_ucs_ha.xml
+++ b/xml/p10/node_cfir_mc_ucs_ha.xml
@@ -42,11 +42,11 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="MC_LOCAL_FIR" node_inst="0,1,2,3" pos="4">Local FIR</bit>
- <bit child_node="MC_DSTL_FIR" node_inst="0,2,4,6" pos="5">MC Fault Isolation Register (DSTLFIR)</bit>
- <bit child_node="MC_USTL_FIR" node_inst="0,2,4,6" pos="6">MC Fault Isolation Register (USTLFIR)</bit>
- <bit child_node="MC_DSTL_FIR" node_inst="1,3,5,7" pos="7">MC Fault Isolation Register (DSTLFIR)</bit>
- <bit child_node="MC_USTL_FIR" node_inst="1,3,5,7" pos="8">MC Fault Isolation Register (USTLFIR)</bit>
- <bit child_node="MC_FIR" node_inst="0,1,2,3" pos="9">MC Fault Isolation Register (MCFIR)</bit>
- <bit child_node="MC_MISC_FIR" node_inst="0,1,2,3" pos="10">MISC Fault Isolation Register</bit>
+ <bit child_node="MC_LOCAL_FIR" node_inst="0,1,2,3" pos="4">Attention from MC_LOCAL_FIR</bit>
+ <bit child_node="MC_DSTL_FIR" node_inst="0,2,4,6" pos="5">Attention from MC_DSTL_FIR 0</bit>
+ <bit child_node="MC_USTL_FIR" node_inst="0,2,4,6" pos="6">Attention from MC_USTL_FIR 0</bit>
+ <bit child_node="MC_DSTL_FIR" node_inst="1,3,5,7" pos="7">Attention from MC_DSTL_FIR 1</bit>
+ <bit child_node="MC_USTL_FIR" node_inst="1,3,5,7" pos="8">Attention from MC_USTL_FIR 1</bit>
+ <bit child_node="MC_FIR" node_inst="0,1,2,3" pos="9">Attention from MC_FIR</bit>
+ <bit child_node="MC_MISC_FIR" node_inst="0,1,2,3" pos="10">Attention from MC_MISC_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_n0_cs_re.xml b/xml/p10/node_cfir_n0_cs_re.xml
index 845b897..7a24f09 100644
--- a/xml/p10/node_cfir_n0_cs_re.xml
+++ b/xml/p10/node_cfir_n0_cs_re.xml
@@ -30,14 +30,14 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="N0_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
- <bit child_node="NMMU_CQ_FIR" node_inst="0" pos="5">PBI CQ FIR Register</bit>
- <bit child_node="NMMU_FIR" node_inst="0" pos="6">NMMU FIR1 Register</bit>
- <bit child_node="INT_CQ_FIR" node_inst="0" pos="7">Primary Error Register for INT_CQ. This contains all of the individual errors detected by INT_CQ, plus summary error indicators from VC and PC (see bits 43:63).</bit>
- <bit child_node="VAS_FIR" node_inst="0" pos="8">Local FIR register for the VAS unit logic</bit>
- <bit child_node="NX_DMA_ENG_FIR" node_inst="0" pos="9">DMA and Engine Fault Isolation Register</bit>
- <bit child_node="NX_CQ_FIR" node_inst="0" pos="10">PBI CQ FIR Register</bit>
- <bit child_node="PCI_NEST_FIR" node_inst="3" pos="13">PCI Nest FIR Register</bit>
- <bit child_node="PCI_NEST_FIR" node_inst="4" pos="14">PCI Nest FIR Register</bit>
- <bit child_node="PCI_NEST_FIR" node_inst="5" pos="15">PCI Nest FIR Register</bit>
+ <bit child_node="N0_LOCAL_FIR" node_inst="0" pos="4">Attention from N0_LOCAL_FIR</bit>
+ <bit child_node="NMMU_CQ_FIR" node_inst="0" pos="5">Attention from NMMU_CQ_FIR 0</bit>
+ <bit child_node="NMMU_FIR" node_inst="0" pos="6">Attention from NMMU_FIR 0</bit>
+ <bit child_node="INT_CQ_FIR" node_inst="0" pos="7">Attention from INT_CQ_FIR</bit>
+ <bit child_node="VAS_FIR" node_inst="0" pos="8">Attention from VAS_FIR</bit>
+ <bit child_node="NX_DMA_ENG_FIR" node_inst="0" pos="9">Attention from NX_DMA_ENG_FIR</bit>
+ <bit child_node="NX_CQ_FIR" node_inst="0" pos="10">Attention from NX_CQ_FIR</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="3" pos="13">Attention from PCI_NEST_FIR 3</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="4" pos="14">Attention from PCI_NEST_FIR 4</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="5" pos="15">Attention from PCI_NEST_FIR 5</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_n0_ha.xml b/xml/p10/node_cfir_n0_ha.xml
index f912397..c4d660a 100644
--- a/xml/p10/node_cfir_n0_ha.xml
+++ b/xml/p10/node_cfir_n0_ha.xml
@@ -15,5 +15,5 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="N0_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
+ <bit child_node="N0_LOCAL_FIR" node_inst="0" pos="4">Attention from N0_LOCAL_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_n0_spa.xml b/xml/p10/node_cfir_n0_spa.xml
index 63aa866..e32ae1a 100644
--- a/xml/p10/node_cfir_n0_spa.xml
+++ b/xml/p10/node_cfir_n0_spa.xml
@@ -15,6 +15,6 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="N0_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
- <bit child_node="INT_CQ_FIR" node_inst="0" pos="7">Primary Error Register for INT_CQ. This contains all of the individual errors detected by INT_CQ, plus summary error indicators from VC and PC (see bits 43:63).</bit>
+ <bit child_node="N0_LOCAL_FIR" node_inst="0" pos="4">Attention from N0_LOCAL_FIR</bit>
+ <bit child_node="INT_CQ_FIR" node_inst="0" pos="7">Attention from INT_CQ_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_n0_ucs.xml b/xml/p10/node_cfir_n0_ucs.xml
index 93c5b18..72c2005 100644
--- a/xml/p10/node_cfir_n0_ucs.xml
+++ b/xml/p10/node_cfir_n0_ucs.xml
@@ -15,10 +15,10 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="N0_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
- <bit child_node="NMMU_CQ_FIR" node_inst="0" pos="5">PBI CQ FIR Register</bit>
- <bit child_node="NMMU_FIR" node_inst="0" pos="6">NMMU FIR1 Register</bit>
- <bit child_node="VAS_FIR" node_inst="0" pos="8">Local FIR register for the VAS unit logic</bit>
- <bit child_node="NX_DMA_ENG_FIR" node_inst="0" pos="9">DMA and Engine Fault Isolation Register</bit>
- <bit child_node="NX_CQ_FIR" node_inst="0" pos="10">PBI CQ FIR Register</bit>
+ <bit child_node="N0_LOCAL_FIR" node_inst="0" pos="4">Attention from N0_LOCAL_FIR</bit>
+ <bit child_node="NMMU_CQ_FIR" node_inst="0" pos="5">Attention from NMMU_CQ_FIR 0</bit>
+ <bit child_node="NMMU_FIR" node_inst="0" pos="6">Attention from NMMU_FIR 0</bit>
+ <bit child_node="VAS_FIR" node_inst="0" pos="8">Attention from VAS_FIR</bit>
+ <bit child_node="NX_DMA_ENG_FIR" node_inst="0" pos="9">Attention from NX_DMA_ENG_FIR</bit>
+ <bit child_node="NX_CQ_FIR" node_inst="0" pos="10">Attention from NX_CQ_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_n1_cs.xml b/xml/p10/node_cfir_n1_cs.xml
index 253bb52..763fd79 100644
--- a/xml/p10/node_cfir_n1_cs.xml
+++ b/xml/p10/node_cfir_n1_cs.xml
@@ -15,32 +15,32 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="N1_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
- <bit child_node="NMMU_CQ_FIR" node_inst="1" pos="5">PBI CQ FIR Register</bit>
- <bit child_node="NMMU_FIR" node_inst="1" pos="6">NMMU FIR1 Register</bit>
- <bit child_node="MCD_FIR" node_inst="0" pos="7">Local FIR register for MCD</bit>
- <bit child_node="HCA_FIR" node_inst="0" pos="9">HCA Fault Isolation Register</bit>
- <bit child_node="LPC_FIR" node_inst="0" pos="11">PBAM low sped part FIR Register</bit>
- <bit child_node="PCI_NEST_FIR" node_inst="0" pos="13">PCI Nest FIR Register</bit>
- <bit child_node="PCI_NEST_FIR" node_inst="1" pos="14">PCI Nest FIR Register</bit>
- <bit child_node="PCI_NEST_FIR" node_inst="2" pos="15">PCI Nest FIR Register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="0" pos="17">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="1" pos="18">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="2" pos="19">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="3" pos="20">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="4" pos="21">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="5" pos="22">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="6" pos="23">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="7" pos="24">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EN1" node_inst="0" pos="25">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EN2" node_inst="0" pos="26">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EN3" node_inst="0" pos="27">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EN4" node_inst="0" pos="28">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_ES1" node_inst="0" pos="29">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_ES2" node_inst="0" pos="30">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_ES3" node_inst="0" pos="31">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_ES4" node_inst="0" pos="32">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_EXT_FIR" node_inst="0" pos="33">PowerBus EH EXTFIR register</bit>
- <bit child_node="PSIHB_FIR" node_inst="0" pos="38">PSI Host Bridge FIR Register</bit>
- <bit child_node="PBAF_FIR" node_inst="0" pos="39">PBA Local Fault Isolation Register. Register bits are set for any error condition detected by the PBA. The PBAFIR will freeze upon logging the first error not masked in PBAFIRMASK.</bit>
+ <bit child_node="N1_LOCAL_FIR" node_inst="0" pos="4">Attention from N1_LOCAL_FIR</bit>
+ <bit child_node="NMMU_CQ_FIR" node_inst="1" pos="5">Attention from NMMU_CQ_FIR 1</bit>
+ <bit child_node="NMMU_FIR" node_inst="1" pos="6">Attention from NMMU_FIR 1</bit>
+ <bit child_node="MCD_FIR" node_inst="0" pos="7">Attention from MCD_FIR</bit>
+ <bit child_node="HCA_FIR" node_inst="0" pos="9">Attention from HCA_FIR</bit>
+ <bit child_node="LPC_FIR" node_inst="0" pos="11">Attention from LPC_FIR</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="0" pos="13">Attention from PCI_NEST_FIR 0</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="1" pos="14">Attention from PCI_NEST_FIR 1</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="2" pos="15">Attention from PCI_NEST_FIR 2</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="0" pos="17">Attention from PB_STATION_FIR_EQ 0</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="1" pos="18">Attention from PB_STATION_FIR_EQ 1</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="2" pos="19">Attention from PB_STATION_FIR_EQ 2</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="3" pos="20">Attention from PB_STATION_FIR_EQ 3</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="4" pos="21">Attention from PB_STATION_FIR_EQ 4</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="5" pos="22">Attention from PB_STATION_FIR_EQ 5</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="6" pos="23">Attention from PB_STATION_FIR_EQ 6</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="7" pos="24">Attention from PB_STATION_FIR_EQ 7</bit>
+ <bit child_node="PB_STATION_FIR_EN1" node_inst="0" pos="25">Attention from PB_STATION_FIR_EN1</bit>
+ <bit child_node="PB_STATION_FIR_EN2" node_inst="0" pos="26">Attention from PB_STATION_FIR_EN2</bit>
+ <bit child_node="PB_STATION_FIR_EN3" node_inst="0" pos="27">Attention from PB_STATION_FIR_EN3</bit>
+ <bit child_node="PB_STATION_FIR_EN4" node_inst="0" pos="28">Attention from PB_STATION_FIR_EN4</bit>
+ <bit child_node="PB_STATION_FIR_ES1" node_inst="0" pos="29">Attention from PB_STATION_FIR_ES1</bit>
+ <bit child_node="PB_STATION_FIR_ES2" node_inst="0" pos="30">Attention from PB_STATION_FIR_ES2</bit>
+ <bit child_node="PB_STATION_FIR_ES3" node_inst="0" pos="31">Attention from PB_STATION_FIR_ES3</bit>
+ <bit child_node="PB_STATION_FIR_ES4" node_inst="0" pos="32">Attention from PB_STATION_FIR_ES4</bit>
+ <bit child_node="PB_EXT_FIR" node_inst="0" pos="33">Attention from PB_EXT_FIR</bit>
+ <bit child_node="PSIHB_FIR" node_inst="0" pos="38">Attention from PSIHB_FIR</bit>
+ <bit child_node="PBAF_FIR" node_inst="0" pos="39">Attention from PBAF_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_n1_ha.xml b/xml/p10/node_cfir_n1_ha.xml
index 09b2150..8a99cc4 100644
--- a/xml/p10/node_cfir_n1_ha.xml
+++ b/xml/p10/node_cfir_n1_ha.xml
@@ -15,5 +15,5 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="N1_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
+ <bit child_node="N1_LOCAL_FIR" node_inst="0" pos="4">Attention from N1_LOCAL_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_n1_re.xml b/xml/p10/node_cfir_n1_re.xml
index 6e8d74a..0f7c996 100644
--- a/xml/p10/node_cfir_n1_re.xml
+++ b/xml/p10/node_cfir_n1_re.xml
@@ -15,31 +15,31 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="N1_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
- <bit child_node="NMMU_CQ_FIR" node_inst="1" pos="5">PBI CQ FIR Register</bit>
- <bit child_node="NMMU_FIR" node_inst="1" pos="6">NMMU FIR1 Register</bit>
- <bit child_node="MCD_FIR" node_inst="0" pos="7">Local FIR register for MCD</bit>
- <bit child_node="HCA_FIR" node_inst="0" pos="9">HCA Fault Isolation Register</bit>
- <bit child_node="LPC_FIR" node_inst="0" pos="11">PBAM low sped part FIR Register</bit>
- <bit child_node="PCI_NEST_FIR" node_inst="0" pos="13">PCI Nest FIR Register</bit>
- <bit child_node="PCI_NEST_FIR" node_inst="1" pos="14">PCI Nest FIR Register</bit>
- <bit child_node="PCI_NEST_FIR" node_inst="2" pos="15">PCI Nest FIR Register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="0" pos="17">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="1" pos="18">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="2" pos="19">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="3" pos="20">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="4" pos="21">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="5" pos="22">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="6" pos="23">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="7" pos="24">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EN1" node_inst="0" pos="25">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EN2" node_inst="0" pos="26">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EN3" node_inst="0" pos="27">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EN4" node_inst="0" pos="28">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_ES1" node_inst="0" pos="29">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_ES2" node_inst="0" pos="30">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_ES3" node_inst="0" pos="31">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_ES4" node_inst="0" pos="32">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PSIHB_FIR" node_inst="0" pos="38">PSI Host Bridge FIR Register</bit>
- <bit child_node="PBAF_FIR" node_inst="0" pos="39">PBA Local Fault Isolation Register. Register bits are set for any error condition detected by the PBA. The PBAFIR will freeze upon logging the first error not masked in PBAFIRMASK.</bit>
+ <bit child_node="N1_LOCAL_FIR" node_inst="0" pos="4">Attention from N1_LOCAL_FIR</bit>
+ <bit child_node="NMMU_CQ_FIR" node_inst="1" pos="5">Attention from NMMU_CQ_FIR 1</bit>
+ <bit child_node="NMMU_FIR" node_inst="1" pos="6">Attention from NMMU_FIR 1</bit>
+ <bit child_node="MCD_FIR" node_inst="0" pos="7">Attention from MCD_FIR</bit>
+ <bit child_node="HCA_FIR" node_inst="0" pos="9">Attention from HCA_FIR</bit>
+ <bit child_node="LPC_FIR" node_inst="0" pos="11">Attention from LPC_FIR</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="0" pos="13">Attention from PCI_NEST_FIR 0</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="1" pos="14">Attention from PCI_NEST_FIR 1</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="2" pos="15">Attention from PCI_NEST_FIR 2</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="0" pos="17">Attention from PB_STATION_FIR_EQ 0</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="1" pos="18">Attention from PB_STATION_FIR_EQ 1</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="2" pos="19">Attention from PB_STATION_FIR_EQ 2</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="3" pos="20">Attention from PB_STATION_FIR_EQ 3</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="4" pos="21">Attention from PB_STATION_FIR_EQ 4</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="5" pos="22">Attention from PB_STATION_FIR_EQ 5</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="6" pos="23">Attention from PB_STATION_FIR_EQ 6</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="7" pos="24">Attention from PB_STATION_FIR_EQ 7</bit>
+ <bit child_node="PB_STATION_FIR_EN1" node_inst="0" pos="25">Attention from PB_STATION_FIR_EN1</bit>
+ <bit child_node="PB_STATION_FIR_EN2" node_inst="0" pos="26">Attention from PB_STATION_FIR_EN2</bit>
+ <bit child_node="PB_STATION_FIR_EN3" node_inst="0" pos="27">Attention from PB_STATION_FIR_EN3</bit>
+ <bit child_node="PB_STATION_FIR_EN4" node_inst="0" pos="28">Attention from PB_STATION_FIR_EN4</bit>
+ <bit child_node="PB_STATION_FIR_ES1" node_inst="0" pos="29">Attention from PB_STATION_FIR_ES1</bit>
+ <bit child_node="PB_STATION_FIR_ES2" node_inst="0" pos="30">Attention from PB_STATION_FIR_ES2</bit>
+ <bit child_node="PB_STATION_FIR_ES3" node_inst="0" pos="31">Attention from PB_STATION_FIR_ES3</bit>
+ <bit child_node="PB_STATION_FIR_ES4" node_inst="0" pos="32">Attention from PB_STATION_FIR_ES4</bit>
+ <bit child_node="PSIHB_FIR" node_inst="0" pos="38">Attention from PSIHB_FIR</bit>
+ <bit child_node="PBAF_FIR" node_inst="0" pos="39">Attention from PBAF_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_n1_spa.xml b/xml/p10/node_cfir_n1_spa.xml
index 97dfd93..74d6ec0 100644
--- a/xml/p10/node_cfir_n1_spa.xml
+++ b/xml/p10/node_cfir_n1_spa.xml
@@ -15,22 +15,22 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="N1_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
- <bit child_node="MCD_FIR" node_inst="0" pos="7">Local FIR register for MCD</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="0" pos="17">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="1" pos="18">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="2" pos="19">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="3" pos="20">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="4" pos="21">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="5" pos="22">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="6" pos="23">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EQ" node_inst="7" pos="24">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EN1" node_inst="0" pos="25">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EN2" node_inst="0" pos="26">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EN3" node_inst="0" pos="27">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_EN4" node_inst="0" pos="28">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_ES1" node_inst="0" pos="29">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_ES2" node_inst="0" pos="30">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_ES3" node_inst="0" pos="31">PowerBus PB RaceTrack Station nest domain FIR register</bit>
- <bit child_node="PB_STATION_FIR_ES4" node_inst="0" pos="32">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="N1_LOCAL_FIR" node_inst="0" pos="4">Attention from N1_LOCAL_FIR</bit>
+ <bit child_node="MCD_FIR" node_inst="0" pos="7">Attention from MCD_FIR</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="0" pos="17">Attention from PB_STATION_FIR_EQ 0</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="1" pos="18">Attention from PB_STATION_FIR_EQ 1</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="2" pos="19">Attention from PB_STATION_FIR_EQ 2</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="3" pos="20">Attention from PB_STATION_FIR_EQ 3</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="4" pos="21">Attention from PB_STATION_FIR_EQ 4</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="5" pos="22">Attention from PB_STATION_FIR_EQ 5</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="6" pos="23">Attention from PB_STATION_FIR_EQ 6</bit>
+ <bit child_node="PB_STATION_FIR_EQ" node_inst="7" pos="24">Attention from PB_STATION_FIR_EQ 7</bit>
+ <bit child_node="PB_STATION_FIR_EN1" node_inst="0" pos="25">Attention from PB_STATION_FIR_EN1</bit>
+ <bit child_node="PB_STATION_FIR_EN2" node_inst="0" pos="26">Attention from PB_STATION_FIR_EN2</bit>
+ <bit child_node="PB_STATION_FIR_EN3" node_inst="0" pos="27">Attention from PB_STATION_FIR_EN3</bit>
+ <bit child_node="PB_STATION_FIR_EN4" node_inst="0" pos="28">Attention from PB_STATION_FIR_EN4</bit>
+ <bit child_node="PB_STATION_FIR_ES1" node_inst="0" pos="29">Attention from PB_STATION_FIR_ES1</bit>
+ <bit child_node="PB_STATION_FIR_ES2" node_inst="0" pos="30">Attention from PB_STATION_FIR_ES2</bit>
+ <bit child_node="PB_STATION_FIR_ES3" node_inst="0" pos="31">Attention from PB_STATION_FIR_ES3</bit>
+ <bit child_node="PB_STATION_FIR_ES4" node_inst="0" pos="32">Attention from PB_STATION_FIR_ES4</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_n1_ucs.xml b/xml/p10/node_cfir_n1_ucs.xml
index 4a57ccf..51b877e 100644
--- a/xml/p10/node_cfir_n1_ucs.xml
+++ b/xml/p10/node_cfir_n1_ucs.xml
@@ -15,7 +15,7 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="N1_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
- <bit child_node="NMMU_CQ_FIR" node_inst="1" pos="5">PBI CQ FIR Register</bit>
- <bit child_node="NMMU_FIR" node_inst="1" pos="6">NMMU FIR1 Register</bit>
+ <bit child_node="N1_LOCAL_FIR" node_inst="0" pos="4">Attention from N1_LOCAL_FIR</bit>
+ <bit child_node="NMMU_CQ_FIR" node_inst="1" pos="5">Attention from NMMU_CQ_FIR 1</bit>
+ <bit child_node="NMMU_FIR" node_inst="1" pos="6">Attention from NMMU_FIR 1</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_paue_cs_re.xml b/xml/p10/node_cfir_paue_cs_re.xml
index 81967a2..11c8e20 100644
--- a/xml/p10/node_cfir_paue_cs_re.xml
+++ b/xml/p10/node_cfir_paue_cs_re.xml
@@ -34,10 +34,10 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
- <bit child_node="PAU_FIR_0" node_inst="0,3" pos="5">Local FIR register for the PAU (1 of 3)</bit>
- <bit child_node="PAU_FIR_1" node_inst="0,3" pos="6">Local FIR register for the PAU (2 of 3)</bit>
- <bit child_node="PAU_FIR_2" node_inst="0,3" pos="7">Local FIR register for the PAU (3 of 3)</bit>
- <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Local FIR register for the chip pervasive logic</bit>
- <bit child_node="PAU_PTL_FIR" node_inst="0,1" pos="16"/>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Attention from PAU_LOCAL_FIR</bit>
+ <bit child_node="PAU_FIR_0" node_inst="0,3" pos="5">Attention from PAU_FIR_0</bit>
+ <bit child_node="PAU_FIR_1" node_inst="0,3" pos="6">Attention from PAU_FIR_1</bit>
+ <bit child_node="PAU_FIR_2" node_inst="0,3" pos="7">Attention from PAU_FIR_2</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Attention from PAU_PHY_FIR</bit>
+ <bit child_node="PAU_PTL_FIR" node_inst="0,1" pos="16">Attention from PAU_PTL_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_paue_cs_re_p10_10.xml b/xml/p10/node_cfir_paue_cs_re_p10_10.xml
index a1bcb5a..e38b1ba 100644
--- a/xml/p10/node_cfir_paue_cs_re_p10_10.xml
+++ b/xml/p10/node_cfir_paue_cs_re_p10_10.xml
@@ -34,11 +34,11 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
- <bit child_node="PAU_FIR_0" node_inst="0,3" pos="5">Local FIR register for the PAU (1 of 3)</bit>
- <bit child_node="PAU_FIR_1" node_inst="0,3" pos="6">Local FIR register for the PAU (2 of 3)</bit>
- <bit child_node="PAU_FIR_2" node_inst="0,3" pos="7">Local FIR register for the PAU (3 of 3)</bit>
- <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Local FIR register for the chip pervasive logic</bit>
- <bit child_node="PAU_DL_FIR" node_inst="0,1" pos="14">Local FIR register for the chip pervasive logic</bit>
- <bit child_node="PAU_PTL_FIR" node_inst="0,1" pos="16"/>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Attention from PAU_LOCAL_FIR</bit>
+ <bit child_node="PAU_FIR_0" node_inst="0,3" pos="5">Attention from PAU_FIR_0</bit>
+ <bit child_node="PAU_FIR_1" node_inst="0,3" pos="6">Attention from PAU_FIR_1</bit>
+ <bit child_node="PAU_FIR_2" node_inst="0,3" pos="7">Attention from PAU_FIR_2</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Attention from PAU_PHY_FIR</bit>
+ <bit child_node="PAU_DL_FIR" node_inst="0,1" pos="14">Attention from PAU_DL_FIR</bit>
+ <bit child_node="PAU_PTL_FIR" node_inst="0,1" pos="16">Attention from PAU_PTL_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_paue_ha.xml b/xml/p10/node_cfir_paue_ha.xml
index 089d3c4..8369ab0 100644
--- a/xml/p10/node_cfir_paue_ha.xml
+++ b/xml/p10/node_cfir_paue_ha.xml
@@ -17,5 +17,5 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Attention from PAU_LOCAL_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_paue_spa.xml b/xml/p10/node_cfir_paue_spa.xml
index 71c2552..47b5c7b 100644
--- a/xml/p10/node_cfir_paue_spa.xml
+++ b/xml/p10/node_cfir_paue_spa.xml
@@ -17,7 +17,7 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
- <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Local FIR register for the chip pervasive logic</bit>
- <bit child_node="PAU_PTL_FIR" node_inst="0,1" pos="16"/>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Attention from PAU_LOCAL_FIR</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Attention from PAU_PHY_FIR</bit>
+ <bit child_node="PAU_PTL_FIR" node_inst="0,1" pos="16">Attention from PAU_PTL_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_paue_spa_p10_10.xml b/xml/p10/node_cfir_paue_spa_p10_10.xml
index b173b23..c8ded86 100644
--- a/xml/p10/node_cfir_paue_spa_p10_10.xml
+++ b/xml/p10/node_cfir_paue_spa_p10_10.xml
@@ -17,8 +17,8 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
- <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Local FIR register for the chip pervasive logic</bit>
- <bit child_node="PAU_DL_FIR" node_inst="0,1" pos="14">Local FIR register for the chip pervasive logic</bit>
- <bit child_node="PAU_PTL_FIR" node_inst="0,1" pos="16"/>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Attention from PAU_LOCAL_FIR</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Attention from PAU_PHY_FIR</bit>
+ <bit child_node="PAU_DL_FIR" node_inst="0,1" pos="14">Attention from PAU_DL_FIR</bit>
+ <bit child_node="PAU_PTL_FIR" node_inst="0,1" pos="16">Attention from PAU_PTL_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_paue_ucs.xml b/xml/p10/node_cfir_paue_ucs.xml
index 9f31ee3..c64d46b 100644
--- a/xml/p10/node_cfir_paue_ucs.xml
+++ b/xml/p10/node_cfir_paue_ucs.xml
@@ -17,9 +17,9 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
- <bit child_node="PAU_FIR_0" node_inst="0,3" pos="5">Local FIR register for the PAU (1 of 3)</bit>
- <bit child_node="PAU_FIR_1" node_inst="0,3" pos="6">Local FIR register for the PAU (2 of 3)</bit>
- <bit child_node="PAU_FIR_2" node_inst="0,3" pos="7">Local FIR register for the PAU (3 of 3)</bit>
- <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Local FIR register for the chip pervasive logic</bit>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Attention from PAU_LOCAL_FIR</bit>
+ <bit child_node="PAU_FIR_0" node_inst="0,3" pos="5">Attention from PAU_FIR_0</bit>
+ <bit child_node="PAU_FIR_1" node_inst="0,3" pos="6">Attention from PAU_FIR_1</bit>
+ <bit child_node="PAU_FIR_2" node_inst="0,3" pos="7">Attention from PAU_FIR_2</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Attention from PAU_PHY_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_paue_ucs_p10_10.xml b/xml/p10/node_cfir_paue_ucs_p10_10.xml
index efac4df..07b4d32 100644
--- a/xml/p10/node_cfir_paue_ucs_p10_10.xml
+++ b/xml/p10/node_cfir_paue_ucs_p10_10.xml
@@ -17,10 +17,10 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
- <bit child_node="PAU_FIR_0" node_inst="0,3" pos="5">Local FIR register for the PAU (1 of 3)</bit>
- <bit child_node="PAU_FIR_1" node_inst="0,3" pos="6">Local FIR register for the PAU (2 of 3)</bit>
- <bit child_node="PAU_FIR_2" node_inst="0,3" pos="7">Local FIR register for the PAU (3 of 3)</bit>
- <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Local FIR register for the chip pervasive logic</bit>
- <bit child_node="PAU_DL_FIR" node_inst="0,1" pos="14">Local FIR register for the chip pervasive logic</bit>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Attention from PAU_LOCAL_FIR</bit>
+ <bit child_node="PAU_FIR_0" node_inst="0,3" pos="5">Attention from PAU_FIR_0</bit>
+ <bit child_node="PAU_FIR_1" node_inst="0,3" pos="6">Attention from PAU_FIR_1</bit>
+ <bit child_node="PAU_FIR_2" node_inst="0,3" pos="7">Attention from PAU_FIR_2</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Attention from PAU_PHY_FIR</bit>
+ <bit child_node="PAU_DL_FIR" node_inst="0,1" pos="14">Attention from PAU_DL_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_pauw_cs_re.xml b/xml/p10/node_cfir_pauw_cs_re.xml
index 2ab3794..b3a455b 100644
--- a/xml/p10/node_cfir_pauw_cs_re.xml
+++ b/xml/p10/node_cfir_pauw_cs_re.xml
@@ -34,13 +34,13 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Local FIR</bit>
- <bit child_node="PAU_FIR_0" node_inst="4,6" pos="5">Local FIR register for the PAU (1 of 3)</bit>
- <bit child_node="PAU_FIR_1" node_inst="4,6" pos="6">Local FIR register for the PAU (2 of 3)</bit>
- <bit child_node="PAU_FIR_2" node_inst="4,6" pos="7">Local FIR register for the PAU (3 of 3)</bit>
- <bit child_node="PAU_FIR_0" node_inst="5,7" pos="9">Local FIR register for the PAU (1 of 3)</bit>
- <bit child_node="PAU_FIR_1" node_inst="5,7" pos="10">Local FIR register for the PAU (2 of 3)</bit>
- <bit child_node="PAU_FIR_2" node_inst="5,7" pos="11">Local FIR register for the PAU (3 of 3)</bit>
- <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Local FIR register for the chip pervasive logic</bit>
- <bit child_node="PAU_PTL_FIR" node_inst="2,3" pos="16"/>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Attention from PAU_LOCAL_FIR</bit>
+ <bit child_node="PAU_FIR_0" node_inst="4,6" pos="5">Attention from PAU_FIR_0</bit>
+ <bit child_node="PAU_FIR_1" node_inst="4,6" pos="6">Attention from PAU_FIR_1</bit>
+ <bit child_node="PAU_FIR_2" node_inst="4,6" pos="7">Attention from PAU_FIR_2</bit>
+ <bit child_node="PAU_FIR_0" node_inst="5,7" pos="9">Attention from PAU_FIR_0</bit>
+ <bit child_node="PAU_FIR_1" node_inst="5,7" pos="10">Attention from PAU_FIR_1</bit>
+ <bit child_node="PAU_FIR_2" node_inst="5,7" pos="11">Attention from PAU_FIR_2</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Attention from PAU_PHY_FIR</bit>
+ <bit child_node="PAU_PTL_FIR" node_inst="2,3" pos="16">Attention from PAU_PTL_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_pauw_cs_re_p10_10.xml b/xml/p10/node_cfir_pauw_cs_re_p10_10.xml
index 73a16cb..bc4d308 100644
--- a/xml/p10/node_cfir_pauw_cs_re_p10_10.xml
+++ b/xml/p10/node_cfir_pauw_cs_re_p10_10.xml
@@ -34,14 +34,14 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Local FIR</bit>
- <bit child_node="PAU_FIR_0" node_inst="4,6" pos="5">Local FIR register for the PAU (1 of 3)</bit>
- <bit child_node="PAU_FIR_1" node_inst="4,6" pos="6">Local FIR register for the PAU (2 of 3)</bit>
- <bit child_node="PAU_FIR_2" node_inst="4,6" pos="7">Local FIR register for the PAU (3 of 3)</bit>
- <bit child_node="PAU_FIR_0" node_inst="5,7" pos="9">Local FIR register for the PAU (1 of 3)</bit>
- <bit child_node="PAU_FIR_1" node_inst="5,7" pos="10">Local FIR register for the PAU (2 of 3)</bit>
- <bit child_node="PAU_FIR_2" node_inst="5,7" pos="11">Local FIR register for the PAU (3 of 3)</bit>
- <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Local FIR register for the chip pervasive logic</bit>
- <bit child_node="PAU_DL_FIR" node_inst="2,3" pos="14">Local FIR register for the chip pervasive logic</bit>
- <bit child_node="PAU_PTL_FIR" node_inst="2,3" pos="16"/>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Attention from PAU_LOCAL_FIR</bit>
+ <bit child_node="PAU_FIR_0" node_inst="4,6" pos="5">Attention from PAU_FIR_0</bit>
+ <bit child_node="PAU_FIR_1" node_inst="4,6" pos="6">Attention from PAU_FIR_1</bit>
+ <bit child_node="PAU_FIR_2" node_inst="4,6" pos="7">Attention from PAU_FIR_2</bit>
+ <bit child_node="PAU_FIR_0" node_inst="5,7" pos="9">Attention from PAU_FIR_0</bit>
+ <bit child_node="PAU_FIR_1" node_inst="5,7" pos="10">Attention from PAU_FIR_1</bit>
+ <bit child_node="PAU_FIR_2" node_inst="5,7" pos="11">Attention from PAU_FIR_2</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Attention from PAU_PHY_FIR</bit>
+ <bit child_node="PAU_DL_FIR" node_inst="2,3" pos="14">Attention from PAU_DL_FIR</bit>
+ <bit child_node="PAU_PTL_FIR" node_inst="2,3" pos="16">Attention from PAU_PTL_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_pauw_ha.xml b/xml/p10/node_cfir_pauw_ha.xml
index bd7ac57..79242c7 100644
--- a/xml/p10/node_cfir_pauw_ha.xml
+++ b/xml/p10/node_cfir_pauw_ha.xml
@@ -17,5 +17,5 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Local FIR</bit>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Attention from PAU_LOCAL_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_pauw_spa.xml b/xml/p10/node_cfir_pauw_spa.xml
index 3075b4d..a4f09c9 100644
--- a/xml/p10/node_cfir_pauw_spa.xml
+++ b/xml/p10/node_cfir_pauw_spa.xml
@@ -17,7 +17,7 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Local FIR</bit>
- <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Local FIR register for the chip pervasive logic</bit>
- <bit child_node="PAU_PTL_FIR" node_inst="2,3" pos="16"/>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Attention from PAU_LOCAL_FIR</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Attention from PAU_PHY_FIR</bit>
+ <bit child_node="PAU_PTL_FIR" node_inst="2,3" pos="16">Attention from PAU_PTL_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_pauw_spa_p10_10.xml b/xml/p10/node_cfir_pauw_spa_p10_10.xml
index 95df6ad..c2e2c4e 100644
--- a/xml/p10/node_cfir_pauw_spa_p10_10.xml
+++ b/xml/p10/node_cfir_pauw_spa_p10_10.xml
@@ -17,8 +17,8 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Local FIR</bit>
- <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Local FIR register for the chip pervasive logic</bit>
- <bit child_node="PAU_DL_FIR" node_inst="2,3" pos="14">Local FIR register for the chip pervasive logic</bit>
- <bit child_node="PAU_PTL_FIR" node_inst="2,3" pos="16"/>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Attention from PAU_LOCAL_FIR</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Attention from PAU_PHY_FIR</bit>
+ <bit child_node="PAU_DL_FIR" node_inst="2,3" pos="14">Attention from PAU_DL_FIR</bit>
+ <bit child_node="PAU_PTL_FIR" node_inst="2,3" pos="16">Attention from PAU_PTL_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_pauw_ucs.xml b/xml/p10/node_cfir_pauw_ucs.xml
index 87fab96..e62c3dd 100644
--- a/xml/p10/node_cfir_pauw_ucs.xml
+++ b/xml/p10/node_cfir_pauw_ucs.xml
@@ -17,12 +17,12 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Local FIR</bit>
- <bit child_node="PAU_FIR_0" node_inst="4,6" pos="5">Local FIR register for the PAU (1 of 3)</bit>
- <bit child_node="PAU_FIR_1" node_inst="4,6" pos="6">Local FIR register for the PAU (2 of 3)</bit>
- <bit child_node="PAU_FIR_2" node_inst="4,6" pos="7">Local FIR register for the PAU (3 of 3)</bit>
- <bit child_node="PAU_FIR_0" node_inst="5,7" pos="9">Local FIR register for the PAU (1 of 3)</bit>
- <bit child_node="PAU_FIR_1" node_inst="5,7" pos="10">Local FIR register for the PAU (2 of 3)</bit>
- <bit child_node="PAU_FIR_2" node_inst="5,7" pos="11">Local FIR register for the PAU (3 of 3)</bit>
- <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Local FIR register for the chip pervasive logic</bit>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Attention from PAU_LOCAL_FIR</bit>
+ <bit child_node="PAU_FIR_0" node_inst="4,6" pos="5">Attention from PAU_FIR_0</bit>
+ <bit child_node="PAU_FIR_1" node_inst="4,6" pos="6">Attention from PAU_FIR_1</bit>
+ <bit child_node="PAU_FIR_2" node_inst="4,6" pos="7">Attention from PAU_FIR_2</bit>
+ <bit child_node="PAU_FIR_0" node_inst="5,7" pos="9">Attention from PAU_FIR_0</bit>
+ <bit child_node="PAU_FIR_1" node_inst="5,7" pos="10">Attention from PAU_FIR_1</bit>
+ <bit child_node="PAU_FIR_2" node_inst="5,7" pos="11">Attention from PAU_FIR_2</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Attention from PAU_PHY_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_pauw_ucs_p10_10.xml b/xml/p10/node_cfir_pauw_ucs_p10_10.xml
index f52277a..76932a0 100644
--- a/xml/p10/node_cfir_pauw_ucs_p10_10.xml
+++ b/xml/p10/node_cfir_pauw_ucs_p10_10.xml
@@ -17,13 +17,13 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Local FIR</bit>
- <bit child_node="PAU_FIR_0" node_inst="4,6" pos="5">Local FIR register for the PAU (1 of 3)</bit>
- <bit child_node="PAU_FIR_1" node_inst="4,6" pos="6">Local FIR register for the PAU (2 of 3)</bit>
- <bit child_node="PAU_FIR_2" node_inst="4,6" pos="7">Local FIR register for the PAU (3 of 3)</bit>
- <bit child_node="PAU_FIR_0" node_inst="5,7" pos="9">Local FIR register for the PAU (1 of 3)</bit>
- <bit child_node="PAU_FIR_1" node_inst="5,7" pos="10">Local FIR register for the PAU (2 of 3)</bit>
- <bit child_node="PAU_FIR_2" node_inst="5,7" pos="11">Local FIR register for the PAU (3 of 3)</bit>
- <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Local FIR register for the chip pervasive logic</bit>
- <bit child_node="PAU_DL_FIR" node_inst="2,3" pos="14">Local FIR register for the chip pervasive logic</bit>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Attention from PAU_LOCAL_FIR</bit>
+ <bit child_node="PAU_FIR_0" node_inst="4,6" pos="5">Attention from PAU_FIR_0</bit>
+ <bit child_node="PAU_FIR_1" node_inst="4,6" pos="6">Attention from PAU_FIR_1</bit>
+ <bit child_node="PAU_FIR_2" node_inst="4,6" pos="7">Attention from PAU_FIR_2</bit>
+ <bit child_node="PAU_FIR_0" node_inst="5,7" pos="9">Attention from PAU_FIR_0</bit>
+ <bit child_node="PAU_FIR_1" node_inst="5,7" pos="10">Attention from PAU_FIR_1</bit>
+ <bit child_node="PAU_FIR_2" node_inst="5,7" pos="11">Attention from PAU_FIR_2</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Attention from PAU_PHY_FIR</bit>
+ <bit child_node="PAU_DL_FIR" node_inst="2,3" pos="14">Attention from PAU_DL_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_pci_cs_re.xml b/xml/p10/node_cfir_pci_cs_re.xml
index 0c78fd3..0cd9339 100644
--- a/xml/p10/node_cfir_pci_cs_re.xml
+++ b/xml/p10/node_cfir_pci_cs_re.xml
@@ -34,13 +34,13 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="PCI_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
- <bit child_node="PCI_ETU_FIR" node_inst="0,3" pos="5">ETU FIR Register</bit>
- <bit child_node="PCI_ETU_FIR" node_inst="1,4" pos="6">ETU FIR Register</bit>
- <bit child_node="PCI_ETU_FIR" node_inst="2,5" pos="7">ETU FIR Register</bit>
- <bit child_node="PCI_FIR" node_inst="0,3" pos="9">PCI FIR Register</bit>
- <bit child_node="PCI_FIR" node_inst="1,4" pos="10">PCI FIR Register</bit>
- <bit child_node="PCI_FIR" node_inst="2,5" pos="11">PCI FIR Register</bit>
- <bit child_node="PCI_IOP_FIR" node_inst="0,2" pos="12">IOP Local Fault Isolation Register. Register bits are set for any error condition detected by the IOP. The IOPFIR will freeze upon logging the first error not masked in IOPMASK.</bit>
- <bit child_node="PCI_IOP_FIR" node_inst="1,3" pos="13">IOP Local Fault Isolation Register. Register bits are set for any error condition detected by the IOP. The IOPFIR will freeze upon logging the first error not masked in IOPMASK.</bit>
+ <bit child_node="PCI_LOCAL_FIR" node_inst="0,1" pos="4">Attention from PCI_LOCAL_FIR</bit>
+ <bit child_node="PCI_ETU_FIR" node_inst="0,3" pos="5">Attention from PCI_ETU_FIR 0</bit>
+ <bit child_node="PCI_ETU_FIR" node_inst="1,4" pos="6">Attention from PCI_ETU_FIR 1</bit>
+ <bit child_node="PCI_ETU_FIR" node_inst="2,5" pos="7">Attention from PCI_ETU_FIR 2</bit>
+ <bit child_node="PCI_FIR" node_inst="0,3" pos="9">Attention from PCI_FIR 0</bit>
+ <bit child_node="PCI_FIR" node_inst="1,4" pos="10">Attention from PCI_FIR 1</bit>
+ <bit child_node="PCI_FIR" node_inst="2,5" pos="11">Attention from PCI_FIR 2</bit>
+ <bit child_node="PCI_IOP_FIR" node_inst="0,2" pos="12">Attention from PCI_IOP_FIR 0</bit>
+ <bit child_node="PCI_IOP_FIR" node_inst="1,3" pos="13">Attention from PCI_IOP_FIR 1</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_pci_spa_ha.xml b/xml/p10/node_cfir_pci_spa_ha.xml
index f03156a..238b5c9 100644
--- a/xml/p10/node_cfir_pci_spa_ha.xml
+++ b/xml/p10/node_cfir_pci_spa_ha.xml
@@ -34,5 +34,5 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="PCI_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
+ <bit child_node="PCI_LOCAL_FIR" node_inst="0,1" pos="4">Attention from PCI_LOCAL_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_pci_ucs.xml b/xml/p10/node_cfir_pci_ucs.xml
index c48ac5b..a7b981c 100644
--- a/xml/p10/node_cfir_pci_ucs.xml
+++ b/xml/p10/node_cfir_pci_ucs.xml
@@ -17,7 +17,7 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="PCI_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
- <bit child_node="PCI_IOP_FIR" node_inst="0,2" pos="12">IOP Local Fault Isolation Register. Register bits are set for any error condition detected by the IOP. The IOPFIR will freeze upon logging the first error not masked in IOPMASK.</bit>
- <bit child_node="PCI_IOP_FIR" node_inst="1,3" pos="13">IOP Local Fault Isolation Register. Register bits are set for any error condition detected by the IOP. The IOPFIR will freeze upon logging the first error not masked in IOPMASK.</bit>
+ <bit child_node="PCI_LOCAL_FIR" node_inst="0,1" pos="4">Attention from PCI_LOCAL_FIR</bit>
+ <bit child_node="PCI_IOP_FIR" node_inst="0,2" pos="12">Attention from PCI_IOP_FIR 0</bit>
+ <bit child_node="PCI_IOP_FIR" node_inst="1,3" pos="13">Attention from PCI_IOP_FIR 1</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_tp_cs_re.xml b/xml/p10/node_cfir_tp_cs_re.xml
index 20fd153..639a381 100644
--- a/xml/p10/node_cfir_tp_cs_re.xml
+++ b/xml/p10/node_cfir_tp_cs_re.xml
@@ -30,7 +30,7 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="TP_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
- <bit child_node="OCC_FIR" node_inst="0" pos="5">OCC Local Fault Isolation Register</bit>
- <bit child_node="PBAO_FIR" node_inst="0" pos="6">PBA Local Fault Isolation Register. Register bits are set for any error condition detected by the PBA. The PBAFIR will freeze upon logging the first error not masked in PBAFIRMASK.</bit>
+ <bit child_node="TP_LOCAL_FIR" node_inst="0" pos="4">Attention from TP_LOCAL_FIR</bit>
+ <bit child_node="OCC_FIR" node_inst="0" pos="5">Attention from OCC_FIR</bit>
+ <bit child_node="PBAO_FIR" node_inst="0" pos="6">Attention from PBAO_FIR</bit>
</attn_node>
diff --git a/xml/p10/node_cfir_tp_spa_ucs_ha.xml b/xml/p10/node_cfir_tp_spa_ucs_ha.xml
index 37313b9..cc70c5b 100644
--- a/xml/p10/node_cfir_tp_spa_ucs_ha.xml
+++ b/xml/p10/node_cfir_tp_spa_ucs_ha.xml
@@ -45,5 +45,5 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <bit child_node="TP_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
+ <bit child_node="TP_LOCAL_FIR" node_inst="0" pos="4">Attention from TP_LOCAL_FIR</bit>
</attn_node>