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gerrit.openbmc.org / openbmc / openpower-libhei / 94db72a9842935ce3de114f8c17df3ba986a6056 / . / xml / p10 / node_pll_unlock.xml
blob: ae690f7cefe2a313fa3f83c4e7f1181e08f41c91 [file] [log] [blame]
<?xml version="1.0" encoding="UTF-8"?>
<attn_node model_ec="P10_10,P10_20" name="PLL_UNLOCK" reg_type="SCOM">
<capture_group node_inst="0">
<capture_register reg_name="ROOT_CTRL0" reg_inst= "0" />
<capture_register reg_name="ROOT_CTRL3" reg_inst= "0" />
<capture_register reg_name="ROOT_CTRL4" reg_inst= "0" />
<capture_register reg_name="ROOT_CTRL5" reg_inst= "0" />
<capture_register reg_name="ROOT_CTRL6" reg_inst= "0" />
<capture_register reg_name="RCS_SENSE_1" reg_inst= "0" />
<capture_register reg_name="RCS_SENSE_2" reg_inst= "0" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst= "1" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst= "2" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst= "3" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst= "8" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst= "9" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="12" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="13" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="14" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="15" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="16" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="17" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="18" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="19" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="24" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="25" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="26" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="27" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="28" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="29" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="30" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="31" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="32" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="33" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="34" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="35" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="36" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="37" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="38" />
<capture_register reg_name="PCBSLV_CONFIG" reg_inst="39" />
<capture_register reg_name="BC_OR_PCBSLV_ERROR" reg_inst= "0" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst= "1" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst= "2" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst= "3" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst= "8" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst= "9" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="12" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="13" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="14" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="15" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="16" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="17" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="18" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="19" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="24" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="25" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="26" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="27" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="28" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="29" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="30" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="31" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="32" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="33" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="34" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="35" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="36" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="37" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="38" />
<capture_register reg_name="PCBSLV_ERROR" reg_inst="39" />
</capture_group>
<rule attn_type="CS" node_inst="0">
<expr type="or">
<!-- PLL summary for clock 0 -->
<expr type="and">
<!-- Check for primary clock 0 (RCS_SENSE_1[12]) -->
<expr type="lshift" value1="12">
<expr type="reg" value1="RCS_SENSE_1" />
</expr>
<!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
<expr type="or">
<expr type="lshift" value1="24">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="25">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="26">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="27">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="28">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="29">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="30">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="31">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
</expr>
<!-- The summary has been shifted to the left most bit. -->
<expr type="int" value1="0x8000000000000000"/>
</expr>
<!-- PLL summary for clock 1 -->
<expr type="rshift" value1="1">
<expr type="and">
<!-- Check for primary clock 1 (RCS_SENSE_1[13]) -->
<expr type="lshift" value1="13">
<expr type="reg" value1="RCS_SENSE_1" />
</expr>
<!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
<expr type="or">
<expr type="lshift" value1="24">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="25">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="26">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="27">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="28">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="29">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="30">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="31">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
</expr>
<!-- The summary has been shifted to the left most bit. -->
<expr type="int" value1="0x8000000000000000"/>
</expr>
</expr>
</expr>
</rule>
<rule attn_type="RE" node_inst="0">
<expr type="or">
<!-- PLL summary for clock 0 -->
<expr type="and">
<!-- Check for primary clock 0 (RCS_SENSE_1[12]) -->
<expr type="lshift" value1="12">
<expr type="reg" value1="RCS_SENSE_1" />
</expr>
<!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
<expr type="or">
<expr type="lshift" value1="24">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="25">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="26">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="27">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="28">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="29">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="30">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="31">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
</expr>
<!-- The summary has been shifted to the left most bit. -->
<expr type="int" value1="0x8000000000000000"/>
</expr>
<!-- PLL summary for clock 1 -->
<expr type="rshift" value1="1">
<expr type="and">
<!-- Check for primary clock 1 (RCS_SENSE_1[13]) -->
<expr type="lshift" value1="13">
<expr type="reg" value1="RCS_SENSE_1" />
</expr>
<!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
<expr type="or">
<expr type="lshift" value1="24">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="25">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="26">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="27">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="28">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="29">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="30">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="31">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
</expr>
<!-- The summary has been shifted to the left most bit. -->
<expr type="int" value1="0x8000000000000000"/>
</expr>
</expr>
</expr>
</rule>
<rule attn_type="SPA" node_inst="0">
<expr type="or">
<!-- PLL summary for clock 0 -->
<expr type="and">
<!-- Check for primary clock 0 (RCS_SENSE_1[12]) -->
<expr type="lshift" value1="12">
<expr type="reg" value1="RCS_SENSE_1" />
</expr>
<!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
<expr type="or">
<expr type="lshift" value1="24">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="25">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="26">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="27">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="28">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="29">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="30">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="31">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
</expr>
<!-- The summary has been shifted to the left most bit. -->
<expr type="int" value1="0x8000000000000000"/>
</expr>
<!-- PLL summary for clock 1 -->
<expr type="rshift" value1="1">
<expr type="and">
<!-- Check for primary clock 1 (RCS_SENSE_1[13]) -->
<expr type="lshift" value1="13">
<expr type="reg" value1="RCS_SENSE_1" />
</expr>
<!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
<expr type="or">
<expr type="lshift" value1="24">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="25">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="26">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="27">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="28">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="29">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="30">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="31">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
</expr>
<!-- The summary has been shifted to the left most bit. -->
<expr type="int" value1="0x8000000000000000"/>
</expr>
</expr>
</expr>
</rule>
<rule attn_type="UCS" node_inst="0">
<expr type="or">
<!-- PLL summary for clock 0 -->
<expr type="and">
<!-- Check for primary clock 0 (RCS_SENSE_1[12]) -->
<expr type="lshift" value1="12">
<expr type="reg" value1="RCS_SENSE_1" />
</expr>
<!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
<expr type="or">
<expr type="lshift" value1="24">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="25">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="26">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="27">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="28">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="29">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="30">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="31">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
</expr>
<!-- The summary has been shifted to the left most bit. -->
<expr type="int" value1="0x8000000000000000"/>
</expr>
<!-- PLL summary for clock 1 -->
<expr type="rshift" value1="1">
<expr type="and">
<!-- Check for primary clock 1 (RCS_SENSE_1[13]) -->
<expr type="lshift" value1="13">
<expr type="reg" value1="RCS_SENSE_1" />
</expr>
<!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
<expr type="or">
<expr type="lshift" value1="24">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="25">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="26">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="27">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="28">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="29">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="30">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="31">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
</expr>
<!-- The summary has been shifted to the left most bit. -->
<expr type="int" value1="0x8000000000000000"/>
</expr>
</expr>
</expr>
</rule>
<rule attn_type="HA" node_inst="0">
<expr type="or">
<!-- PLL summary for clock 0 -->
<expr type="and">
<!-- Check for primary clock 0 (RCS_SENSE_1[12]) -->
<expr type="lshift" value1="12">
<expr type="reg" value1="RCS_SENSE_1" />
</expr>
<!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
<expr type="or">
<expr type="lshift" value1="24">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="25">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="26">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="27">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="28">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="29">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="30">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="31">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
</expr>
<!-- The summary has been shifted to the left most bit. -->
<expr type="int" value1="0x8000000000000000"/>
</expr>
<!-- PLL summary for clock 1 -->
<expr type="rshift" value1="1">
<expr type="and">
<!-- Check for primary clock 1 (RCS_SENSE_1[13]) -->
<expr type="lshift" value1="13">
<expr type="reg" value1="RCS_SENSE_1" />
</expr>
<!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
<expr type="or">
<expr type="lshift" value1="24">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="25">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="26">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="27">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="28">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="29">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="30">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
<expr type="lshift" value1="31">
<expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
</expr>
</expr>
<!-- The summary has been shifted to the left most bit. -->
<expr type="int" value1="0x8000000000000000"/>
</expr>
</expr>
</expr>
</rule>
<bit pos="0">PLL unlock on clk A</bit>
<bit pos="1">PLL unlock on clk B</bit>
</attn_node>