Copied Chip Data XML from Hostboot project
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I0a230be8ba2840768e2097fd4e479c8feb8fc452
diff --git a/xml/p10/node_cfir_eq_spa.xml b/xml/p10/node_cfir_eq_spa.xml
new file mode 100644
index 0000000..c2d544b
--- /dev/null
+++ b/xml/p10/node_cfir_eq_spa.xml
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_EQ_SPA" reg_type="SCOM">
+ <register name="CFIR_EQ_SPATTN">
+ <instance addr="0x20040002" reg_inst="0"/>
+ <instance addr="0x21040002" reg_inst="1"/>
+ <instance addr="0x22040002" reg_inst="2"/>
+ <instance addr="0x23040002" reg_inst="3"/>
+ <instance addr="0x24040002" reg_inst="4"/>
+ <instance addr="0x25040002" reg_inst="5"/>
+ <instance addr="0x26040002" reg_inst="6"/>
+ <instance addr="0x27040002" reg_inst="7"/>
+ </register>
+ <register name="CFIR_EQ_SPATTN_MASK">
+ <instance addr="0x20040042" reg_inst="0"/>
+ <instance addr="0x21040042" reg_inst="1"/>
+ <instance addr="0x22040042" reg_inst="2"/>
+ <instance addr="0x23040042" reg_inst="3"/>
+ <instance addr="0x24040042" reg_inst="4"/>
+ <instance addr="0x25040042" reg_inst="5"/>
+ <instance addr="0x26040042" reg_inst="6"/>
+ <instance addr="0x27040042" reg_inst="7"/>
+ </register>
+ <rule attn_type="SPA" node_inst="0:7">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_EQ_SPATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_EQ_SPATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Local FIR</bit>
+ <!-- NOTE: Attentions routed to this node from the EQ_SPATTN registers
+ depend if the cores are configured in Normal or Fused Core mode.
+ Therefore the core thread state must be queried first. -->
+ <bit child_node="EQ_CORE_THREAD_STATE" node_inst="0,4,8,12,16,20,24,28" pos="5:8">Core Special Attention Register</bit>
+ <bit child_node="EQ_CORE_THREAD_STATE" node_inst="1,5,9,13,17,21,25,29" pos="9:12">Core Special Attention Register</bit>
+ <bit child_node="EQ_CORE_THREAD_STATE" node_inst="2,6,10,14,18,22,26,30" pos="13:16">Core Special Attention Register</bit>
+ <bit child_node="EQ_CORE_THREAD_STATE" node_inst="3,7,11,15,19,23,27,31" pos="17:20">Core Special Attention Register</bit>
+</attn_node>