Copied Chip Data XML from Hostboot project
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I0a230be8ba2840768e2097fd4e479c8feb8fc452
diff --git a/xml/p10/chip_p10.xml b/xml/p10/chip_p10.xml
new file mode 100644
index 0000000..f598f33
--- /dev/null
+++ b/xml/p10/chip_p10.xml
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<chip model_ec="P10_10" name="P10">
+ <attn_tree attn_type="CS" node_inst="0" root_node="GFIR_CS"/>
+ <attn_tree attn_type="RE" node_inst="0" root_node="GFIR_RE"/>
+ <attn_tree attn_type="SPA" node_inst="0" root_node="GFIR_SPA"/>
+ <attn_tree attn_type="UCS" node_inst="0" root_node="GFIR_UCS"/>
+ <attn_tree attn_type="HA" node_inst="0" root_node="GFIR_HA"/>
+</chip>
diff --git a/xml/p10/node_cfir_eq_cs.xml b/xml/p10/node_cfir_eq_cs.xml
new file mode 100644
index 0000000..8aa6162
--- /dev/null
+++ b/xml/p10/node_cfir_eq_cs.xml
@@ -0,0 +1,50 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_EQ_CS" reg_type="SCOM">
+ <register name="CFIR_EQ_XSTOP">
+ <instance addr="0x20040000" reg_inst="0"/>
+ <instance addr="0x21040000" reg_inst="1"/>
+ <instance addr="0x22040000" reg_inst="2"/>
+ <instance addr="0x23040000" reg_inst="3"/>
+ <instance addr="0x24040000" reg_inst="4"/>
+ <instance addr="0x25040000" reg_inst="5"/>
+ <instance addr="0x26040000" reg_inst="6"/>
+ <instance addr="0x27040000" reg_inst="7"/>
+ </register>
+ <register name="CFIR_EQ_XSTOP_MASK">
+ <instance addr="0x20040040" reg_inst="0"/>
+ <instance addr="0x21040040" reg_inst="1"/>
+ <instance addr="0x22040040" reg_inst="2"/>
+ <instance addr="0x23040040" reg_inst="3"/>
+ <instance addr="0x24040040" reg_inst="4"/>
+ <instance addr="0x25040040" reg_inst="5"/>
+ <instance addr="0x26040040" reg_inst="6"/>
+ <instance addr="0x27040040" reg_inst="7"/>
+ </register>
+ <rule attn_type="CS" node_inst="0:7">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_EQ_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_EQ_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Local FIR</bit>
+ <bit child_node="EQ_L2_FIR" node_inst="0,4,8,12,16,20,24,28" pos="9">L2 FIR Register</bit>
+ <bit child_node="EQ_L2_FIR" node_inst="1,5,9,13,17,21,25,29" pos="10">L2 FIR Register</bit>
+ <bit child_node="EQ_L2_FIR" node_inst="2,6,10,14,18,22,26,30" pos="11">L2 FIR Register</bit>
+ <bit child_node="EQ_L2_FIR" node_inst="3,7,11,15,19,23,27,31" pos="12">L2 FIR Register</bit>
+ <bit child_node="EQ_L3_FIR" node_inst="0,4,8,12,16,20,24,28" pos="13">L3 FIR Register</bit>
+ <bit child_node="EQ_L3_FIR" node_inst="1,5,9,13,17,21,25,29" pos="14">L3 FIR Register</bit>
+ <bit child_node="EQ_L3_FIR" node_inst="2,6,10,14,18,22,26,30" pos="15">L3 FIR Register</bit>
+ <bit child_node="EQ_L3_FIR" node_inst="3,7,11,15,19,23,27,31" pos="16">L3 FIR Register</bit>
+ <bit child_node="EQ_NCU_FIR" node_inst="0,4,8,12,16,20,24,28" pos="17">NCU FIR Register</bit>
+ <bit child_node="EQ_NCU_FIR" node_inst="1,5,9,13,17,21,25,29" pos="18">NCU FIR Register</bit>
+ <bit child_node="EQ_NCU_FIR" node_inst="2,6,10,14,18,22,26,30" pos="19">NCU FIR Register</bit>
+ <bit child_node="EQ_NCU_FIR" node_inst="3,7,11,15,19,23,27,31" pos="20">NCU FIR Register</bit>
+ <bit child_node="EQ_QME_FIR" node_inst="0,1,2,3,4,5,6,7" pos="21">QME Local Fault Isolation Register</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="0,4,8,12,16,20,24,28" pos="5">Core Fault Isolation Register</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="1,5,9,13,17,21,25,29" pos="6">Core Fault Isolation Register</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="2,6,10,14,18,22,26,30" pos="7">Core Fault Isolation Register</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="3,7,11,15,19,23,27,31" pos="8">Core Fault Isolation Register</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_eq_ha.xml b/xml/p10/node_cfir_eq_ha.xml
new file mode 100644
index 0000000..00cf785
--- /dev/null
+++ b/xml/p10/node_cfir_eq_ha.xml
@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_EQ_HA" reg_type="SCOM">
+ <register name="CFIR_EQ_HOSTATTN">
+ <instance addr="0x20040004" reg_inst="0"/>
+ <instance addr="0x21040004" reg_inst="1"/>
+ <instance addr="0x22040004" reg_inst="2"/>
+ <instance addr="0x23040004" reg_inst="3"/>
+ <instance addr="0x24040004" reg_inst="4"/>
+ <instance addr="0x25040004" reg_inst="5"/>
+ <instance addr="0x26040004" reg_inst="6"/>
+ <instance addr="0x27040004" reg_inst="7"/>
+ </register>
+ <register name="CFIR_EQ_HOSTATTN_MASK">
+ <instance addr="0x20040044" reg_inst="0"/>
+ <instance addr="0x21040044" reg_inst="1"/>
+ <instance addr="0x22040044" reg_inst="2"/>
+ <instance addr="0x23040044" reg_inst="3"/>
+ <instance addr="0x24040044" reg_inst="4"/>
+ <instance addr="0x25040044" reg_inst="5"/>
+ <instance addr="0x26040044" reg_inst="6"/>
+ <instance addr="0x27040044" reg_inst="7"/>
+ </register>
+ <rule attn_type="HA" node_inst="0:7">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_EQ_HOSTATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_EQ_HOSTATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Local FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_eq_re.xml b/xml/p10/node_cfir_eq_re.xml
new file mode 100644
index 0000000..180691a
--- /dev/null
+++ b/xml/p10/node_cfir_eq_re.xml
@@ -0,0 +1,51 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_EQ_RE" reg_type="SCOM">
+ <register name="CFIR_EQ_RECOV">
+ <instance addr="0x20040001" reg_inst="0"/>
+ <instance addr="0x21040001" reg_inst="1"/>
+ <instance addr="0x22040001" reg_inst="2"/>
+ <instance addr="0x23040001" reg_inst="3"/>
+ <instance addr="0x24040001" reg_inst="4"/>
+ <instance addr="0x25040001" reg_inst="5"/>
+ <instance addr="0x26040001" reg_inst="6"/>
+ <instance addr="0x27040001" reg_inst="7"/>
+ </register>
+ <register name="CFIR_EQ_RECOV_MASK">
+ <instance addr="0x20040041" reg_inst="0"/>
+ <instance addr="0x21040041" reg_inst="1"/>
+ <instance addr="0x22040041" reg_inst="2"/>
+ <instance addr="0x23040041" reg_inst="3"/>
+ <instance addr="0x24040041" reg_inst="4"/>
+ <instance addr="0x25040041" reg_inst="5"/>
+ <instance addr="0x26040041" reg_inst="6"/>
+ <instance addr="0x27040041" reg_inst="7"/>
+ </register>
+ <rule attn_type="RE" node_inst="0:7">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_EQ_RECOV"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_EQ_RECOV_MASK"/>
+ </expr>
+ <expr type="int" value1="0x2FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit pos="2">recovery with any local checkstop</bit>
+ <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Local FIR</bit>
+ <bit child_node="EQ_L2_FIR" node_inst="0,4,8,12,16,20,24,28" pos="9">L2 FIR Register</bit>
+ <bit child_node="EQ_L2_FIR" node_inst="1,5,9,13,17,21,25,29" pos="10">L2 FIR Register</bit>
+ <bit child_node="EQ_L2_FIR" node_inst="2,6,10,14,18,22,26,30" pos="11">L2 FIR Register</bit>
+ <bit child_node="EQ_L2_FIR" node_inst="3,7,11,15,19,23,27,31" pos="12">L2 FIR Register</bit>
+ <bit child_node="EQ_L3_FIR" node_inst="0,4,8,12,16,20,24,28" pos="13">L3 FIR Register</bit>
+ <bit child_node="EQ_L3_FIR" node_inst="1,5,9,13,17,21,25,29" pos="14">L3 FIR Register</bit>
+ <bit child_node="EQ_L3_FIR" node_inst="2,6,10,14,18,22,26,30" pos="15">L3 FIR Register</bit>
+ <bit child_node="EQ_L3_FIR" node_inst="3,7,11,15,19,23,27,31" pos="16">L3 FIR Register</bit>
+ <bit child_node="EQ_NCU_FIR" node_inst="0,4,8,12,16,20,24,28" pos="17">NCU FIR Register</bit>
+ <bit child_node="EQ_NCU_FIR" node_inst="1,5,9,13,17,21,25,29" pos="18">NCU FIR Register</bit>
+ <bit child_node="EQ_NCU_FIR" node_inst="2,6,10,14,18,22,26,30" pos="19">NCU FIR Register</bit>
+ <bit child_node="EQ_NCU_FIR" node_inst="3,7,11,15,19,23,27,31" pos="20">NCU FIR Register</bit>
+ <bit child_node="EQ_QME_FIR" node_inst="0,1,2,3,4,5,6,7" pos="21">QME Local Fault Isolation Register</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="0,4,8,12,16,20,24,28" pos="5">Core Fault Isolation Register</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="1,5,9,13,17,21,25,29" pos="6">Core Fault Isolation Register</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="2,6,10,14,18,22,26,30" pos="7">Core Fault Isolation Register</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="3,7,11,15,19,23,27,31" pos="8">Core Fault Isolation Register</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_eq_spa.xml b/xml/p10/node_cfir_eq_spa.xml
new file mode 100644
index 0000000..c2d544b
--- /dev/null
+++ b/xml/p10/node_cfir_eq_spa.xml
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_EQ_SPA" reg_type="SCOM">
+ <register name="CFIR_EQ_SPATTN">
+ <instance addr="0x20040002" reg_inst="0"/>
+ <instance addr="0x21040002" reg_inst="1"/>
+ <instance addr="0x22040002" reg_inst="2"/>
+ <instance addr="0x23040002" reg_inst="3"/>
+ <instance addr="0x24040002" reg_inst="4"/>
+ <instance addr="0x25040002" reg_inst="5"/>
+ <instance addr="0x26040002" reg_inst="6"/>
+ <instance addr="0x27040002" reg_inst="7"/>
+ </register>
+ <register name="CFIR_EQ_SPATTN_MASK">
+ <instance addr="0x20040042" reg_inst="0"/>
+ <instance addr="0x21040042" reg_inst="1"/>
+ <instance addr="0x22040042" reg_inst="2"/>
+ <instance addr="0x23040042" reg_inst="3"/>
+ <instance addr="0x24040042" reg_inst="4"/>
+ <instance addr="0x25040042" reg_inst="5"/>
+ <instance addr="0x26040042" reg_inst="6"/>
+ <instance addr="0x27040042" reg_inst="7"/>
+ </register>
+ <rule attn_type="SPA" node_inst="0:7">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_EQ_SPATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_EQ_SPATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Local FIR</bit>
+ <!-- NOTE: Attentions routed to this node from the EQ_SPATTN registers
+ depend if the cores are configured in Normal or Fused Core mode.
+ Therefore the core thread state must be queried first. -->
+ <bit child_node="EQ_CORE_THREAD_STATE" node_inst="0,4,8,12,16,20,24,28" pos="5:8">Core Special Attention Register</bit>
+ <bit child_node="EQ_CORE_THREAD_STATE" node_inst="1,5,9,13,17,21,25,29" pos="9:12">Core Special Attention Register</bit>
+ <bit child_node="EQ_CORE_THREAD_STATE" node_inst="2,6,10,14,18,22,26,30" pos="13:16">Core Special Attention Register</bit>
+ <bit child_node="EQ_CORE_THREAD_STATE" node_inst="3,7,11,15,19,23,27,31" pos="17:20">Core Special Attention Register</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_eq_ucs.xml b/xml/p10/node_cfir_eq_ucs.xml
new file mode 100644
index 0000000..6220245
--- /dev/null
+++ b/xml/p10/node_cfir_eq_ucs.xml
@@ -0,0 +1,37 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_EQ_UCS" reg_type="SCOM">
+ <register name="CFIR_EQ_LOCAL_XSTOP">
+ <instance addr="0x20040003" reg_inst="0"/>
+ <instance addr="0x21040003" reg_inst="1"/>
+ <instance addr="0x22040003" reg_inst="2"/>
+ <instance addr="0x23040003" reg_inst="3"/>
+ <instance addr="0x24040003" reg_inst="4"/>
+ <instance addr="0x25040003" reg_inst="5"/>
+ <instance addr="0x26040003" reg_inst="6"/>
+ <instance addr="0x27040003" reg_inst="7"/>
+ </register>
+ <register name="CFIR_EQ_LOCAL_XSTOP_MASK">
+ <instance addr="0x20040043" reg_inst="0"/>
+ <instance addr="0x21040043" reg_inst="1"/>
+ <instance addr="0x22040043" reg_inst="2"/>
+ <instance addr="0x23040043" reg_inst="3"/>
+ <instance addr="0x24040043" reg_inst="4"/>
+ <instance addr="0x25040043" reg_inst="5"/>
+ <instance addr="0x26040043" reg_inst="6"/>
+ <instance addr="0x27040043" reg_inst="7"/>
+ </register>
+ <rule attn_type="UCS" node_inst="0:7">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_EQ_LOCAL_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_EQ_LOCAL_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Local FIR</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="0,4,8,12,16,20,24,28" pos="5">Core Fault Isolation Register</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="1,5,9,13,17,21,25,29" pos="6">Core Fault Isolation Register</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="2,6,10,14,18,22,26,30" pos="7">Core Fault Isolation Register</bit>
+ <bit child_node="EQ_CORE_FIR" node_inst="3,7,11,15,19,23,27,31" pos="8">Core Fault Isolation Register</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_iohs_cs_re_spa.xml b/xml/p10/node_cfir_iohs_cs_re_spa.xml
new file mode 100644
index 0000000..d3153ac
--- /dev/null
+++ b/xml/p10/node_cfir_iohs_cs_re_spa.xml
@@ -0,0 +1,92 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_IOHS_CS_RE_SPA" reg_type="SCOM">
+ <register name="CFIR_IOHS_XSTOP">
+ <instance addr="0x18040000" reg_inst="0"/>
+ <instance addr="0x19040000" reg_inst="1"/>
+ <instance addr="0x1A040000" reg_inst="2"/>
+ <instance addr="0x1B040000" reg_inst="3"/>
+ <instance addr="0x1C040000" reg_inst="4"/>
+ <instance addr="0x1D040000" reg_inst="5"/>
+ <instance addr="0x1E040000" reg_inst="6"/>
+ <instance addr="0x1F040000" reg_inst="7"/>
+ </register>
+ <register name="CFIR_IOHS_XSTOP_MASK">
+ <instance addr="0x18040040" reg_inst="0"/>
+ <instance addr="0x19040040" reg_inst="1"/>
+ <instance addr="0x1A040040" reg_inst="2"/>
+ <instance addr="0x1B040040" reg_inst="3"/>
+ <instance addr="0x1C040040" reg_inst="4"/>
+ <instance addr="0x1D040040" reg_inst="5"/>
+ <instance addr="0x1E040040" reg_inst="6"/>
+ <instance addr="0x1F040040" reg_inst="7"/>
+ </register>
+ <register name="CFIR_IOHS_RECOV">
+ <instance addr="0x18040001" reg_inst="0"/>
+ <instance addr="0x19040001" reg_inst="1"/>
+ <instance addr="0x1A040001" reg_inst="2"/>
+ <instance addr="0x1B040001" reg_inst="3"/>
+ <instance addr="0x1C040001" reg_inst="4"/>
+ <instance addr="0x1D040001" reg_inst="5"/>
+ <instance addr="0x1E040001" reg_inst="6"/>
+ <instance addr="0x1F040001" reg_inst="7"/>
+ </register>
+ <register name="CFIR_IOHS_RECOV_MASK">
+ <instance addr="0x18040041" reg_inst="0"/>
+ <instance addr="0x19040041" reg_inst="1"/>
+ <instance addr="0x1A040041" reg_inst="2"/>
+ <instance addr="0x1B040041" reg_inst="3"/>
+ <instance addr="0x1C040041" reg_inst="4"/>
+ <instance addr="0x1D040041" reg_inst="5"/>
+ <instance addr="0x1E040041" reg_inst="6"/>
+ <instance addr="0x1F040041" reg_inst="7"/>
+ </register>
+ <register name="CFIR_IOHS_SPATTN">
+ <instance addr="0x18040002" reg_inst="0"/>
+ <instance addr="0x19040002" reg_inst="1"/>
+ <instance addr="0x1A040002" reg_inst="2"/>
+ <instance addr="0x1B040002" reg_inst="3"/>
+ <instance addr="0x1C040002" reg_inst="4"/>
+ <instance addr="0x1D040002" reg_inst="5"/>
+ <instance addr="0x1E040002" reg_inst="6"/>
+ <instance addr="0x1F040002" reg_inst="7"/>
+ </register>
+ <register name="CFIR_IOHS_SPATTN_MASK">
+ <instance addr="0x18040042" reg_inst="0"/>
+ <instance addr="0x19040042" reg_inst="1"/>
+ <instance addr="0x1A040042" reg_inst="2"/>
+ <instance addr="0x1B040042" reg_inst="3"/>
+ <instance addr="0x1C040042" reg_inst="4"/>
+ <instance addr="0x1D040042" reg_inst="5"/>
+ <instance addr="0x1E040042" reg_inst="6"/>
+ <instance addr="0x1F040042" reg_inst="7"/>
+ </register>
+ <rule attn_type="CS" node_inst="0:7">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_IOHS_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_IOHS_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <rule attn_type="RE" node_inst="0:7">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_IOHS_RECOV"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_IOHS_RECOV_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <rule attn_type="SPA" node_inst="0:7">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_IOHS_SPATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_IOHS_SPATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="IOHS_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Local FIR</bit>
+ <bit child_node="IOHS_DLP_FIR" node_inst="0,1,2,3,4,5,6,7" pos="5">PowerBus OLL FIR Register</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_iohs_ucs_ha.xml b/xml/p10/node_cfir_iohs_ucs_ha.xml
new file mode 100644
index 0000000..cf8f9cc
--- /dev/null
+++ b/xml/p10/node_cfir_iohs_ucs_ha.xml
@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_IOHS_UCS_HA" reg_type="SCOM">
+ <register name="CFIR_IOHS_LOCAL_XSTOP">
+ <instance addr="0x18040003" reg_inst="0"/>
+ <instance addr="0x19040003" reg_inst="1"/>
+ <instance addr="0x1A040003" reg_inst="2"/>
+ <instance addr="0x1B040003" reg_inst="3"/>
+ <instance addr="0x1C040003" reg_inst="4"/>
+ <instance addr="0x1D040003" reg_inst="5"/>
+ <instance addr="0x1E040003" reg_inst="6"/>
+ <instance addr="0x1F040003" reg_inst="7"/>
+ </register>
+ <register name="CFIR_IOHS_LOCAL_XSTOP_MASK">
+ <instance addr="0x18040043" reg_inst="0"/>
+ <instance addr="0x19040043" reg_inst="1"/>
+ <instance addr="0x1A040043" reg_inst="2"/>
+ <instance addr="0x1B040043" reg_inst="3"/>
+ <instance addr="0x1C040043" reg_inst="4"/>
+ <instance addr="0x1D040043" reg_inst="5"/>
+ <instance addr="0x1E040043" reg_inst="6"/>
+ <instance addr="0x1F040043" reg_inst="7"/>
+ </register>
+ <register name="CFIR_IOHS_HOSTATTN">
+ <instance addr="0x18040004" reg_inst="0"/>
+ <instance addr="0x19040004" reg_inst="1"/>
+ <instance addr="0x1A040004" reg_inst="2"/>
+ <instance addr="0x1B040004" reg_inst="3"/>
+ <instance addr="0x1C040004" reg_inst="4"/>
+ <instance addr="0x1D040004" reg_inst="5"/>
+ <instance addr="0x1E040004" reg_inst="6"/>
+ <instance addr="0x1F040004" reg_inst="7"/>
+ </register>
+ <register name="CFIR_IOHS_HOSTATTN_MASK">
+ <instance addr="0x18040044" reg_inst="0"/>
+ <instance addr="0x19040044" reg_inst="1"/>
+ <instance addr="0x1A040044" reg_inst="2"/>
+ <instance addr="0x1B040044" reg_inst="3"/>
+ <instance addr="0x1C040044" reg_inst="4"/>
+ <instance addr="0x1D040044" reg_inst="5"/>
+ <instance addr="0x1E040044" reg_inst="6"/>
+ <instance addr="0x1F040044" reg_inst="7"/>
+ </register>
+ <rule attn_type="UCS" node_inst="0:7">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_IOHS_LOCAL_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_IOHS_LOCAL_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <rule attn_type="HA" node_inst="0:7">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_IOHS_HOSTATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_IOHS_HOSTATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="IOHS_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Local FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_mc_cs_re_spa.xml b/xml/p10/node_cfir_mc_cs_re_spa.xml
new file mode 100644
index 0000000..2bf05f9
--- /dev/null
+++ b/xml/p10/node_cfir_mc_cs_re_spa.xml
@@ -0,0 +1,75 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_MC_CS_RE_SPA" reg_type="SCOM">
+ <register name="CFIR_MC_XSTOP">
+ <instance addr="0x0C040000" reg_inst="0"/>
+ <instance addr="0x0D040000" reg_inst="1"/>
+ <instance addr="0x0E040000" reg_inst="2"/>
+ <instance addr="0x0F040000" reg_inst="3"/>
+ </register>
+ <register name="CFIR_MC_XSTOP_MASK">
+ <instance addr="0x0C040040" reg_inst="0"/>
+ <instance addr="0x0D040040" reg_inst="1"/>
+ <instance addr="0x0E040040" reg_inst="2"/>
+ <instance addr="0x0F040040" reg_inst="3"/>
+ </register>
+ <register name="CFIR_MC_RECOV">
+ <instance addr="0x0C040001" reg_inst="0"/>
+ <instance addr="0x0D040001" reg_inst="1"/>
+ <instance addr="0x0E040001" reg_inst="2"/>
+ <instance addr="0x0F040001" reg_inst="3"/>
+ </register>
+ <register name="CFIR_MC_RECOV_MASK">
+ <instance addr="0x0C040041" reg_inst="0"/>
+ <instance addr="0x0D040041" reg_inst="1"/>
+ <instance addr="0x0E040041" reg_inst="2"/>
+ <instance addr="0x0F040041" reg_inst="3"/>
+ </register>
+ <register name="CFIR_MC_SPATTN">
+ <instance addr="0x0C040002" reg_inst="0"/>
+ <instance addr="0x0D040002" reg_inst="1"/>
+ <instance addr="0x0E040002" reg_inst="2"/>
+ <instance addr="0x0F040002" reg_inst="3"/>
+ </register>
+ <register name="CFIR_MC_SPATTN_MASK">
+ <instance addr="0x0C040042" reg_inst="0"/>
+ <instance addr="0x0D040042" reg_inst="1"/>
+ <instance addr="0x0E040042" reg_inst="2"/>
+ <instance addr="0x0F040042" reg_inst="3"/>
+ </register>
+ <rule attn_type="CS" node_inst="0:3">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_MC_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_MC_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <rule attn_type="RE" node_inst="0:3">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_MC_RECOV"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_MC_RECOV_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <rule attn_type="SPA" node_inst="0:3">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_MC_SPATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_MC_SPATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="MC_LOCAL_FIR" node_inst="0,1,2,3" pos="4">Local FIR</bit>
+ <bit child_node="MC_DSTL_FIR" node_inst="0,2,4,6" pos="5">MC Fault Isolation Register (DSTLFIR)</bit>
+ <bit child_node="MC_USTL_FIR" node_inst="0,2,4,6" pos="6">MC Fault Isolation Register (USTLFIR)</bit>
+ <bit child_node="MC_DSTL_FIR" node_inst="1,3,5,7" pos="7">MC Fault Isolation Register (DSTLFIR)</bit>
+ <bit child_node="MC_USTL_FIR" node_inst="1,3,5,7" pos="8">MC Fault Isolation Register (USTLFIR)</bit>
+ <bit child_node="MC_FIR" node_inst="0,1,2,3" pos="9">MC Fault Isolation Register (MCFIR)</bit>
+ <bit child_node="MC_MISC_FIR" node_inst="0,1,2,3" pos="10">MISC Fault Isolation Register</bit>
+ <bit child_node="MC_OMI_DL_FIR" node_inst="0,2,4,6" pos="13">OMI-DL common FIR Register</bit>
+ <bit child_node="MC_OMI_DL_FIR" node_inst="1,3,5,7" pos="14">OMI-DL common FIR Register</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_mc_ucs_ha.xml b/xml/p10/node_cfir_mc_ucs_ha.xml
new file mode 100644
index 0000000..3934db8
--- /dev/null
+++ b/xml/p10/node_cfir_mc_ucs_ha.xml
@@ -0,0 +1,52 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_MC_UCS_HA" reg_type="SCOM">
+ <register name="CFIR_MC_LOCAL_XSTOP">
+ <instance addr="0x0C040003" reg_inst="0"/>
+ <instance addr="0x0D040003" reg_inst="1"/>
+ <instance addr="0x0E040003" reg_inst="2"/>
+ <instance addr="0x0F040003" reg_inst="3"/>
+ </register>
+ <register name="CFIR_MC_LOCAL_XSTOP_MASK">
+ <instance addr="0x0C040043" reg_inst="0"/>
+ <instance addr="0x0D040043" reg_inst="1"/>
+ <instance addr="0x0E040043" reg_inst="2"/>
+ <instance addr="0x0F040043" reg_inst="3"/>
+ </register>
+ <register name="CFIR_MC_HOSTATTN">
+ <instance addr="0x0C040004" reg_inst="0"/>
+ <instance addr="0x0D040004" reg_inst="1"/>
+ <instance addr="0x0E040004" reg_inst="2"/>
+ <instance addr="0x0F040004" reg_inst="3"/>
+ </register>
+ <register name="CFIR_MC_HOSTATTN_MASK">
+ <instance addr="0x0C040044" reg_inst="0"/>
+ <instance addr="0x0D040044" reg_inst="1"/>
+ <instance addr="0x0E040044" reg_inst="2"/>
+ <instance addr="0x0F040044" reg_inst="3"/>
+ </register>
+ <rule attn_type="UCS" node_inst="0:3">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_MC_LOCAL_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_MC_LOCAL_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <rule attn_type="HA" node_inst="0:3">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_MC_HOSTATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_MC_HOSTATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="MC_LOCAL_FIR" node_inst="0,1,2,3" pos="4">Local FIR</bit>
+ <bit child_node="MC_DSTL_FIR" node_inst="0,2,4,6" pos="5">MC Fault Isolation Register (DSTLFIR)</bit>
+ <bit child_node="MC_USTL_FIR" node_inst="0,2,4,6" pos="6">MC Fault Isolation Register (USTLFIR)</bit>
+ <bit child_node="MC_DSTL_FIR" node_inst="1,3,5,7" pos="7">MC Fault Isolation Register (DSTLFIR)</bit>
+ <bit child_node="MC_USTL_FIR" node_inst="1,3,5,7" pos="8">MC Fault Isolation Register (USTLFIR)</bit>
+ <bit child_node="MC_FIR" node_inst="0,1,2,3" pos="9">MC Fault Isolation Register (MCFIR)</bit>
+ <bit child_node="MC_MISC_FIR" node_inst="0,1,2,3" pos="10">MISC Fault Isolation Register</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_n0_cs_re.xml b/xml/p10/node_cfir_n0_cs_re.xml
new file mode 100644
index 0000000..1df737a
--- /dev/null
+++ b/xml/p10/node_cfir_n0_cs_re.xml
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_N0_CS_RE" reg_type="SCOM">
+ <register name="CFIR_N0_XSTOP">
+ <instance addr="0x02040000" reg_inst="0"/>
+ </register>
+ <register name="CFIR_N0_XSTOP_MASK">
+ <instance addr="0x02040040" reg_inst="0"/>
+ </register>
+ <register name="CFIR_N0_RECOV">
+ <instance addr="0x02040001" reg_inst="0"/>
+ </register>
+ <register name="CFIR_N0_RECOV_MASK">
+ <instance addr="0x02040041" reg_inst="0"/>
+ </register>
+ <rule attn_type="CS" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_N0_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_N0_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <rule attn_type="RE" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_N0_RECOV"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_N0_RECOV_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="N0_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
+ <bit child_node="NMMU_CQ_FIR" node_inst="0" pos="5">PBI CQ FIR Register</bit>
+ <bit child_node="NMMU_FIR" node_inst="0" pos="6">NMMU FIR1 Register</bit>
+ <bit child_node="INT_CQ_FIR" node_inst="0" pos="7">Primary Error Register for INT_CQ. This contains all of the individual errors detected by INT_CQ, plus summary error indicators from VC and PC (see bits 43:63).</bit>
+ <bit child_node="VAS_FIR" node_inst="0" pos="8">Local FIR register for the VAS unit logic</bit>
+ <bit child_node="NX_DMA_ENG_FIR" node_inst="0" pos="9">DMA and Engine Fault Isolation Register</bit>
+ <bit child_node="NX_CQ_FIR" node_inst="0" pos="10">PBI CQ FIR Register</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="3" pos="13">PCI Nest FIR Register</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="4" pos="14">PCI Nest FIR Register</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="5" pos="15">PCI Nest FIR Register</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_n0_ha.xml b/xml/p10/node_cfir_n0_ha.xml
new file mode 100644
index 0000000..496223f
--- /dev/null
+++ b/xml/p10/node_cfir_n0_ha.xml
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_N0_HA" reg_type="SCOM">
+ <register name="CFIR_N0_HOSTATTN">
+ <instance addr="0x02040004" reg_inst="0"/>
+ </register>
+ <register name="CFIR_N0_HOSTATTN_MASK">
+ <instance addr="0x02040044" reg_inst="0"/>
+ </register>
+ <rule attn_type="HA" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_N0_HOSTATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_N0_HOSTATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="N0_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_n0_spa.xml b/xml/p10/node_cfir_n0_spa.xml
new file mode 100644
index 0000000..573d748
--- /dev/null
+++ b/xml/p10/node_cfir_n0_spa.xml
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_N0_SPA" reg_type="SCOM">
+ <register name="CFIR_N0_SPATTN">
+ <instance addr="0x02040002" reg_inst="0"/>
+ </register>
+ <register name="CFIR_N0_SPATTN_MASK">
+ <instance addr="0x02040042" reg_inst="0"/>
+ </register>
+ <rule attn_type="SPA" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_N0_SPATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_N0_SPATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="N0_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
+ <bit child_node="INT_CQ_FIR" node_inst="0" pos="7">Primary Error Register for INT_CQ. This contains all of the individual errors detected by INT_CQ, plus summary error indicators from VC and PC (see bits 43:63).</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_n0_ucs.xml b/xml/p10/node_cfir_n0_ucs.xml
new file mode 100644
index 0000000..6fe76a4
--- /dev/null
+++ b/xml/p10/node_cfir_n0_ucs.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_N0_UCS" reg_type="SCOM">
+ <register name="CFIR_N0_LOCAL_XSTOP">
+ <instance addr="0x02040003" reg_inst="0"/>
+ </register>
+ <register name="CFIR_N0_LOCAL_XSTOP_MASK">
+ <instance addr="0x02040043" reg_inst="0"/>
+ </register>
+ <rule attn_type="UCS" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_N0_LOCAL_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_N0_LOCAL_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="N0_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
+ <bit child_node="NMMU_CQ_FIR" node_inst="0" pos="5">PBI CQ FIR Register</bit>
+ <bit child_node="NMMU_FIR" node_inst="0" pos="6">NMMU FIR1 Register</bit>
+ <bit child_node="VAS_FIR" node_inst="0" pos="8">Local FIR register for the VAS unit logic</bit>
+ <bit child_node="NX_DMA_ENG_FIR" node_inst="0" pos="9">DMA and Engine Fault Isolation Register</bit>
+ <bit child_node="NX_CQ_FIR" node_inst="0" pos="10">PBI CQ FIR Register</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_n1_cs.xml b/xml/p10/node_cfir_n1_cs.xml
new file mode 100644
index 0000000..c5492b1
--- /dev/null
+++ b/xml/p10/node_cfir_n1_cs.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_N1_CS" reg_type="SCOM">
+ <register name="CFIR_N1_XSTOP">
+ <instance addr="0x03040000" reg_inst="0"/>
+ </register>
+ <register name="CFIR_N1_XSTOP_MASK">
+ <instance addr="0x03040040" reg_inst="0"/>
+ </register>
+ <rule attn_type="CS" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_N1_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_N1_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="N1_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
+ <bit child_node="NMMU_CQ_FIR" node_inst="1" pos="5">PBI CQ FIR Register</bit>
+ <bit child_node="NMMU_FIR" node_inst="1" pos="6">NMMU FIR1 Register</bit>
+ <bit child_node="MCD_FIR" node_inst="0" pos="7">Local FIR register for MCD</bit>
+ <bit child_node="HCA_FIR" node_inst="0" pos="9">HCA Fault Isolation Register</bit>
+ <bit child_node="LPC_FIR" node_inst="0" pos="11">PBAM low sped part FIR Register</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="0" pos="13">PCI Nest FIR Register</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="1" pos="14">PCI Nest FIR Register</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="2" pos="15">PCI Nest FIR Register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="4" pos="17">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="5" pos="18">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="6" pos="19">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="7" pos="20">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="8" pos="21">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="9" pos="22">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="10" pos="23">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="11" pos="24">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="0" pos="25">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="1" pos="26">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="2" pos="27">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="3" pos="28">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="12" pos="29">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="13" pos="30">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="14" pos="31">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="15" pos="32">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_EXT_FIR" node_inst="0" pos="33">PowerBus EH EXTFIR register</bit>
+ <bit child_node="PSIHB_FIR" node_inst="0" pos="38">PSI Host Bridge FIR Register</bit>
+ <bit child_node="PBAF_FIR" node_inst="0" pos="39">PBA Local Fault Isolation Register. Register bits are set for any error condition detected by the PBA. The PBAFIR will freeze upon logging the first error not masked in PBAFIRMASK.</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_n1_ha.xml b/xml/p10/node_cfir_n1_ha.xml
new file mode 100644
index 0000000..8dd5dd7
--- /dev/null
+++ b/xml/p10/node_cfir_n1_ha.xml
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_N1_HA" reg_type="SCOM">
+ <register name="CFIR_N1_HOSTATTN">
+ <instance addr="0x03040004" reg_inst="0"/>
+ </register>
+ <register name="CFIR_N1_HOSTATTN_MASK">
+ <instance addr="0x03040044" reg_inst="0"/>
+ </register>
+ <rule attn_type="HA" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_N1_HOSTATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_N1_HOSTATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="N1_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_n1_re.xml b/xml/p10/node_cfir_n1_re.xml
new file mode 100644
index 0000000..d565d0e
--- /dev/null
+++ b/xml/p10/node_cfir_n1_re.xml
@@ -0,0 +1,45 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_N1_RE" reg_type="SCOM">
+ <register name="CFIR_N1_RECOV">
+ <instance addr="0x03040001" reg_inst="0"/>
+ </register>
+ <register name="CFIR_N1_RECOV_MASK">
+ <instance addr="0x03040041" reg_inst="0"/>
+ </register>
+ <rule attn_type="RE" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_N1_RECOV"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_N1_RECOV_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="N1_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
+ <bit child_node="NMMU_CQ_FIR" node_inst="1" pos="5">PBI CQ FIR Register</bit>
+ <bit child_node="NMMU_FIR" node_inst="1" pos="6">NMMU FIR1 Register</bit>
+ <bit child_node="MCD_FIR" node_inst="0" pos="7">Local FIR register for MCD</bit>
+ <bit child_node="HCA_FIR" node_inst="0" pos="9">HCA Fault Isolation Register</bit>
+ <bit child_node="LPC_FIR" node_inst="0" pos="11">PBAM low sped part FIR Register</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="0" pos="13">PCI Nest FIR Register</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="1" pos="14">PCI Nest FIR Register</bit>
+ <bit child_node="PCI_NEST_FIR" node_inst="2" pos="15">PCI Nest FIR Register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="4" pos="17">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="5" pos="18">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="6" pos="19">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="7" pos="20">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="8" pos="21">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="9" pos="22">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="10" pos="23">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="11" pos="24">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="0" pos="25">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="1" pos="26">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="2" pos="27">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="3" pos="28">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="12" pos="29">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="13" pos="30">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="14" pos="31">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="15" pos="32">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PSIHB_FIR" node_inst="0" pos="38">PSI Host Bridge FIR Register</bit>
+ <bit child_node="PBAF_FIR" node_inst="0" pos="39">PBA Local Fault Isolation Register. Register bits are set for any error condition detected by the PBA. The PBAFIR will freeze upon logging the first error not masked in PBAFIRMASK.</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_n1_spa.xml b/xml/p10/node_cfir_n1_spa.xml
new file mode 100644
index 0000000..d7a2ca7
--- /dev/null
+++ b/xml/p10/node_cfir_n1_spa.xml
@@ -0,0 +1,36 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_N1_SPA" reg_type="SCOM">
+ <register name="CFIR_N1_SPATTN">
+ <instance addr="0x03040002" reg_inst="0"/>
+ </register>
+ <register name="CFIR_N1_SPATTN_MASK">
+ <instance addr="0x03040042" reg_inst="0"/>
+ </register>
+ <rule attn_type="SPA" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_N1_SPATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_N1_SPATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="N1_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
+ <bit child_node="MCD_FIR" node_inst="0" pos="7">Local FIR register for MCD</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="4" pos="17">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="5" pos="18">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="6" pos="19">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="7" pos="20">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="8" pos="21">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="9" pos="22">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="10" pos="23">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="11" pos="24">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="0" pos="25">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="1" pos="26">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="2" pos="27">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="3" pos="28">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="12" pos="29">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="13" pos="30">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="14" pos="31">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+ <bit child_node="PB_STATION_FIR" node_inst="15" pos="32">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_n1_ucs.xml b/xml/p10/node_cfir_n1_ucs.xml
new file mode 100644
index 0000000..11220f3
--- /dev/null
+++ b/xml/p10/node_cfir_n1_ucs.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_N1_UCS" reg_type="SCOM">
+ <register name="CFIR_N1_LOCAL_XSTOP">
+ <instance addr="0x03040003" reg_inst="0"/>
+ </register>
+ <register name="CFIR_N1_LOCAL_XSTOP_MASK">
+ <instance addr="0x03040043" reg_inst="0"/>
+ </register>
+ <rule attn_type="UCS" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_N1_LOCAL_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_N1_LOCAL_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="N1_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
+ <bit child_node="NMMU_CQ_FIR" node_inst="1" pos="5">PBI CQ FIR Register</bit>
+ <bit child_node="NMMU_FIR" node_inst="1" pos="6">NMMU FIR1 Register</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_paue_cs_re.xml b/xml/p10/node_cfir_paue_cs_re.xml
new file mode 100644
index 0000000..a1bcb5a
--- /dev/null
+++ b/xml/p10/node_cfir_paue_cs_re.xml
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PAUE_CS_RE" reg_type="SCOM">
+ <register name="CFIR_PAUE_XSTOP">
+ <instance addr="0x10040000" reg_inst="0"/>
+ <instance addr="0x11040000" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PAUE_XSTOP_MASK">
+ <instance addr="0x10040040" reg_inst="0"/>
+ <instance addr="0x11040040" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PAUE_RECOV">
+ <instance addr="0x10040001" reg_inst="0"/>
+ <instance addr="0x11040001" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PAUE_RECOV_MASK">
+ <instance addr="0x10040041" reg_inst="0"/>
+ <instance addr="0x11040041" reg_inst="1"/>
+ </register>
+ <rule attn_type="CS" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PAUE_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PAUE_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <rule attn_type="RE" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PAUE_RECOV"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PAUE_RECOV_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
+ <bit child_node="PAU_FIR_0" node_inst="0,3" pos="5">Local FIR register for the PAU (1 of 3)</bit>
+ <bit child_node="PAU_FIR_1" node_inst="0,3" pos="6">Local FIR register for the PAU (2 of 3)</bit>
+ <bit child_node="PAU_FIR_2" node_inst="0,3" pos="7">Local FIR register for the PAU (3 of 3)</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Local FIR register for the chip pervasive logic</bit>
+ <bit child_node="PAU_DL_FIR" node_inst="0,1" pos="14">Local FIR register for the chip pervasive logic</bit>
+ <bit child_node="PAU_PTL_FIR" node_inst="0,1" pos="16"/>
+</attn_node>
diff --git a/xml/p10/node_cfir_paue_ha.xml b/xml/p10/node_cfir_paue_ha.xml
new file mode 100644
index 0000000..fe5fc3d
--- /dev/null
+++ b/xml/p10/node_cfir_paue_ha.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PAUE_HA" reg_type="SCOM">
+ <register name="CFIR_PAUE_HOSTATTN">
+ <instance addr="0x10040004" reg_inst="0"/>
+ <instance addr="0x11040004" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PAUE_HOSTATTN_MASK">
+ <instance addr="0x10040044" reg_inst="0"/>
+ <instance addr="0x11040044" reg_inst="1"/>
+ </register>
+ <rule attn_type="HA" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PAUE_HOSTATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PAUE_HOSTATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_paue_spa.xml b/xml/p10/node_cfir_paue_spa.xml
new file mode 100644
index 0000000..b173b23
--- /dev/null
+++ b/xml/p10/node_cfir_paue_spa.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PAUE_SPA" reg_type="SCOM">
+ <register name="CFIR_PAUE_SPATTN">
+ <instance addr="0x10040002" reg_inst="0"/>
+ <instance addr="0x11040002" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PAUE_SPATTN_MASK">
+ <instance addr="0x10040042" reg_inst="0"/>
+ <instance addr="0x11040042" reg_inst="1"/>
+ </register>
+ <rule attn_type="SPA" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PAUE_SPATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PAUE_SPATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Local FIR register for the chip pervasive logic</bit>
+ <bit child_node="PAU_DL_FIR" node_inst="0,1" pos="14">Local FIR register for the chip pervasive logic</bit>
+ <bit child_node="PAU_PTL_FIR" node_inst="0,1" pos="16"/>
+</attn_node>
diff --git a/xml/p10/node_cfir_paue_ucs.xml b/xml/p10/node_cfir_paue_ucs.xml
new file mode 100644
index 0000000..efac4df
--- /dev/null
+++ b/xml/p10/node_cfir_paue_ucs.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PAUE_UCS" reg_type="SCOM">
+ <register name="CFIR_PAUE_LOCAL_XSTOP">
+ <instance addr="0x10040003" reg_inst="0"/>
+ <instance addr="0x11040003" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PAUE_LOCAL_XSTOP_MASK">
+ <instance addr="0x10040043" reg_inst="0"/>
+ <instance addr="0x11040043" reg_inst="1"/>
+ </register>
+ <rule attn_type="UCS" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PAUE_LOCAL_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PAUE_LOCAL_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
+ <bit child_node="PAU_FIR_0" node_inst="0,3" pos="5">Local FIR register for the PAU (1 of 3)</bit>
+ <bit child_node="PAU_FIR_1" node_inst="0,3" pos="6">Local FIR register for the PAU (2 of 3)</bit>
+ <bit child_node="PAU_FIR_2" node_inst="0,3" pos="7">Local FIR register for the PAU (3 of 3)</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Local FIR register for the chip pervasive logic</bit>
+ <bit child_node="PAU_DL_FIR" node_inst="0,1" pos="14">Local FIR register for the chip pervasive logic</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_pauw_cs_re.xml b/xml/p10/node_cfir_pauw_cs_re.xml
new file mode 100644
index 0000000..73a16cb
--- /dev/null
+++ b/xml/p10/node_cfir_pauw_cs_re.xml
@@ -0,0 +1,47 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PAUW_CS_RE" reg_type="SCOM">
+ <register name="CFIR_PAUW_XSTOP">
+ <instance addr="0x12040000" reg_inst="0"/>
+ <instance addr="0x13040000" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PAUW_XSTOP_MASK">
+ <instance addr="0x12040040" reg_inst="0"/>
+ <instance addr="0x13040040" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PAUW_RECOV">
+ <instance addr="0x12040001" reg_inst="0"/>
+ <instance addr="0x13040001" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PAUW_RECOV_MASK">
+ <instance addr="0x12040041" reg_inst="0"/>
+ <instance addr="0x13040041" reg_inst="1"/>
+ </register>
+ <rule attn_type="CS" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PAUW_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PAUW_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <rule attn_type="RE" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PAUW_RECOV"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PAUW_RECOV_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Local FIR</bit>
+ <bit child_node="PAU_FIR_0" node_inst="4,6" pos="5">Local FIR register for the PAU (1 of 3)</bit>
+ <bit child_node="PAU_FIR_1" node_inst="4,6" pos="6">Local FIR register for the PAU (2 of 3)</bit>
+ <bit child_node="PAU_FIR_2" node_inst="4,6" pos="7">Local FIR register for the PAU (3 of 3)</bit>
+ <bit child_node="PAU_FIR_0" node_inst="5,7" pos="9">Local FIR register for the PAU (1 of 3)</bit>
+ <bit child_node="PAU_FIR_1" node_inst="5,7" pos="10">Local FIR register for the PAU (2 of 3)</bit>
+ <bit child_node="PAU_FIR_2" node_inst="5,7" pos="11">Local FIR register for the PAU (3 of 3)</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Local FIR register for the chip pervasive logic</bit>
+ <bit child_node="PAU_DL_FIR" node_inst="2,3" pos="14">Local FIR register for the chip pervasive logic</bit>
+ <bit child_node="PAU_PTL_FIR" node_inst="2,3" pos="16"/>
+</attn_node>
diff --git a/xml/p10/node_cfir_pauw_ha.xml b/xml/p10/node_cfir_pauw_ha.xml
new file mode 100644
index 0000000..e9090eb
--- /dev/null
+++ b/xml/p10/node_cfir_pauw_ha.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PAUW_HA" reg_type="SCOM">
+ <register name="CFIR_PAUW_HOSTATTN">
+ <instance addr="0x12040004" reg_inst="0"/>
+ <instance addr="0x13040004" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PAUW_HOSTATTN_MASK">
+ <instance addr="0x12040044" reg_inst="0"/>
+ <instance addr="0x13040044" reg_inst="1"/>
+ </register>
+ <rule attn_type="HA" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PAUW_HOSTATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PAUW_HOSTATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Local FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_pauw_spa.xml b/xml/p10/node_cfir_pauw_spa.xml
new file mode 100644
index 0000000..95df6ad
--- /dev/null
+++ b/xml/p10/node_cfir_pauw_spa.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PAUW_SPA" reg_type="SCOM">
+ <register name="CFIR_PAUW_SPATTN">
+ <instance addr="0x12040002" reg_inst="0"/>
+ <instance addr="0x13040002" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PAUW_SPATTN_MASK">
+ <instance addr="0x12040042" reg_inst="0"/>
+ <instance addr="0x13040042" reg_inst="1"/>
+ </register>
+ <rule attn_type="SPA" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PAUW_SPATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PAUW_SPATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Local FIR</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Local FIR register for the chip pervasive logic</bit>
+ <bit child_node="PAU_DL_FIR" node_inst="2,3" pos="14">Local FIR register for the chip pervasive logic</bit>
+ <bit child_node="PAU_PTL_FIR" node_inst="2,3" pos="16"/>
+</attn_node>
diff --git a/xml/p10/node_cfir_pauw_ucs.xml b/xml/p10/node_cfir_pauw_ucs.xml
new file mode 100644
index 0000000..f52277a
--- /dev/null
+++ b/xml/p10/node_cfir_pauw_ucs.xml
@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PAUW_UCS" reg_type="SCOM">
+ <register name="CFIR_PAUW_LOCAL_XSTOP">
+ <instance addr="0x12040003" reg_inst="0"/>
+ <instance addr="0x13040003" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PAUW_LOCAL_XSTOP_MASK">
+ <instance addr="0x12040043" reg_inst="0"/>
+ <instance addr="0x13040043" reg_inst="1"/>
+ </register>
+ <rule attn_type="UCS" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PAUW_LOCAL_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PAUW_LOCAL_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Local FIR</bit>
+ <bit child_node="PAU_FIR_0" node_inst="4,6" pos="5">Local FIR register for the PAU (1 of 3)</bit>
+ <bit child_node="PAU_FIR_1" node_inst="4,6" pos="6">Local FIR register for the PAU (2 of 3)</bit>
+ <bit child_node="PAU_FIR_2" node_inst="4,6" pos="7">Local FIR register for the PAU (3 of 3)</bit>
+ <bit child_node="PAU_FIR_0" node_inst="5,7" pos="9">Local FIR register for the PAU (1 of 3)</bit>
+ <bit child_node="PAU_FIR_1" node_inst="5,7" pos="10">Local FIR register for the PAU (2 of 3)</bit>
+ <bit child_node="PAU_FIR_2" node_inst="5,7" pos="11">Local FIR register for the PAU (3 of 3)</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Local FIR register for the chip pervasive logic</bit>
+ <bit child_node="PAU_DL_FIR" node_inst="2,3" pos="14">Local FIR register for the chip pervasive logic</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_pci_cs_re.xml b/xml/p10/node_cfir_pci_cs_re.xml
new file mode 100644
index 0000000..f13a754
--- /dev/null
+++ b/xml/p10/node_cfir_pci_cs_re.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PCI_CS_RE" reg_type="SCOM">
+ <register name="CFIR_PCI_XSTOP">
+ <instance addr="0x08040000" reg_inst="0"/>
+ <instance addr="0x09040000" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PCI_XSTOP_MASK">
+ <instance addr="0x08040040" reg_inst="0"/>
+ <instance addr="0x09040040" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PCI_RECOV">
+ <instance addr="0x08040001" reg_inst="0"/>
+ <instance addr="0x09040001" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PCI_RECOV_MASK">
+ <instance addr="0x08040041" reg_inst="0"/>
+ <instance addr="0x09040041" reg_inst="1"/>
+ </register>
+ <rule attn_type="CS" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PCI_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PCI_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <rule attn_type="RE" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PCI_RECOV"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PCI_RECOV_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="PCI_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
+ <bit child_node="PCI_ETU_FIR" node_inst="0,3" pos="5">ETU FIR Register</bit>
+ <bit child_node="PCI_ETU_FIR" node_inst="1,4" pos="6">ETU FIR Register</bit>
+ <bit child_node="PCI_ETU_FIR" node_inst="2,5" pos="7">ETU FIR Register</bit>
+ <bit child_node="PCI_FIR" node_inst="0,3" pos="9">PCI FIR Register</bit>
+ <bit child_node="PCI_FIR" node_inst="1,4" pos="10">PCI FIR Register</bit>
+ <bit child_node="PCI_FIR" node_inst="2,5" pos="11">PCI FIR Register</bit>
+ <bit child_node="PCI_IOP_FIR" node_inst="0,2" pos="12">IOP Local Fault Isolation Register. Register bits are set for any error condition detected by the IOP. The IOPFIR will freeze upon logging the first error not masked in IOPMASK.</bit>
+ <bit child_node="PCI_IOP_FIR" node_inst="1,3" pos="13">IOP Local Fault Isolation Register. Register bits are set for any error condition detected by the IOP. The IOPFIR will freeze upon logging the first error not masked in IOPMASK.</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_pci_spa_ha.xml b/xml/p10/node_cfir_pci_spa_ha.xml
new file mode 100644
index 0000000..1487b89
--- /dev/null
+++ b/xml/p10/node_cfir_pci_spa_ha.xml
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PCI_SPA_HA" reg_type="SCOM">
+ <register name="CFIR_PCI_SPATTN">
+ <instance addr="0x08040002" reg_inst="0"/>
+ <instance addr="0x09040002" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PCI_SPATTN_MASK">
+ <instance addr="0x08040042" reg_inst="0"/>
+ <instance addr="0x09040042" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PCI_HOSTATTN">
+ <instance addr="0x08040004" reg_inst="0"/>
+ <instance addr="0x09040004" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PCI_HOSTATTN_MASK">
+ <instance addr="0x08040044" reg_inst="0"/>
+ <instance addr="0x09040044" reg_inst="1"/>
+ </register>
+ <rule attn_type="SPA" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PCI_SPATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PCI_SPATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <rule attn_type="HA" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PCI_HOSTATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PCI_HOSTATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="PCI_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_pci_ucs.xml b/xml/p10/node_cfir_pci_ucs.xml
new file mode 100644
index 0000000..fc91dff
--- /dev/null
+++ b/xml/p10/node_cfir_pci_ucs.xml
@@ -0,0 +1,23 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PCI_UCS" reg_type="SCOM">
+ <register name="CFIR_PCI_LOCAL_XSTOP">
+ <instance addr="0x08040003" reg_inst="0"/>
+ <instance addr="0x09040003" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PCI_LOCAL_XSTOP_MASK">
+ <instance addr="0x08040043" reg_inst="0"/>
+ <instance addr="0x09040043" reg_inst="1"/>
+ </register>
+ <rule attn_type="UCS" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PCI_LOCAL_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PCI_LOCAL_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="PCI_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
+ <bit child_node="PCI_IOP_FIR" node_inst="0,2" pos="12">IOP Local Fault Isolation Register. Register bits are set for any error condition detected by the IOP. The IOPFIR will freeze upon logging the first error not masked in IOPMASK.</bit>
+ <bit child_node="PCI_IOP_FIR" node_inst="1,3" pos="13">IOP Local Fault Isolation Register. Register bits are set for any error condition detected by the IOP. The IOPFIR will freeze upon logging the first error not masked in IOPMASK.</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_tp_cs_re.xml b/xml/p10/node_cfir_tp_cs_re.xml
new file mode 100644
index 0000000..2117513
--- /dev/null
+++ b/xml/p10/node_cfir_tp_cs_re.xml
@@ -0,0 +1,36 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_TP_CS_RE" reg_type="SCOM">
+ <register name="CFIR_TP_XSTOP">
+ <instance addr="0x01040000" reg_inst="0"/>
+ </register>
+ <register name="CFIR_TP_XSTOP_MASK">
+ <instance addr="0x01040040" reg_inst="0"/>
+ </register>
+ <register name="CFIR_TP_RECOV">
+ <instance addr="0x01040001" reg_inst="0"/>
+ </register>
+ <register name="CFIR_TP_RECOV_MASK">
+ <instance addr="0x01040041" reg_inst="0"/>
+ </register>
+ <rule attn_type="CS" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_TP_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_TP_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <rule attn_type="RE" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_TP_RECOV"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_TP_RECOV_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="TP_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
+ <bit child_node="OCC_FIR" node_inst="0" pos="5">OCC Local Fault Isolation Register</bit>
+ <bit child_node="PBAO_FIR" node_inst="0" pos="6">PBA Local Fault Isolation Register. Register bits are set for any error condition detected by the PBA. The PBAFIR will freeze upon logging the first error not masked in PBAFIRMASK.</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_tp_spa_ucs_ha.xml b/xml/p10/node_cfir_tp_spa_ucs_ha.xml
new file mode 100644
index 0000000..fc2dd4e
--- /dev/null
+++ b/xml/p10/node_cfir_tp_spa_ucs_ha.xml
@@ -0,0 +1,49 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_TP_SPA_UCS_HA" reg_type="SCOM">
+ <register name="CFIR_TP_SPATTN">
+ <instance addr="0x01040002" reg_inst="0"/>
+ </register>
+ <register name="CFIR_TP_SPATTN_MASK">
+ <instance addr="0x01040042" reg_inst="0"/>
+ </register>
+ <register name="CFIR_TP_LOCAL_XSTOP">
+ <instance addr="0x01040003" reg_inst="0"/>
+ </register>
+ <register name="CFIR_TP_LOCAL_XSTOP_MASK">
+ <instance addr="0x01040043" reg_inst="0"/>
+ </register>
+ <register name="CFIR_TP_HOSTATTN">
+ <instance addr="0x01040004" reg_inst="0"/>
+ </register>
+ <register name="CFIR_TP_HOSTATTN_MASK">
+ <instance addr="0x01040044" reg_inst="0"/>
+ </register>
+ <rule attn_type="SPA" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_TP_SPATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_TP_SPATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <rule attn_type="UCS" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_TP_LOCAL_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_TP_LOCAL_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <rule attn_type="HA" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_TP_HOSTATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_TP_HOSTATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="TP_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_eq_core_fir.xml b/xml/p10/node_eq_core_fir.xml
new file mode 100644
index 0000000..4125951
--- /dev/null
+++ b/xml/p10/node_eq_core_fir.xml
@@ -0,0 +1,276 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="EQ_CORE_FIR" reg_type="SCOM">
+ <register name="EQ_CORE_FIR">
+ <instance addr="0x20028440" reg_inst="0"/>
+ <instance addr="0x20024440" reg_inst="1"/>
+ <instance addr="0x20022440" reg_inst="2"/>
+ <instance addr="0x20021440" reg_inst="3"/>
+ <instance addr="0x21028440" reg_inst="4"/>
+ <instance addr="0x21024440" reg_inst="5"/>
+ <instance addr="0x21022440" reg_inst="6"/>
+ <instance addr="0x21021440" reg_inst="7"/>
+ <instance addr="0x22028440" reg_inst="8"/>
+ <instance addr="0x22024440" reg_inst="9"/>
+ <instance addr="0x22022440" reg_inst="10"/>
+ <instance addr="0x22021440" reg_inst="11"/>
+ <instance addr="0x23028440" reg_inst="12"/>
+ <instance addr="0x23024440" reg_inst="13"/>
+ <instance addr="0x23022440" reg_inst="14"/>
+ <instance addr="0x23021440" reg_inst="15"/>
+ <instance addr="0x24028440" reg_inst="16"/>
+ <instance addr="0x24024440" reg_inst="17"/>
+ <instance addr="0x24022440" reg_inst="18"/>
+ <instance addr="0x24021440" reg_inst="19"/>
+ <instance addr="0x25028440" reg_inst="20"/>
+ <instance addr="0x25024440" reg_inst="21"/>
+ <instance addr="0x25022440" reg_inst="22"/>
+ <instance addr="0x25021440" reg_inst="23"/>
+ <instance addr="0x26028440" reg_inst="24"/>
+ <instance addr="0x26024440" reg_inst="25"/>
+ <instance addr="0x26022440" reg_inst="26"/>
+ <instance addr="0x26021440" reg_inst="27"/>
+ <instance addr="0x27028440" reg_inst="28"/>
+ <instance addr="0x27024440" reg_inst="29"/>
+ <instance addr="0x27022440" reg_inst="30"/>
+ <instance addr="0x27021440" reg_inst="31"/>
+ </register>
+ <register name="EQ_CORE_FIR_MASK">
+ <instance addr="0x20028443" reg_inst="0"/>
+ <instance addr="0x20024443" reg_inst="1"/>
+ <instance addr="0x20022443" reg_inst="2"/>
+ <instance addr="0x20021443" reg_inst="3"/>
+ <instance addr="0x21028443" reg_inst="4"/>
+ <instance addr="0x21024443" reg_inst="5"/>
+ <instance addr="0x21022443" reg_inst="6"/>
+ <instance addr="0x21021443" reg_inst="7"/>
+ <instance addr="0x22028443" reg_inst="8"/>
+ <instance addr="0x22024443" reg_inst="9"/>
+ <instance addr="0x22022443" reg_inst="10"/>
+ <instance addr="0x22021443" reg_inst="11"/>
+ <instance addr="0x23028443" reg_inst="12"/>
+ <instance addr="0x23024443" reg_inst="13"/>
+ <instance addr="0x23022443" reg_inst="14"/>
+ <instance addr="0x23021443" reg_inst="15"/>
+ <instance addr="0x24028443" reg_inst="16"/>
+ <instance addr="0x24024443" reg_inst="17"/>
+ <instance addr="0x24022443" reg_inst="18"/>
+ <instance addr="0x24021443" reg_inst="19"/>
+ <instance addr="0x25028443" reg_inst="20"/>
+ <instance addr="0x25024443" reg_inst="21"/>
+ <instance addr="0x25022443" reg_inst="22"/>
+ <instance addr="0x25021443" reg_inst="23"/>
+ <instance addr="0x26028443" reg_inst="24"/>
+ <instance addr="0x26024443" reg_inst="25"/>
+ <instance addr="0x26022443" reg_inst="26"/>
+ <instance addr="0x26021443" reg_inst="27"/>
+ <instance addr="0x27028443" reg_inst="28"/>
+ <instance addr="0x27024443" reg_inst="29"/>
+ <instance addr="0x27022443" reg_inst="30"/>
+ <instance addr="0x27021443" reg_inst="31"/>
+ </register>
+ <register name="EQ_CORE_FIR_ACT0">
+ <instance addr="0x20028446" reg_inst="0"/>
+ <instance addr="0x20024446" reg_inst="1"/>
+ <instance addr="0x20022446" reg_inst="2"/>
+ <instance addr="0x20021446" reg_inst="3"/>
+ <instance addr="0x21028446" reg_inst="4"/>
+ <instance addr="0x21024446" reg_inst="5"/>
+ <instance addr="0x21022446" reg_inst="6"/>
+ <instance addr="0x21021446" reg_inst="7"/>
+ <instance addr="0x22028446" reg_inst="8"/>
+ <instance addr="0x22024446" reg_inst="9"/>
+ <instance addr="0x22022446" reg_inst="10"/>
+ <instance addr="0x22021446" reg_inst="11"/>
+ <instance addr="0x23028446" reg_inst="12"/>
+ <instance addr="0x23024446" reg_inst="13"/>
+ <instance addr="0x23022446" reg_inst="14"/>
+ <instance addr="0x23021446" reg_inst="15"/>
+ <instance addr="0x24028446" reg_inst="16"/>
+ <instance addr="0x24024446" reg_inst="17"/>
+ <instance addr="0x24022446" reg_inst="18"/>
+ <instance addr="0x24021446" reg_inst="19"/>
+ <instance addr="0x25028446" reg_inst="20"/>
+ <instance addr="0x25024446" reg_inst="21"/>
+ <instance addr="0x25022446" reg_inst="22"/>
+ <instance addr="0x25021446" reg_inst="23"/>
+ <instance addr="0x26028446" reg_inst="24"/>
+ <instance addr="0x26024446" reg_inst="25"/>
+ <instance addr="0x26022446" reg_inst="26"/>
+ <instance addr="0x26021446" reg_inst="27"/>
+ <instance addr="0x27028446" reg_inst="28"/>
+ <instance addr="0x27024446" reg_inst="29"/>
+ <instance addr="0x27022446" reg_inst="30"/>
+ <instance addr="0x27021446" reg_inst="31"/>
+ </register>
+ <register name="EQ_CORE_FIR_ACT1">
+ <instance addr="0x20028447" reg_inst="0"/>
+ <instance addr="0x20024447" reg_inst="1"/>
+ <instance addr="0x20022447" reg_inst="2"/>
+ <instance addr="0x20021447" reg_inst="3"/>
+ <instance addr="0x21028447" reg_inst="4"/>
+ <instance addr="0x21024447" reg_inst="5"/>
+ <instance addr="0x21022447" reg_inst="6"/>
+ <instance addr="0x21021447" reg_inst="7"/>
+ <instance addr="0x22028447" reg_inst="8"/>
+ <instance addr="0x22024447" reg_inst="9"/>
+ <instance addr="0x22022447" reg_inst="10"/>
+ <instance addr="0x22021447" reg_inst="11"/>
+ <instance addr="0x23028447" reg_inst="12"/>
+ <instance addr="0x23024447" reg_inst="13"/>
+ <instance addr="0x23022447" reg_inst="14"/>
+ <instance addr="0x23021447" reg_inst="15"/>
+ <instance addr="0x24028447" reg_inst="16"/>
+ <instance addr="0x24024447" reg_inst="17"/>
+ <instance addr="0x24022447" reg_inst="18"/>
+ <instance addr="0x24021447" reg_inst="19"/>
+ <instance addr="0x25028447" reg_inst="20"/>
+ <instance addr="0x25024447" reg_inst="21"/>
+ <instance addr="0x25022447" reg_inst="22"/>
+ <instance addr="0x25021447" reg_inst="23"/>
+ <instance addr="0x26028447" reg_inst="24"/>
+ <instance addr="0x26024447" reg_inst="25"/>
+ <instance addr="0x26022447" reg_inst="26"/>
+ <instance addr="0x26021447" reg_inst="27"/>
+ <instance addr="0x27028447" reg_inst="28"/>
+ <instance addr="0x27024447" reg_inst="29"/>
+ <instance addr="0x27022447" reg_inst="30"/>
+ <instance addr="0x27021447" reg_inst="31"/>
+ </register>
+ <register name="EQ_CORE_FIR_WOF">
+ <instance addr="0x20028448" reg_inst="0"/>
+ <instance addr="0x20024448" reg_inst="1"/>
+ <instance addr="0x20022448" reg_inst="2"/>
+ <instance addr="0x20021448" reg_inst="3"/>
+ <instance addr="0x21028448" reg_inst="4"/>
+ <instance addr="0x21024448" reg_inst="5"/>
+ <instance addr="0x21022448" reg_inst="6"/>
+ <instance addr="0x21021448" reg_inst="7"/>
+ <instance addr="0x22028448" reg_inst="8"/>
+ <instance addr="0x22024448" reg_inst="9"/>
+ <instance addr="0x22022448" reg_inst="10"/>
+ <instance addr="0x22021448" reg_inst="11"/>
+ <instance addr="0x23028448" reg_inst="12"/>
+ <instance addr="0x23024448" reg_inst="13"/>
+ <instance addr="0x23022448" reg_inst="14"/>
+ <instance addr="0x23021448" reg_inst="15"/>
+ <instance addr="0x24028448" reg_inst="16"/>
+ <instance addr="0x24024448" reg_inst="17"/>
+ <instance addr="0x24022448" reg_inst="18"/>
+ <instance addr="0x24021448" reg_inst="19"/>
+ <instance addr="0x25028448" reg_inst="20"/>
+ <instance addr="0x25024448" reg_inst="21"/>
+ <instance addr="0x25022448" reg_inst="22"/>
+ <instance addr="0x25021448" reg_inst="23"/>
+ <instance addr="0x26028448" reg_inst="24"/>
+ <instance addr="0x26024448" reg_inst="25"/>
+ <instance addr="0x26022448" reg_inst="26"/>
+ <instance addr="0x26021448" reg_inst="27"/>
+ <instance addr="0x27028448" reg_inst="28"/>
+ <instance addr="0x27024448" reg_inst="29"/>
+ <instance addr="0x27022448" reg_inst="30"/>
+ <instance addr="0x27021448" reg_inst="31"/>
+ </register>
+ <rule attn_type="CS" node_inst="0:31">
+ <!-- FIR & ~MASK & ~ACT0 & ~ACT1 -->
+ <expr type="and">
+ <expr type="reg" value1="EQ_CORE_FIR"/>
+ <expr type="not">
+ <expr type="reg" value1="EQ_CORE_FIR_MASK"/>
+ </expr>
+ <expr type="not">
+ <expr type="reg" value1="EQ_CORE_FIR_ACT0"/>
+ </expr>
+ <expr type="not">
+ <expr type="reg" value1="EQ_CORE_FIR_ACT1"/>
+ </expr>
+ </expr>
+ </rule>
+ <rule attn_type="RE" node_inst="0:31">
+ <!-- WOF & ~MASK & ~ACT0 & ACT1 -->
+ <expr type="and">
+ <expr type="reg" value1="EQ_CORE_FIR_WOF"/>
+ <expr type="not">
+ <expr type="reg" value1="EQ_CORE_FIR_MASK"/>
+ </expr>
+ <expr type="not">
+ <expr type="reg" value1="EQ_CORE_FIR_ACT0"/>
+ </expr>
+ <expr type="reg" value1="EQ_CORE_FIR_ACT1"/>
+ </expr>
+ </rule>
+ <rule attn_type="UCS" node_inst="0:31">
+ <!-- FIR & ~MASK & ACT0 & ACT1 -->
+ <expr type="and">
+ <expr type="reg" value1="EQ_CORE_FIR"/>
+ <expr type="not">
+ <expr type="reg" value1="EQ_CORE_FIR_MASK"/>
+ </expr>
+ <expr type="reg" value1="EQ_CORE_FIR_ACT0"/>
+ <expr type="reg" value1="EQ_CORE_FIR_ACT1"/>
+ </expr>
+ </rule>
+ <bit pos="0">IFU SRAM recoverable error (ICACHE parity error, etc)</bit>
+ <bit pos="1">TC checkstop</bit>
+ <bit pos="2">IFU RegFile recoverable error</bit>
+ <bit pos="3">IFU RegFile core checkstop</bit>
+ <bit pos="4">IFU logic recoverable error</bit>
+ <bit pos="5">IFU logic core checkstop</bit>
+ <bit pos="6">reserved</bit>
+ <bit pos="7">VSU Inference Accumulator recoverable error</bit>
+ <bit pos="8">Recovery core checkstop</bit>
+ <bit pos="9">VSU Slice Targeted File (STF) recoverable error</bit>
+ <bit pos="10">reserved</bit>
+ <bit pos="11">ISU logic recoverable error</bit>
+ <bit pos="12">ISU logic core checkstop</bit>
+ <bit pos="13">ISU recoverable if not in MT window</bit>
+ <bit pos="14">MCHK received while ME=0 - non recoverable</bit>
+ <bit pos="15">UE from L2</bit>
+ <bit pos="16">Number of UEs from L2 above threshold</bit>
+ <bit pos="17">UE on CI load</bit>
+ <bit pos="18">MMU TLB parity recoverable error</bit>
+ <bit pos="19">MMU SLB parity recoverable error</bit>
+ <bit pos="20">reserved</bit>
+ <bit pos="21">MMU CXT recoverable error</bit>
+ <bit pos="22">MMU logic core checkstop</bit>
+ <bit pos="23">MMU system checkstop</bit>
+ <bit pos="24">VSU logic recoverable error</bit>
+ <bit pos="25">VSU logic core checkstop</bit>
+ <bit pos="26">Thread in maintenance mode and receives recovery request</bit>
+ <bit pos="27">reserved</bit>
+ <bit pos="28">PC system checkstop - Recoverable error received when recovery disabled</bit>
+ <bit pos="29">LSU SRAM recoverable error (DCACHE parity error, ERAT parity error, etc)</bit>
+ <bit pos="30">LSU set deleted</bit>
+ <bit pos="31">LSU RegFile recoverable error</bit>
+ <bit pos="32">LSU RegFile core checkstop</bit>
+ <bit pos="33">MMU TLB multi hit error occurred</bit>
+ <bit pos="34">MMU SLB multi hit error occurred</bit>
+ <bit pos="35">LSU ERAT multi hit error occurred</bit>
+ <bit pos="36">PC forward progress error</bit>
+ <bit pos="37">LSU logic recoverable error</bit>
+ <bit pos="38">LSU logic core checkstop</bit>
+ <bit pos="39">reserved</bit>
+ <bit pos="40">reserved</bit>
+ <bit pos="41">LSU system checkstop</bit>
+ <bit pos="42">reserved</bit>
+ <bit pos="43">PC thread hang recoverable error</bit>
+ <bit pos="44">reserved</bit>
+ <bit pos="45">PC logic checkstop</bit>
+ <bit pos="46">PC TimeBase Facility checkstop</bit>
+ <bit pos="47">PC TimeBase Facility checkstop</bit>
+ <bit pos="48">reserved</bit>
+ <bit pos="49">reserved</bit>
+ <bit pos="50">reserved</bit>
+ <bit pos="51">reserved</bit>
+ <bit pos="52">Hang Recovery Failed</bit>
+ <bit pos="53">Core Hang detected</bit>
+ <bit pos="54">reserved</bit>
+ <bit pos="55">Nest Hang detected</bit>
+ <bit pos="56">Other Core Chiplet recoverable error</bit>
+ <bit pos="57">Other Core Chiplet core checkstop</bit>
+ <bit pos="58">Other Core Chiplet system checkstop</bit>
+ <bit pos="59">SCOM satellite error detected</bit>
+ <bit pos="60">Debug Trigger error inject</bit>
+ <bit pos="61">SCOM or Firmware recoverable error inject</bit>
+ <bit pos="62">Firmware checkstop error inject</bit>
+ <bit pos="63">PHYP checkstop via SPRC/SPRD</bit>
+</attn_node>
diff --git a/xml/p10/node_eq_core_thread_state.xml b/xml/p10/node_eq_core_thread_state.xml
new file mode 100644
index 0000000..49a68d5
--- /dev/null
+++ b/xml/p10/node_eq_core_thread_state.xml
@@ -0,0 +1,66 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="EQ_CORE_THREAD_STATE" reg_type="SCOM">
+ <register name="CORE_THREAD_STATE">
+ <instance addr="0x20028412" reg_inst="0"/>
+ <instance addr="0x20024412" reg_inst="1"/>
+ <instance addr="0x20022412" reg_inst="2"/>
+ <instance addr="0x20021412" reg_inst="3"/>
+ <instance addr="0x21028412" reg_inst="4"/>
+ <instance addr="0x21024412" reg_inst="5"/>
+ <instance addr="0x21022412" reg_inst="6"/>
+ <instance addr="0x21021412" reg_inst="7"/>
+ <instance addr="0x22028412" reg_inst="8"/>
+ <instance addr="0x22024412" reg_inst="9"/>
+ <instance addr="0x22022412" reg_inst="10"/>
+ <instance addr="0x22021412" reg_inst="11"/>
+ <instance addr="0x23028412" reg_inst="12"/>
+ <instance addr="0x23024412" reg_inst="13"/>
+ <instance addr="0x23022412" reg_inst="14"/>
+ <instance addr="0x23021412" reg_inst="15"/>
+ <instance addr="0x24028412" reg_inst="16"/>
+ <instance addr="0x24024412" reg_inst="17"/>
+ <instance addr="0x24022412" reg_inst="18"/>
+ <instance addr="0x24021412" reg_inst="19"/>
+ <instance addr="0x25028412" reg_inst="20"/>
+ <instance addr="0x25024412" reg_inst="21"/>
+ <instance addr="0x25022412" reg_inst="22"/>
+ <instance addr="0x25021412" reg_inst="23"/>
+ <instance addr="0x26028412" reg_inst="24"/>
+ <instance addr="0x26024412" reg_inst="25"/>
+ <instance addr="0x26022412" reg_inst="26"/>
+ <instance addr="0x26021412" reg_inst="27"/>
+ <instance addr="0x27028412" reg_inst="28"/>
+ <instance addr="0x27024412" reg_inst="29"/>
+ <instance addr="0x27022412" reg_inst="30"/>
+ <instance addr="0x27021412" reg_inst="31"/>
+ </register>
+ <!-- Each EQ_SPATTN will only report 4 of the possible 8 threads back to the
+ CFIR_EQ_SPA. The reported threads are dependent on the core mode. In
+ Normal Core Mode (CORE_THREAD_STATE[63]=0), only threads 0-3 report to
+ the CFIR_EQ_SPA. In Fused Core Mode (CORE_THREAD_STATE[63]=1), both
+ EQ_SPATTN in the fused core pair display the exact same information for
+ all eight threads in the pair. However, only the even threads on the
+ even cores and the odd threads on the odd cores report to the
+ CFIR_EQ_SPA. -->
+ <rule attn_type="SPA" node_inst="0:31">
+ <!-- (~CORE_THREAD_STATE[63] << 63) | (CORE_THREAD_STATE[63] << 62) -->
+ <expr type="or">
+ <expr type="lshift" value1="63">
+ <expr type="and">
+ <expr type="not">
+ <expr type="reg" value1="CORE_THREAD_STATE"/>
+ </expr>
+ <expr type="int" value1="0x0000000000000001"/>
+ </expr>
+ </expr>
+ <expr type="lshift" value1="62">
+ <expr type="and">
+ <expr type="reg" value1="CORE_THREAD_STATE"/>
+ <expr type="int" value1="0x0000000000000001"/>
+ </expr>
+ </expr>
+ </expr>
+ </rule>
+ <bit child_node="EQ_SPATTN_NORMAL" node_inst="0:31" pos="0">EQ_SPATTN normal core mode</bit>
+ <bit child_node="EQ_SPATTN_FUSED" node_inst="0:31" pos="1">EQ_SPATTN fused core mode</bit>
+</attn_node>
diff --git a/xml/p10/node_eq_l2_fir.xml b/xml/p10/node_eq_l2_fir.xml
new file mode 100644
index 0000000..4256626
--- /dev/null
+++ b/xml/p10/node_eq_l2_fir.xml
@@ -0,0 +1,79 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="EQ_L2_FIR" reg_type="SCOM">
+ <local_fir config="" name="EQ_L2_FIR">
+ <instance addr="0x20028000" reg_inst="0"/>
+ <instance addr="0x20024000" reg_inst="1"/>
+ <instance addr="0x20022000" reg_inst="2"/>
+ <instance addr="0x20021000" reg_inst="3"/>
+ <instance addr="0x21028000" reg_inst="4"/>
+ <instance addr="0x21024000" reg_inst="5"/>
+ <instance addr="0x21022000" reg_inst="6"/>
+ <instance addr="0x21021000" reg_inst="7"/>
+ <instance addr="0x22028000" reg_inst="8"/>
+ <instance addr="0x22024000" reg_inst="9"/>
+ <instance addr="0x22022000" reg_inst="10"/>
+ <instance addr="0x22021000" reg_inst="11"/>
+ <instance addr="0x23028000" reg_inst="12"/>
+ <instance addr="0x23024000" reg_inst="13"/>
+ <instance addr="0x23022000" reg_inst="14"/>
+ <instance addr="0x23021000" reg_inst="15"/>
+ <instance addr="0x24028000" reg_inst="16"/>
+ <instance addr="0x24024000" reg_inst="17"/>
+ <instance addr="0x24022000" reg_inst="18"/>
+ <instance addr="0x24021000" reg_inst="19"/>
+ <instance addr="0x25028000" reg_inst="20"/>
+ <instance addr="0x25024000" reg_inst="21"/>
+ <instance addr="0x25022000" reg_inst="22"/>
+ <instance addr="0x25021000" reg_inst="23"/>
+ <instance addr="0x26028000" reg_inst="24"/>
+ <instance addr="0x26024000" reg_inst="25"/>
+ <instance addr="0x26022000" reg_inst="26"/>
+ <instance addr="0x26021000" reg_inst="27"/>
+ <instance addr="0x27028000" reg_inst="28"/>
+ <instance addr="0x27024000" reg_inst="29"/>
+ <instance addr="0x27022000" reg_inst="30"/>
+ <instance addr="0x27021000" reg_inst="31"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ </local_fir>
+ <bit pos="0">H/W Trigger Mechanism at point cache read occurs that detects a CE by ECCCK on RC/CO/SN read. Note: PRD counts the number of these and then will trigger LineDelete.</bit>
+ <bit pos="1">H/W Trigger Mechanism at point cache read occurs that detects a UE(non SUE) by ECCCK on RC/CO/SN read.</bit>
+ <bit pos="2">H/W Trigger Mechanism at point cache read occurs that detects a SUE by ECCCK on RC/CO/SN read.</bit>
+ <bit pos="3">H/W intiated Line Delete occured (Id state injected into the dir) by RC or SN machine.</bit>
+ <bit pos="4">L2 Castout where L2 cache read detected UE/SUE and Line is M,Mu,T,Tn</bit>
+ <bit pos="5">L2 Castout where L2 cache read detected UE/SUE and Line is Me,Te,Ten,Sl,S</bit>
+ <bit pos="6">L2 corrected a CE in the L2 directory</bit>
+ <bit pos="7">L2 detected a UE in the L2 directory</bit>
+ <bit pos="8">L2 detected a SBCE in the L2 directory</bit>
+ <bit pos="9">PEC attempted to repair and CO a SBCE condition but failed(eg CO disp failed). Cache line was lost.</bit>
+ <bit pos="10">DEPRICATED: THIS FIR BIT SHOULD ALWAYS BE MASKED. Multiple CE/UE deteceted between 2 hang 'early hang' pulse time window</bit>
+ <bit pos="11">LRU array has illegal valu in it(due to flipped bit)</bit>
+ <bit pos="12">RC timed out waiting for powerbus to return data.</bit>
+ <bit pos="13">NCU timed out waiting for powerbus to return data.</bit>
+ <bit pos="14">Internal h/w control error</bit>
+ <bit pos="15">All members in a single congruence class has been deleted</bit>
+ <bit pos="16">Cache Inhibited Ld/St hit a line in the L2 cache. SW error</bit>
+ <bit pos="17">RC was doing a fabric op on behalf of a load and got an cresp=addr_err</bit>
+ <bit pos="18">RC was doing a fabric op on behalf of a store and got an cresp=addr_err</bit>
+ <bit pos="19">RC incoming Power Bus data had a CE error.</bit>
+ <bit pos="20">RC incoming Power Bus data had a UE error.</bit>
+ <bit pos="21">RC incoming Power Bus data had a SUE error.</bit>
+ <bit pos="22">Targetted nodal request got rty_inc cresp.</bit>
+ <bit pos="23">RC was doing a fabric op on behalf of a load and got an cresp=addr_err for hyp memory</bit>
+ <bit pos="24">RCDAT read parity error.</bit>
+ <bit pos="25">CO or SNP was doing a fabric op on behalf of a store and got an cresp=addr_err</bit>
+ <bit pos="26">LVDIR took a parity error.</bit>
+ <bit pos="27">bad topology table config software error</bit>
+ <bit pos="28">Darn timed out waiting for data.</bit>
+ <bit pos="29">Early hang in L2.</bit>
+ <bit pos="30">Unexpected cast-out or push during chip_contained mode, maybe also during host-boot before memory available. Mask after host-boot memory ipl.</bit>
+ <bit pos="31">L2 FIR Register</bit>
+ <bit pos="32">PEC Phase3 timeout, recoverable problem, information only.</bit>
+ <bit pos="33">L2 FIR Register</bit>
+ <bit pos="34">L2 FIR Register</bit>
+ <bit pos="35">L2 FIR Register</bit>
+ <bit pos="36">Cache read CE and UE popped within a short hang pulse. Could be a triple bit error.</bit>
+ <bit pos="37">L2 FIR Register</bit>
+ <bit pos="38">L2 FIR Register</bit>
+ <bit pos="39">L2 FIR Register</bit>
+</attn_node>
diff --git a/xml/p10/node_eq_l3_fir.xml b/xml/p10/node_eq_l3_fir.xml
new file mode 100644
index 0000000..69e61b1
--- /dev/null
+++ b/xml/p10/node_eq_l3_fir.xml
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="EQ_L3_FIR" reg_type="SCOM">
+ <local_fir config="" name="EQ_L3_FIR">
+ <instance addr="0x20018600" reg_inst="0"/>
+ <instance addr="0x20014600" reg_inst="1"/>
+ <instance addr="0x20012600" reg_inst="2"/>
+ <instance addr="0x20011600" reg_inst="3"/>
+ <instance addr="0x21018600" reg_inst="4"/>
+ <instance addr="0x21014600" reg_inst="5"/>
+ <instance addr="0x21012600" reg_inst="6"/>
+ <instance addr="0x21011600" reg_inst="7"/>
+ <instance addr="0x22018600" reg_inst="8"/>
+ <instance addr="0x22014600" reg_inst="9"/>
+ <instance addr="0x22012600" reg_inst="10"/>
+ <instance addr="0x22011600" reg_inst="11"/>
+ <instance addr="0x23018600" reg_inst="12"/>
+ <instance addr="0x23014600" reg_inst="13"/>
+ <instance addr="0x23012600" reg_inst="14"/>
+ <instance addr="0x23011600" reg_inst="15"/>
+ <instance addr="0x24018600" reg_inst="16"/>
+ <instance addr="0x24014600" reg_inst="17"/>
+ <instance addr="0x24012600" reg_inst="18"/>
+ <instance addr="0x24011600" reg_inst="19"/>
+ <instance addr="0x25018600" reg_inst="20"/>
+ <instance addr="0x25014600" reg_inst="21"/>
+ <instance addr="0x25012600" reg_inst="22"/>
+ <instance addr="0x25011600" reg_inst="23"/>
+ <instance addr="0x26018600" reg_inst="24"/>
+ <instance addr="0x26014600" reg_inst="25"/>
+ <instance addr="0x26012600" reg_inst="26"/>
+ <instance addr="0x26011600" reg_inst="27"/>
+ <instance addr="0x27018600" reg_inst="28"/>
+ <instance addr="0x27014600" reg_inst="29"/>
+ <instance addr="0x27012600" reg_inst="30"/>
+ <instance addr="0x27011600" reg_inst="31"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ </local_fir>
+ <bit pos="0">When this error occurs, no members are available for a particular CGC. This will cause an infinite hang of a CI machine. There may be no members available due to a combination of line delete, way disable, and segr lco/qbit mode.</bit>
+ <bit pos="1">L3 attempted to master a CP (Castout/Push) command to the fabric when in chip_contained mode</bit>
+ <bit pos="2">Access attempted to use invalid topology table entry. Access may be from CO, RD, PF or snoop</bit>
+ <bit pos="3">This error indicates at least 1 CE and 1 UE have occurred within 1 fabric data hang pulse interval. This is an indication that a wordline fail may be occurring.</bit>
+ <bit pos="4">CE detected along read dataflow. This may assert due to cache read, casthru, pf_byp. If we are configured to do a single line delete and detect a CE for a cache read from a snoop/read machine, then fir26 will assert instead (fir4 will not assert). If set to do continuous line deletes fir4 will assert on CE (fir26 will not assert).</bit>
+ <bit pos="5">UE detected along read dataflow. May assert due to cache read, casthru, pf_byp.</bit>
+ <bit pos="6">SUE detected along read dataflow. May assert due to cache read, casthru, pf_byp.</bit>
+ <bit pos="7">CE detected along write dataflow with data from PowerBus (Prefetch, LCO or Cache Inject)</bit>
+ <bit pos="8">UE detected along write dataflow with data from PowerBus (Prefetch, LCO or Cache Inject)</bit>
+ <bit pos="9">SUE detected along write dataflow with data from PowerBus (Prefetch, LCO or Cache Inject)</bit>
+ <bit pos="10">CE detected along write dataflow with data from L2 CPI buffer or WIHPC</bit>
+ <bit pos="11">UE detected along write dataflow with data from L2 CPI buffer or WIHPC</bit>
+ <bit pos="12">SUE detected along write dataflow with data from L2 CPI buffer or WIHPC</bit>
+ <bit pos="13">Directory CE Occured</bit>
+ <bit pos="14">Directory UE Occured</bit>
+ <bit pos="15">Directory error occured but no error found during re-read of the directory again</bit>
+ <bit pos="16">Received addr_error cresp on Snoop Machine or Castout Operation</bit>
+ <bit pos="17">Received addr_error cresp for Prefetch Operation</bit>
+ <bit pos="18">Asserts when the L3 returns presp_rty_other to a PowerBus hang.poll or hang.check RCMD. This is typically masked, but provides an indication that an operation hang has been detected and signalled.</bit>
+ <bit pos="19">lru invalid count error. Violation of requirement that, when not in dmap or fixed-member mode, each group must have a member with lru_cnt=0 for 1st class and a member with lru_cnt=0 for 2nd class if there is a 2nd class member. Will not assert when an lru_cnt=0 is found for a member that is disabled. This error (missing lru_cnt=0) is recoverable - the L3 fails dispatch and then goes into random-victim- selection mode until it succeeds. On an L2-read or snoop, an LRU array is read, but errors aren't corrected because no LRU array write occurs. Thus, repeated reads to the location with the error may cause this bit to repeated assert. This bit may assert despite no error if the group and config have changed since the last time the CGC was accessed.</bit>
+ <bit pos="20">spare20</bit>
+ <bit pos="21">spare21</bit>
+ <bit pos="22">spare22</bit>
+ <bit pos="23">Prefetcj or Write Inject machine PowerBus data hang check</bit>
+ <bit pos="24">Hardware Control Error. See Hardware Control Error Read0/1 SCOM Registers for details.</bit>
+ <bit pos="25">Cache Inhibited operation was hit in the L3 directory. This is usually a software bug.</bit>
+ <bit pos="26">Snoop Machine or Read machine has performed a line delete from a cache read</bit>
+ <bit pos="27">Indicates that this l3 has snooped an incoming lco and in which the source (rcmdx_source) is not proxime. This is likely due to a programming error and could result in multiple owners of a line</bit>
+ <bit pos="28">Indicates the LRU intended to victimize a line, but failed to select exactly one member for victimization. This asserts due to a LRU array bit error (lru_inval_cnt_err also asserts) or an algorithm or implementation error in the logic that generates the selection. The lru_inval_cnt_err, and thus this bit, may assert despite no error if the group and config have changed since the last time the CGC was accessed. This error is recoverable - the L3 fails dispatch and then goes into random-victim- selection mode until it succeeds. On an l2-read or snoop, an LRU array is read, but errors aren't corrected because there is no LRU array write. Thus, repeated reads to the location with the error may cause this bit to repeated assert.</bit>
+ <bit pos="29">All members are either column or line deleted in some CGC class</bit>
+ <bit pos="30">Indicates that this l3 has snooped an incoming lco and we are the target however, our lco target id (set via SCOM in mode_reg1) does not match the chiplet id set by pb through input pins pb_ex_chiplet_id_dc Note that in chip-contained mode, the LCOs ID are often set to values that dont match the pb_ex_chiplet_id, thus this error is masked in that mode.</bit>
+ <bit pos="31">Received ack_dead or ed_ack_dead cresp on CO, SN operation (pb write)</bit>
+ <bit pos="32">Received ack_dead or ed_ack_dead cresp on PF operation (pb read)</bit>
+</attn_node>
diff --git a/xml/p10/node_eq_local_fir.xml b/xml/p10/node_eq_local_fir.xml
new file mode 100644
index 0000000..7895c79
--- /dev/null
+++ b/xml/p10/node_eq_local_fir.xml
@@ -0,0 +1,82 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="EQ_LOCAL_FIR" reg_type="SCOM">
+ <local_fir config="W2" name="EQ_LOCAL_FIR">
+ <instance addr="0x20040100" reg_inst="0"/>
+ <instance addr="0x21040100" reg_inst="1"/>
+ <instance addr="0x22040100" reg_inst="2"/>
+ <instance addr="0x23040100" reg_inst="3"/>
+ <instance addr="0x24040100" reg_inst="4"/>
+ <instance addr="0x25040100" reg_inst="5"/>
+ <instance addr="0x26040100" reg_inst="6"/>
+ <instance addr="0x27040100" reg_inst="7"/>
+ <action attn_type="CS" config="000"/>
+ <action attn_type="RE" config="010"/>
+ <action attn_type="SPA" config="100"/>
+ <action attn_type="UCS" config="110"/>
+ <action attn_type="HA" config="001"/>
+ </local_fir>
+ <bit pos="0">CFIR - Parity or PCB access error</bit>
+ <bit pos="1">CPLT_CTRL - PCB access error</bit>
+ <bit pos="2">CC - PCB access error - read and clear nn03000F</bit>
+ <bit pos="3">CC - Clock Control Error - read and clear nn03000F</bit>
+ <bit pos="4">PSC - PSCOM access error - read and clear nn01001</bit>
+ <bit pos="5">PSC - internal or ring interface error - read and clear nn01001</bit>
+ <bit pos="6">THERM1 - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050013</bit>
+ <bit pos="7">THERM1 - pcb error</bit>
+ <bit pos="8">THERMTRIP1 - Critical temperature indicator</bit>
+ <bit pos="9">THERMTRIP1 - Fatal temperature indicator</bit>
+ <bit pos="10">VOLTTRIP1 - Voltage sense error</bit>
+ <bit pos="11">THERM2 - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050033</bit>
+ <bit pos="12">THERM2 - pcb error</bit>
+ <bit pos="13">THERMTRIP2 - Critical temperature indicator</bit>
+ <bit pos="14">THERMTRIP2 - Fatal temperature indicator</bit>
+ <bit pos="15">VOLTTRIP2 - Voltage sense error</bit>
+ <bit pos="16">DBG - scom parity fail</bit>
+ <bit pos="17">reserved</bit>
+ <bit pos="18">reserved</bit>
+ <bit pos="19">reserved</bit>
+ <bit pos="20">L30 Trace Err</bit>
+ <bit pos="21">L31 Trace Err</bit>
+ <bit pos="22">L32 Trace Err</bit>
+ <bit pos="23">L33 Trace Err</bit>
+ <bit pos="24">DCADJ FIR ERR Core 0</bit>
+ <bit pos="25">DCADJ FIR ERR Core 1</bit>
+ <bit pos="26">DCADJ FIR ERR Core 2</bit>
+ <bit pos="27">DCADJ FIR ERR Core 3</bit>
+ <bit pos="28">SKEWADJ FIR ERR Core0</bit>
+ <bit pos="29">SKEWADJ FIR ERR Core1</bit>
+ <bit pos="30">SKEWADJ FIR ERR Core2</bit>
+ <bit pos="31">SKEWADJ FIR ERR Core3</bit>
+ <bit pos="32">DC_SCOM_ERR_0</bit>
+ <bit pos="33">DC_SCOM_ERR_1</bit>
+ <bit pos="34">DC_SCOM_ERR_2</bit>
+ <bit pos="35">DC_SCOM_ERR_3</bit>
+ <bit pos="36">SKEW_SCOM_ERR_0</bit>
+ <bit pos="37">SKEW_SCOM_ERR_1</bit>
+ <bit pos="38">SKEW_SCOM_ERR_2</bit>
+ <bit pos="39">SKEW_SCOM_ERR_3</bit>
+ <bit pos="40">unused</bit>
+ <bit pos="41">unused</bit>
+ <bit pos="42">unused</bit>
+ <bit pos="43">unused</bit>
+ <bit pos="44">unused</bit>
+ <bit pos="45">unused</bit>
+ <bit pos="46">unused</bit>
+ <bit pos="47">unused</bit>
+ <bit pos="48">unused</bit>
+ <bit pos="49">unused</bit>
+ <bit pos="50">unused</bit>
+ <bit pos="51">unused</bit>
+ <bit pos="52">unused</bit>
+ <bit pos="53">unused</bit>
+ <bit pos="54">unused</bit>
+ <bit pos="55">unused</bit>
+ <bit pos="56">unused</bit>
+ <bit pos="57">unused</bit>
+ <bit pos="58">unused</bit>
+ <bit pos="59">unused</bit>
+ <bit pos="60">unused</bit>
+ <bit pos="61">unused</bit>
+ <bit pos="62">unused</bit>
+ <bit pos="63">ext_local_xstop</bit>
+</attn_node>
diff --git a/xml/p10/node_eq_ncu_fir.xml b/xml/p10/node_eq_ncu_fir.xml
new file mode 100644
index 0000000..1d40018
--- /dev/null
+++ b/xml/p10/node_eq_ncu_fir.xml
@@ -0,0 +1,68 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="EQ_NCU_FIR" reg_type="SCOM">
+ <local_fir config="" name="EQ_NCU_FIR">
+ <instance addr="0x20018640" reg_inst="0"/>
+ <instance addr="0x20014640" reg_inst="1"/>
+ <instance addr="0x20012640" reg_inst="2"/>
+ <instance addr="0x20011640" reg_inst="3"/>
+ <instance addr="0x21018640" reg_inst="4"/>
+ <instance addr="0x21014640" reg_inst="5"/>
+ <instance addr="0x21012640" reg_inst="6"/>
+ <instance addr="0x21011640" reg_inst="7"/>
+ <instance addr="0x22018640" reg_inst="8"/>
+ <instance addr="0x22014640" reg_inst="9"/>
+ <instance addr="0x22012640" reg_inst="10"/>
+ <instance addr="0x22011640" reg_inst="11"/>
+ <instance addr="0x23018640" reg_inst="12"/>
+ <instance addr="0x23014640" reg_inst="13"/>
+ <instance addr="0x23012640" reg_inst="14"/>
+ <instance addr="0x23011640" reg_inst="15"/>
+ <instance addr="0x24018640" reg_inst="16"/>
+ <instance addr="0x24014640" reg_inst="17"/>
+ <instance addr="0x24012640" reg_inst="18"/>
+ <instance addr="0x24011640" reg_inst="19"/>
+ <instance addr="0x25018640" reg_inst="20"/>
+ <instance addr="0x25014640" reg_inst="21"/>
+ <instance addr="0x25012640" reg_inst="22"/>
+ <instance addr="0x25011640" reg_inst="23"/>
+ <instance addr="0x26018640" reg_inst="24"/>
+ <instance addr="0x26014640" reg_inst="25"/>
+ <instance addr="0x26012640" reg_inst="26"/>
+ <instance addr="0x26011640" reg_inst="27"/>
+ <instance addr="0x27018640" reg_inst="28"/>
+ <instance addr="0x27014640" reg_inst="29"/>
+ <instance addr="0x27012640" reg_inst="30"/>
+ <instance addr="0x27011640" reg_inst="31"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ </local_fir>
+ <bit pos="0">H/W control error.</bit>
+ <bit pos="1">TLBIE control error.</bit>
+ <bit pos="2">TLBIE or SLBIEG received illegal fields from core.</bit>
+ <bit pos="3">Store address machine received addr_err cresp.</bit>
+ <bit pos="4">Load address machine received addr_err cresp.</bit>
+ <bit pos="5">Topology table error - tried accessing invalid entry</bit>
+ <bit pos="6">One the NCU machines triggerd PB into early hang recovery</bit>
+ <bit pos="7">MSGSND received addr_err</bit>
+ <bit pos="8">Store data parity error from regfile detected.</bit>
+ <bit pos="9">Store timed out on PB.</bit>
+ <bit pos="10">TLBIE master timed out on PB.</bit>
+ <bit pos="11">TLBIE snooper timed out waiting for core.</bit>
+ <bit pos="12">IMA received addr_err cresp.</bit>
+ <bit pos="13">TLBIE/sync machine received addr_err cresp.</bit>
+ <bit pos="14">PMISC received address error cresp.</bit>
+ <bit pos="15">cHTM logic recieve an HTM/IMA packet that it wasn't setup for</bit>
+ <bit pos="16">Spare fir bits.</bit>
+ <bit pos="17">Spare fir bits.</bit>
+ <bit pos="18">Spare fir bits.</bit>
+ <bit pos="19">PPE write received ack_dead</bit>
+ <bit pos="20">Darn ttype while darn not enabled.</bit>
+ <bit pos="21">Darn Address Error cresp.</bit>
+ <bit pos="22">Spare fir bits.</bit>
+ <bit pos="23">Spare fir bits.</bit>
+ <bit pos="24">Spare fir bits.</bit>
+ <bit pos="25">Spare fir bits.</bit>
+ <bit pos="26">Spare fir bits.</bit>
+ <bit pos="27">Spare fir bits.</bit>
+ <bit pos="28">Spare fir bits.</bit>
+</attn_node>
diff --git a/xml/p10/node_eq_qme_fir.xml b/xml/p10/node_eq_qme_fir.xml
new file mode 100644
index 0000000..aaaa854
--- /dev/null
+++ b/xml/p10/node_eq_qme_fir.xml
@@ -0,0 +1,107 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="EQ_QME_FIR" reg_type="SCOM">
+ <register name="EQ_QME_FIR">
+ <instance addr="0x200E0000" reg_inst="0"/>
+ <instance addr="0x210E0000" reg_inst="1"/>
+ <instance addr="0x220E0000" reg_inst="2"/>
+ <instance addr="0x230E0000" reg_inst="3"/>
+ <instance addr="0x240E0000" reg_inst="4"/>
+ <instance addr="0x250E0000" reg_inst="5"/>
+ <instance addr="0x260E0000" reg_inst="6"/>
+ <instance addr="0x270E0000" reg_inst="7"/>
+ </register>
+ <register name="EQ_QME_FIR_MASK">
+ <instance addr="0x200E0004" reg_inst="0"/>
+ <instance addr="0x210E0004" reg_inst="1"/>
+ <instance addr="0x220E0004" reg_inst="2"/>
+ <instance addr="0x230E0004" reg_inst="3"/>
+ <instance addr="0x240E0004" reg_inst="4"/>
+ <instance addr="0x250E0004" reg_inst="5"/>
+ <instance addr="0x260E0004" reg_inst="6"/>
+ <instance addr="0x270E0004" reg_inst="7"/>
+ </register>
+ <register name="EQ_QME_FIR_ACT0">
+ <instance addr="0x200E0008" reg_inst="0"/>
+ <instance addr="0x210E0008" reg_inst="1"/>
+ <instance addr="0x220E0008" reg_inst="2"/>
+ <instance addr="0x230E0008" reg_inst="3"/>
+ <instance addr="0x240E0008" reg_inst="4"/>
+ <instance addr="0x250E0008" reg_inst="5"/>
+ <instance addr="0x260E0008" reg_inst="6"/>
+ <instance addr="0x270E0008" reg_inst="7"/>
+ </register>
+ <register name="EQ_QME_FIR_ACT1">
+ <instance addr="0x200E000c" reg_inst="0"/>
+ <instance addr="0x210E000c" reg_inst="1"/>
+ <instance addr="0x220E000c" reg_inst="2"/>
+ <instance addr="0x230E000c" reg_inst="3"/>
+ <instance addr="0x240E000c" reg_inst="4"/>
+ <instance addr="0x250E000c" reg_inst="5"/>
+ <instance addr="0x260E000c" reg_inst="6"/>
+ <instance addr="0x270E000c" reg_inst="7"/>
+ </register>
+ <rule attn_type="CS" node_inst="0:7">
+ <!-- FIR & ~MASK & ~ACT0 & ~ACT1 -->
+ <expr type="and">
+ <expr type="reg" value1="EQ_QME_FIR"/>
+ <expr type="not">
+ <expr type="reg" value1="EQ_QME_FIR_MASK"/>
+ </expr>
+ <expr type="not">
+ <expr type="reg" value1="EQ_QME_FIR_ACT0"/>
+ </expr>
+ <expr type="not">
+ <expr type="reg" value1="EQ_QME_FIR_ACT1"/>
+ </expr>
+ </expr>
+ </rule>
+ <rule attn_type="RE" node_inst="0:7">
+ <!-- FIR & ~MASK & ~ACT0 & ACT1 -->
+ <expr type="and">
+ <expr type="reg" value1="EQ_QME_FIR"/>
+ <expr type="not">
+ <expr type="reg" value1="EQ_QME_FIR_MASK"/>
+ </expr>
+ <expr type="not">
+ <expr type="reg" value1="EQ_QME_FIR_ACT0"/>
+ </expr>
+ <expr type="reg" value1="EQ_QME_FIR_ACT1"/>
+ </expr>
+ </rule>
+ <bit pos="0">PPE halted due to an error, which is an OR the 4 signals captured in ERR(0:3). This indication is intended to be reported to the OCC complex as an</bit>
+ <bit pos="1">PPE asserted debug trigger. Connected to PPEDBG[FIR_TRIGGER]. May be used by QME hcode to indicate an error to PRD or to induce a checkstop for</bit>
+ <bit pos="2">Used for TBD testing or workarounds</bit>
+ <bit pos="3">PPE asserted a watchdog timeout condition.</bit>
+ <bit pos="4">QME hardware detected its own timeout on the PCB Slave interface and forced a return code of 0x7. Note: uses the Watchdog TSEL minus 2 bits (watchdog</bit>
+ <bit pos="5">Either the Block Copy Engine or QME PPE direct access received an error from the Fabric. A BCE error also causes an interrupt to the QME PPE, if it</bit>
+ <bit pos="6">SRAM Uncorrectable Error.</bit>
+ <bit pos="7">SRAM Correctable Error. QME received corrected data, but SRAM content is bad until next scrub to that line. (Should be masked in the product;</bit>
+ <bit pos="8">Resonant Clock Table array Parity Error.</bit>
+ <bit pos="9">Hcode wrote the PIG to request a PCB interrupt before its previously requested interrupt had been completed (meaning PIG[PENDING_SOURCE(0)] = 1 OR</bit>
+ <bit pos="10">Scrub timer tick occurred when scrub is still pending (hardware defect or severe configuration error). Unless the FIT timer is set to smaller than 16</bit>
+ <bit pos="11">Refer to ERR bits of the same name to see which Core instance.</bit>
+ <bit pos="12">Refer to ERR bits of the same name to see which Core instance.</bit>
+ <bit pos="13">PGPE Heartbeat Lost indication from a hardware deadman timer controlled by QHB. Intended to be reported as an interrupt to QME via action 10.</bit>
+ <bit pos="14">Notification that BCE has not made forward progress in the time period corresponding to two scrub timer pulses (regardless of scrub enable). The BCE</bit>
+ <bit pos="15">Resclk TARGET_PSTATE Change Protocol Error. PGPE code bug.</bit>
+ <bit pos="16">PCB Network or Endpoint Reset occurred when QME was not halted. This should never occur during runtime (for lab debug use only) and MAY result in loss</bit>
+ <bit pos="17">Firmware cleared their Special Wakeup request in SPWU_{OTR|FSP|OCC|HYP}[ SPECIAL_WKUP_REQ] before the SPECIAL_WKUP_DONE was set.</bit>
+ <bit pos="18">Indicates a window condition occurred where one firmware component set a new special wakeup right after a different firmware component cleared the</bit>
+ <bit pos="19">Any of the Core External Interrupt wakeup sources (os, hyp, msgsnd, msgsndu) are present but disabled by the threads PECE (or UDEE) when it is in Stop</bit>
+ <bit pos="20">Any of the Core External Interrupts (os, hyp, msgsnd, msgsndu) are present but the chiplet is deconfigured (based on the partial good region enable</bit>
+ <bit pos="21">Notification that RS4 engine has not made forward progress in the time period corresponding to two watchdog timer pulses (regardless of PPE watchdog</bit>
+ <bit pos="22">Data hang was detected in the powerbus logic, caused by a powerbus read command waiting for data that is lost.</bit>
+ <bit pos="23">The PPE tried to write a protected address as defined by the SWPR[n] register</bit>
+ <bit pos="24">DTC Sequencer read a UE from SRAM, causing it to abort its current sequence and disable itself in QMCR.</bit>
+ <bit pos="25">Correctable error detected on incoming data for a PowerBus read.</bit>
+ <bit pos="26">UE Detected on incoming data for a PowerBus read.</bit>
+ <bit pos="27">SUE Detected on incoming data for a PowerBus read.</bit>
+ <bit pos="28">A Powerbus Request address has hit an invalid entry in the TOPOLOGY XLATE TABLE [PBTXTR] REGISTER. This is an unrecoverable error indicating the</bit>
+ <bit pos="29">Parity error detected on a powerbus tag. Includes combined response ATAG/TTAG parity error as well as a data transaction RTAG parity error.</bit>
+ <bit pos="30">Code attempted to write the PIG register when the previous request was still pending i.e. PIG.PENDING_SOURCE(0)=1.</bit>
+ <bit pos="31">Set based on the OR of three ERR[LOCAL_ACCESS_*_ERR] bits.</bit>
+ <bit pos="32">CE detected on a read to the SSA located in the QME powerbus routing logic.</bit>
+ <bit pos="33">UE detected on a read to the SSA located in the QME powerbus routing logic.</bit>
+ <bit pos="34">Implemented but not used. Input tied to 0.</bit>
+ <bit pos="35">Implemented but not used. Input tied to 0.</bit>
+</attn_node>
diff --git a/xml/p10/node_eq_spattn_fused.xml b/xml/p10/node_eq_spattn_fused.xml
new file mode 100644
index 0000000..400090b
--- /dev/null
+++ b/xml/p10/node_eq_spattn_fused.xml
@@ -0,0 +1,125 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="EQ_SPATTN_FUSED" reg_type="SCOM">
+ <register name="EQ_SPATTN">
+ <instance addr="0x20028499" reg_inst="0"/>
+ <instance addr="0x20024499" reg_inst="1"/>
+ <instance addr="0x20022499" reg_inst="2"/>
+ <instance addr="0x20021499" reg_inst="3"/>
+ <instance addr="0x21028499" reg_inst="4"/>
+ <instance addr="0x21024499" reg_inst="5"/>
+ <instance addr="0x21022499" reg_inst="6"/>
+ <instance addr="0x21021499" reg_inst="7"/>
+ <instance addr="0x22028499" reg_inst="8"/>
+ <instance addr="0x22024499" reg_inst="9"/>
+ <instance addr="0x22022499" reg_inst="10"/>
+ <instance addr="0x22021499" reg_inst="11"/>
+ <instance addr="0x23028499" reg_inst="12"/>
+ <instance addr="0x23024499" reg_inst="13"/>
+ <instance addr="0x23022499" reg_inst="14"/>
+ <instance addr="0x23021499" reg_inst="15"/>
+ <instance addr="0x24028499" reg_inst="16"/>
+ <instance addr="0x24024499" reg_inst="17"/>
+ <instance addr="0x24022499" reg_inst="18"/>
+ <instance addr="0x24021499" reg_inst="19"/>
+ <instance addr="0x25028499" reg_inst="20"/>
+ <instance addr="0x25024499" reg_inst="21"/>
+ <instance addr="0x25022499" reg_inst="22"/>
+ <instance addr="0x25021499" reg_inst="23"/>
+ <instance addr="0x26028499" reg_inst="24"/>
+ <instance addr="0x26024499" reg_inst="25"/>
+ <instance addr="0x26022499" reg_inst="26"/>
+ <instance addr="0x26021499" reg_inst="27"/>
+ <instance addr="0x27028499" reg_inst="28"/>
+ <instance addr="0x27024499" reg_inst="29"/>
+ <instance addr="0x27022499" reg_inst="30"/>
+ <instance addr="0x27021499" reg_inst="31"/>
+ </register>
+ <register name="EQ_SPATTN_MASK">
+ <instance addr="0x2002849a" reg_inst="0"/>
+ <instance addr="0x2002449a" reg_inst="1"/>
+ <instance addr="0x2002249a" reg_inst="2"/>
+ <instance addr="0x2002149a" reg_inst="3"/>
+ <instance addr="0x2102849a" reg_inst="4"/>
+ <instance addr="0x2102449a" reg_inst="5"/>
+ <instance addr="0x2102249a" reg_inst="6"/>
+ <instance addr="0x2102149a" reg_inst="7"/>
+ <instance addr="0x2202849a" reg_inst="8"/>
+ <instance addr="0x2202449a" reg_inst="9"/>
+ <instance addr="0x2202249a" reg_inst="10"/>
+ <instance addr="0x2202149a" reg_inst="11"/>
+ <instance addr="0x2302849a" reg_inst="12"/>
+ <instance addr="0x2302449a" reg_inst="13"/>
+ <instance addr="0x2302249a" reg_inst="14"/>
+ <instance addr="0x2302149a" reg_inst="15"/>
+ <instance addr="0x2402849a" reg_inst="16"/>
+ <instance addr="0x2402449a" reg_inst="17"/>
+ <instance addr="0x2402249a" reg_inst="18"/>
+ <instance addr="0x2402149a" reg_inst="19"/>
+ <instance addr="0x2502849a" reg_inst="20"/>
+ <instance addr="0x2502449a" reg_inst="21"/>
+ <instance addr="0x2502249a" reg_inst="22"/>
+ <instance addr="0x2502149a" reg_inst="23"/>
+ <instance addr="0x2602849a" reg_inst="24"/>
+ <instance addr="0x2602449a" reg_inst="25"/>
+ <instance addr="0x2602249a" reg_inst="26"/>
+ <instance addr="0x2602149a" reg_inst="27"/>
+ <instance addr="0x2702849a" reg_inst="28"/>
+ <instance addr="0x2702449a" reg_inst="29"/>
+ <instance addr="0x2702249a" reg_inst="30"/>
+ <instance addr="0x2702149a" reg_inst="31"/>
+ </register>
+ <!-- In Fused Core mode, both local EQ_SPATTN in the fused core pair
+ display the exact same information for all eight threads in the pair.
+ However, only the even threads on the even cores and the odd threads on
+ the odd cores report to the CFIR_EQ_SPA. -->
+ <rule attn_type="SPA" node_inst="0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30">
+ <expr type="and">
+ <expr type="reg" value1="EQ_SPATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="EQ_SPATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0xf0f0f0f000000000"/>
+ </expr>
+ </rule>
+ <rule attn_type="SPA" node_inst="1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31">
+ <expr type="and">
+ <expr type="reg" value1="EQ_SPATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="EQ_SPATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0f0f0f0f00000000"/>
+ </expr>
+ </rule>
+ <bit pos="0">lt0_spr_instr_stop</bit>
+ <bit pos="1">lt0_attn_complete</bit>
+ <bit pos="2">lt0_core_checkstop_recovery_handshake</bit>
+ <bit pos="3">lt0_core_code_to_sp</bit>
+ <bit pos="4">lt1_spr_instr_stop</bit>
+ <bit pos="5">lt1_attn_complete</bit>
+ <bit pos="6">lt1_core_checkstop_recovery_handshake</bit>
+ <bit pos="7">lt1_core_code_to_sp</bit>
+ <bit pos="8">lt2_spr_instr_stop</bit>
+ <bit pos="9">lt2_attn_complete</bit>
+ <bit pos="10">lt2_core_checkstop_recovery_handshake</bit>
+ <bit pos="11">lt2_core_code_to_sp</bit>
+ <bit pos="12">lt3_spr_instr_stop</bit>
+ <bit pos="13">lt3_attn_complete</bit>
+ <bit pos="14">lt3_core_checkstop_recovery_handshake</bit>
+ <bit pos="15">lt3_core_code_to_sp</bit>
+ <bit pos="16">lt4_spr_instr_stop</bit>
+ <bit pos="17">lt4_attn_complete</bit>
+ <bit pos="18">lt4_core_checkstop_recovery_handshake</bit>
+ <bit pos="19">lt4_core_code_to_sp</bit>
+ <bit pos="20">lt5_spr_instr_stop</bit>
+ <bit pos="21">lt5_attn_complete</bit>
+ <bit pos="22">lt5_core_checkstop_recovery_handshake</bit>
+ <bit pos="23">lt5_core_code_to_sp</bit>
+ <bit pos="24">lt6_spr_instr_stop</bit>
+ <bit pos="25">lt6_attn_complete</bit>
+ <bit pos="26">lt6_core_checkstop_recovery_handshake</bit>
+ <bit pos="27">lt6_core_code_to_sp</bit>
+ <bit pos="28">lt7_spr_instr_stop</bit>
+ <bit pos="29">lt7_attn_complete</bit>
+ <bit pos="30">lt7_core_checkstop_recovery_handshake</bit>
+ <bit pos="31">lt7_core_code_to_sp</bit>
+</attn_node>
diff --git a/xml/p10/node_eq_spattn_normal.xml b/xml/p10/node_eq_spattn_normal.xml
new file mode 100644
index 0000000..fa83655
--- /dev/null
+++ b/xml/p10/node_eq_spattn_normal.xml
@@ -0,0 +1,97 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="EQ_SPATTN_NORMAL" reg_type="SCOM">
+ <register name="EQ_SPATTN">
+ <instance addr="0x20028499" reg_inst="0"/>
+ <instance addr="0x20024499" reg_inst="1"/>
+ <instance addr="0x20022499" reg_inst="2"/>
+ <instance addr="0x20021499" reg_inst="3"/>
+ <instance addr="0x21028499" reg_inst="4"/>
+ <instance addr="0x21024499" reg_inst="5"/>
+ <instance addr="0x21022499" reg_inst="6"/>
+ <instance addr="0x21021499" reg_inst="7"/>
+ <instance addr="0x22028499" reg_inst="8"/>
+ <instance addr="0x22024499" reg_inst="9"/>
+ <instance addr="0x22022499" reg_inst="10"/>
+ <instance addr="0x22021499" reg_inst="11"/>
+ <instance addr="0x23028499" reg_inst="12"/>
+ <instance addr="0x23024499" reg_inst="13"/>
+ <instance addr="0x23022499" reg_inst="14"/>
+ <instance addr="0x23021499" reg_inst="15"/>
+ <instance addr="0x24028499" reg_inst="16"/>
+ <instance addr="0x24024499" reg_inst="17"/>
+ <instance addr="0x24022499" reg_inst="18"/>
+ <instance addr="0x24021499" reg_inst="19"/>
+ <instance addr="0x25028499" reg_inst="20"/>
+ <instance addr="0x25024499" reg_inst="21"/>
+ <instance addr="0x25022499" reg_inst="22"/>
+ <instance addr="0x25021499" reg_inst="23"/>
+ <instance addr="0x26028499" reg_inst="24"/>
+ <instance addr="0x26024499" reg_inst="25"/>
+ <instance addr="0x26022499" reg_inst="26"/>
+ <instance addr="0x26021499" reg_inst="27"/>
+ <instance addr="0x27028499" reg_inst="28"/>
+ <instance addr="0x27024499" reg_inst="29"/>
+ <instance addr="0x27022499" reg_inst="30"/>
+ <instance addr="0x27021499" reg_inst="31"/>
+ </register>
+ <register name="EQ_SPATTN_MASK">
+ <instance addr="0x2002849a" reg_inst="0"/>
+ <instance addr="0x2002449a" reg_inst="1"/>
+ <instance addr="0x2002249a" reg_inst="2"/>
+ <instance addr="0x2002149a" reg_inst="3"/>
+ <instance addr="0x2102849a" reg_inst="4"/>
+ <instance addr="0x2102449a" reg_inst="5"/>
+ <instance addr="0x2102249a" reg_inst="6"/>
+ <instance addr="0x2102149a" reg_inst="7"/>
+ <instance addr="0x2202849a" reg_inst="8"/>
+ <instance addr="0x2202449a" reg_inst="9"/>
+ <instance addr="0x2202249a" reg_inst="10"/>
+ <instance addr="0x2202149a" reg_inst="11"/>
+ <instance addr="0x2302849a" reg_inst="12"/>
+ <instance addr="0x2302449a" reg_inst="13"/>
+ <instance addr="0x2302249a" reg_inst="14"/>
+ <instance addr="0x2302149a" reg_inst="15"/>
+ <instance addr="0x2402849a" reg_inst="16"/>
+ <instance addr="0x2402449a" reg_inst="17"/>
+ <instance addr="0x2402249a" reg_inst="18"/>
+ <instance addr="0x2402149a" reg_inst="19"/>
+ <instance addr="0x2502849a" reg_inst="20"/>
+ <instance addr="0x2502449a" reg_inst="21"/>
+ <instance addr="0x2502249a" reg_inst="22"/>
+ <instance addr="0x2502149a" reg_inst="23"/>
+ <instance addr="0x2602849a" reg_inst="24"/>
+ <instance addr="0x2602449a" reg_inst="25"/>
+ <instance addr="0x2602249a" reg_inst="26"/>
+ <instance addr="0x2602149a" reg_inst="27"/>
+ <instance addr="0x2702849a" reg_inst="28"/>
+ <instance addr="0x2702449a" reg_inst="29"/>
+ <instance addr="0x2702249a" reg_inst="30"/>
+ <instance addr="0x2702149a" reg_inst="31"/>
+ </register>
+ <!-- In Normal Core mode, only threads 0-3 report to the CFIR_EQ_SPA. -->
+ <rule attn_type="SPA" node_inst="0:31">
+ <expr type="and">
+ <expr type="reg" value1="EQ_SPATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="EQ_SPATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0xffff000000000000"/>
+ </expr>
+ </rule>
+ <bit pos="0">lt0_spr_instr_stop</bit>
+ <bit pos="1">lt0_attn_complete</bit>
+ <bit pos="2">lt0_core_checkstop_recovery_handshake</bit>
+ <bit pos="3">lt0_core_code_to_sp</bit>
+ <bit pos="4">lt1_spr_instr_stop</bit>
+ <bit pos="5">lt1_attn_complete</bit>
+ <bit pos="6">lt1_core_checkstop_recovery_handshake</bit>
+ <bit pos="7">lt1_core_code_to_sp</bit>
+ <bit pos="8">lt2_spr_instr_stop</bit>
+ <bit pos="9">lt2_attn_complete</bit>
+ <bit pos="10">lt2_core_checkstop_recovery_handshake</bit>
+ <bit pos="11">lt2_core_code_to_sp</bit>
+ <bit pos="12">lt3_spr_instr_stop</bit>
+ <bit pos="13">lt3_attn_complete</bit>
+ <bit pos="14">lt3_core_checkstop_recovery_handshake</bit>
+ <bit pos="15">lt3_core_code_to_sp</bit>
+</attn_node>
diff --git a/xml/p10/node_gfir_cs.xml b/xml/p10/node_gfir_cs.xml
new file mode 100644
index 0000000..315a421
--- /dev/null
+++ b/xml/p10/node_gfir_cs.xml
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="GFIR_CS" reg_type="SCOM">
+ <register name="GFIR_REG_CS">
+ <instance addr="0x570F001C" reg_inst="0"/>
+ </register>
+ <rule attn_type="CS" node_inst="0">
+ <expr type="reg" value1="GFIR_REG_CS"/>
+ </rule>
+ <bit child_node="CFIR_TP_CS_RE" node_inst="0" pos="1">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_N0_CS_RE" node_inst="0" pos="2">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_N1_CS" node_inst="0" pos="3">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PCI_CS_RE" node_inst="0" pos="8">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PCI_CS_RE" node_inst="1" pos="9">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="0" pos="12">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="1" pos="13">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="2" pos="14">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="3" pos="15">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUE_CS_RE" node_inst="0" pos="16">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUE_CS_RE" node_inst="1" pos="17">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUW_CS_RE" node_inst="0" pos="18">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUW_CS_RE" node_inst="1" pos="19">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="0" pos="24">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="1" pos="25">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="2" pos="26">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="3" pos="27">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="4" pos="28">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="5" pos="29">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="6" pos="30">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="7" pos="31">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_CS" node_inst="0" pos="32">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_CS" node_inst="1" pos="33">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_CS" node_inst="2" pos="34">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_CS" node_inst="3" pos="35">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_CS" node_inst="4" pos="36">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_CS" node_inst="5" pos="37">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_CS" node_inst="6" pos="38">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_CS" node_inst="7" pos="39">XSTOP Register - after masking - OLD XFIR</bit>
+</attn_node>
diff --git a/xml/p10/node_gfir_ha.xml b/xml/p10/node_gfir_ha.xml
new file mode 100644
index 0000000..960fe8a
--- /dev/null
+++ b/xml/p10/node_gfir_ha.xml
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="GFIR_HA" reg_type="SCOM">
+ <register name="GFIR_REG_HA">
+ <instance addr="0x570F002B" reg_inst="0"/>
+ </register>
+ <rule attn_type="HA" node_inst="0">
+ <expr type="reg" value1="GFIR_REG_HA"/>
+ </rule>
+ <bit child_node="CFIR_TP_SPA_UCS_HA" node_inst="0" pos="1">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_N0_HA" node_inst="0" pos="2">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_N1_HA" node_inst="0" pos="3">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PCI_SPA_HA" node_inst="0" pos="8">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PCI_SPA_HA" node_inst="1" pos="9">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_UCS_HA" node_inst="0" pos="12">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_UCS_HA" node_inst="1" pos="13">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_UCS_HA" node_inst="2" pos="14">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_UCS_HA" node_inst="3" pos="15">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUE_HA" node_inst="0" pos="16">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUE_HA" node_inst="1" pos="17">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUW_HA" node_inst="0" pos="18">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUW_HA" node_inst="1" pos="19">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_UCS_HA" node_inst="0" pos="24">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_UCS_HA" node_inst="1" pos="25">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_UCS_HA" node_inst="2" pos="26">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_UCS_HA" node_inst="3" pos="27">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_UCS_HA" node_inst="4" pos="28">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_UCS_HA" node_inst="5" pos="29">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_UCS_HA" node_inst="6" pos="30">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_UCS_HA" node_inst="7" pos="31">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_HA" node_inst="0" pos="32">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_HA" node_inst="1" pos="33">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_HA" node_inst="2" pos="34">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_HA" node_inst="3" pos="35">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_HA" node_inst="4" pos="36">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_HA" node_inst="5" pos="37">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_HA" node_inst="6" pos="38">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_HA" node_inst="7" pos="39">XSTOP Register - after masking - OLD XFIR</bit>
+</attn_node>
diff --git a/xml/p10/node_gfir_re.xml b/xml/p10/node_gfir_re.xml
new file mode 100644
index 0000000..1f9668c
--- /dev/null
+++ b/xml/p10/node_gfir_re.xml
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="GFIR_RE" reg_type="SCOM">
+ <register name="GFIR_REG_RE">
+ <instance addr="0x570F001B" reg_inst="0"/>
+ </register>
+ <rule attn_type="RE" node_inst="0">
+ <expr type="reg" value1="GFIR_REG_RE"/>
+ </rule>
+ <bit child_node="CFIR_TP_CS_RE" node_inst="0" pos="1">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_N0_CS_RE" node_inst="0" pos="2">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_N1_RE" node_inst="0" pos="3">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PCI_CS_RE" node_inst="0" pos="8">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PCI_CS_RE" node_inst="1" pos="9">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="0" pos="12">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="1" pos="13">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="2" pos="14">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="3" pos="15">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUE_CS_RE" node_inst="0" pos="16">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUE_CS_RE" node_inst="1" pos="17">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUW_CS_RE" node_inst="0" pos="18">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUW_CS_RE" node_inst="1" pos="19">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="0" pos="24">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="1" pos="25">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="2" pos="26">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="3" pos="27">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="4" pos="28">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="5" pos="29">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="6" pos="30">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="7" pos="31">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_RE" node_inst="0" pos="32">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_RE" node_inst="1" pos="33">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_RE" node_inst="2" pos="34">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_RE" node_inst="3" pos="35">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_RE" node_inst="4" pos="36">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_RE" node_inst="5" pos="37">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_RE" node_inst="6" pos="38">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_RE" node_inst="7" pos="39">XSTOP Register - after masking - OLD XFIR</bit>
+</attn_node>
diff --git a/xml/p10/node_gfir_spa.xml b/xml/p10/node_gfir_spa.xml
new file mode 100644
index 0000000..b957190
--- /dev/null
+++ b/xml/p10/node_gfir_spa.xml
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="GFIR_SPA" reg_type="SCOM">
+ <register name="GFIR_REG_SPA">
+ <instance addr="0x570F001A" reg_inst="0"/>
+ </register>
+ <rule attn_type="SPA" node_inst="0">
+ <expr type="reg" value1="GFIR_REG_SPA"/>
+ </rule>
+ <bit child_node="CFIR_TP_SPA_UCS_HA" node_inst="0" pos="1">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_N0_SPA" node_inst="0" pos="2">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_N1_SPA" node_inst="0" pos="3">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PCI_SPA_HA" node_inst="0" pos="8">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PCI_SPA_HA" node_inst="1" pos="9">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="0" pos="12">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="1" pos="13">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="2" pos="14">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="3" pos="15">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUE_SPA" node_inst="0" pos="16">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUE_SPA" node_inst="1" pos="17">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUW_SPA" node_inst="0" pos="18">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUW_SPA" node_inst="1" pos="19">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="0" pos="24">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="1" pos="25">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="2" pos="26">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="3" pos="27">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="4" pos="28">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="5" pos="29">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="6" pos="30">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="7" pos="31">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_SPA" node_inst="0" pos="32">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_SPA" node_inst="1" pos="33">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_SPA" node_inst="2" pos="34">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_SPA" node_inst="3" pos="35">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_SPA" node_inst="4" pos="36">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_SPA" node_inst="5" pos="37">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_SPA" node_inst="6" pos="38">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_SPA" node_inst="7" pos="39">XSTOP Register - after masking - OLD XFIR</bit>
+</attn_node>
diff --git a/xml/p10/node_gfir_ucs.xml b/xml/p10/node_gfir_ucs.xml
new file mode 100644
index 0000000..99e9ed9
--- /dev/null
+++ b/xml/p10/node_gfir_ucs.xml
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="GFIR_UCS" reg_type="SCOM">
+ <register name="GFIR_REG_UCS">
+ <instance addr="0x570F002A" reg_inst="0"/>
+ </register>
+ <rule attn_type="UCS" node_inst="0">
+ <expr type="reg" value1="GFIR_REG_UCS"/>
+ </rule>
+ <bit child_node="CFIR_TP_SPA_UCS_HA" node_inst="0" pos="1">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_N0_UCS" node_inst="0" pos="2">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_N1_UCS" node_inst="0" pos="3">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PCI_UCS" node_inst="0" pos="8">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PCI_UCS" node_inst="1" pos="9">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_UCS_HA" node_inst="0" pos="12">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_UCS_HA" node_inst="1" pos="13">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_UCS_HA" node_inst="2" pos="14">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_MC_UCS_HA" node_inst="3" pos="15">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUE_UCS" node_inst="0" pos="16">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUE_UCS" node_inst="1" pos="17">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUW_UCS" node_inst="0" pos="18">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_PAUW_UCS" node_inst="1" pos="19">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_UCS_HA" node_inst="0" pos="24">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_UCS_HA" node_inst="1" pos="25">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_UCS_HA" node_inst="2" pos="26">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_UCS_HA" node_inst="3" pos="27">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_UCS_HA" node_inst="4" pos="28">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_UCS_HA" node_inst="5" pos="29">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_UCS_HA" node_inst="6" pos="30">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_IOHS_UCS_HA" node_inst="7" pos="31">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_UCS" node_inst="0" pos="32">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_UCS" node_inst="1" pos="33">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_UCS" node_inst="2" pos="34">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_UCS" node_inst="3" pos="35">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_UCS" node_inst="4" pos="36">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_UCS" node_inst="5" pos="37">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_UCS" node_inst="6" pos="38">XSTOP Register - after masking - OLD XFIR</bit>
+ <bit child_node="CFIR_EQ_UCS" node_inst="7" pos="39">XSTOP Register - after masking - OLD XFIR</bit>
+</attn_node>
diff --git a/xml/p10/node_hca_fir.xml b/xml/p10/node_hca_fir.xml
new file mode 100644
index 0000000..26e5b15
--- /dev/null
+++ b/xml/p10/node_hca_fir.xml
@@ -0,0 +1,36 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="HCA_FIR" reg_type="SCOM">
+ <local_fir config="W" name="HCA_FIR">
+ <instance addr="0x03011D40" reg_inst="0"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ </local_fir>
+ <bit pos="0">Powerbus rcmd address parity error</bit>
+ <bit pos="1">Powerbus rcmd ttag parity error</bit>
+ <bit pos="2">Powerbus cresp ttag parity error</bit>
+ <bit pos="3">Powerbus cresp atag parity error</bit>
+ <bit pos="4">HCA updt received addr_err cresp</bit>
+ <bit pos="5">HCA updt received invalid cresp</bit>
+ <bit pos="6">HCA updt received unexpected cresp</bit>
+ <bit pos="7">HCA detected powerbus hang</bit>
+ <bit pos="8">HCA rcmd hits both BARs</bit>
+ <bit pos="9">HCA cache array correctable error</bit>
+ <bit pos="10">HCA cache array uncorrectable error</bit>
+ <bit pos="11">HCA rcmd drop counter overflow</bit>
+ <bit pos="12">HCA updt command drop counter overflow</bit>
+ <bit pos="13">HCA updt lost decay request. No pbi machine available.</bit>
+ <bit pos="14">ADU or PSI SMF error</bit>
+ <bit pos="15">Spare FIR bit</bit>
+ <bit pos="16">ADU recoverable error 0</bit>
+ <bit pos="17">ADU recoverable error 1</bit>
+ <bit pos="18">ADU recoverable error 2</bit>
+ <bit pos="19">ADU recoverable error 3</bit>
+ <bit pos="20">ADU recoverable error 4</bit>
+ <bit pos="21">ADU recoverable error 5</bit>
+ <bit pos="22">ADU checkstop error 0</bit>
+ <bit pos="23">ADU checkstop error 1</bit>
+ <bit pos="24">ADU checkstop error 2</bit>
+ <bit pos="25">ADU checkstop error 3</bit>
+ <bit pos="26">ADU checkstop error 4</bit>
+ <bit pos="27">ADU checkstop error 5</bit>
+</attn_node>
diff --git a/xml/p10/node_int_cq_fir.xml b/xml/p10/node_int_cq_fir.xml
new file mode 100644
index 0000000..bbbafa3
--- /dev/null
+++ b/xml/p10/node_int_cq_fir.xml
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="INT_CQ_FIR" reg_type="SCOM">
+ <local_fir config="W" name="INT_CQ_FIR">
+ <instance addr="0x02010830" reg_inst="0"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ <action attn_type="SPA" config="10"/>
+ </local_fir>
+ <bit pos="0">Correctable ECC error detected while consuming data from the PowerBus Data ramp. See INT_CQ_ERR_INFO2 for details.</bit>
+ <bit pos="1">Uncorrectable ECC error detected while consuming data from the PowerBus Data ramp. See INT_CQ_ERR_INFO2 for details.</bit>
+ <bit pos="2">Special uncorrectable ECC error detected while consuming data on the PowerBus Data ramp for a Master DMA Read or Master CI Read.</bit>
+ <bit pos="3">Correctable ECC error detected while reading the PowerBus Data In Array. See INT_CQ_ERR_INFO2 for details.</bit>
+ <bit pos="4">Uncorrectable ECC error detected while reading the PowerBus Data In Array. See INT_CQ_ERR_INFO2 for details.</bit>
+ <bit pos="5">Correctable ECC error detected while reading the PowerBus Data Out Array. See INT_CQ_ERR_INFO2 for details.</bit>
+ <bit pos="6">Uncorrectable ECC error detected while reading the PowerBus Data Out Array. See INT_CQ_ERR_INFO2 for details.</bit>
+ <bit pos="7">Correctable ECC error detected while consuming data on the AIB Data Bus. See INT_CQ_ERR_INFO2 for details.</bit>
+ <bit pos="8">Uncorrectable ECC error detected while consuming data on the AIB Data Bus. See INT_CQ_ERR_INFO2 for details.</bit>
+ <bit pos="9">Received an unsolicited master Combined Response - The master cResp tTag(0:11) matched my topology ID and unit ID, but tTag(12:19) pointed to TxIDs</bit>
+ <bit pos="10">Received unsolicited PowerBus data - The rTag(0:11) of incoming PB data matched my topology ID and unit ID, but rTag(12:19) pointed to TxIDs that</bit>
+ <bit pos="11">Parity error detected on AIB credit signals from PC</bit>
+ <bit pos="12">Parity error detected on AIB credit available signals from PC</bit>
+ <bit pos="13">Parity error detected on AIB credit signals from VC</bit>
+ <bit pos="14">Parity error detected on AIB credit available signals from VC</bit>
+ <bit pos="15">Parity error detected on AIB Command Control</bit>
+ <bit pos="16">Parity error detected on AIB Command Bus</bit>
+ <bit pos="17">Parity error detected on AIB Data Control</bit>
+ <bit pos="18">Parity error detected on one of the following PowerBus interfaces (Rcmdx, cRespx, Data rtag). See INT_CQ_ERR_INFO0 for details.</bit>
+ <bit pos="19">Slave CI Store or CI Load to an improper location. This includes a Read targeting a WO space, a Write targeting a RO space, or targeting reserved</bit>
+ <bit pos="20">Slave CI Store or CI Load to an invalid Set Translation Table entry (that are associated with the NVPG, NVC, ESB and END BARs).</bit>
+ <bit pos="21">Slave CI Store or CI Load (that targets the IC_BAR) with a size violation, alignment problem, or comes from an unsupported source.</bit>
+ <bit pos="22">Slave CI Store or CI Load (that does not target the IC_BAR) with a size violation, alignment problem or comes from an unsupported source.</bit>
+ <bit pos="23">Migration Register Table (MRT) access - invalid entry selected.</bit>
+ <bit pos="24">Migration Register Table (MRT) access - The Table Size received in the AIB command is greater than the Target Page Size in the MRT entry.</bit>
+ <bit pos="25">SCOM satellite error</bit>
+ <bit pos="26">Topology ID Index Translation Table Entry Invalid - When INT initiates a master op (Read or Write) on the PowerBus, in determining the initial</bit>
+ <bit pos="27">Master Write Queue has flagged a PowerBus operational hang</bit>
+ <bit pos="28">Master Read Queue has flagged a PowerBus operational hang</bit>
+ <bit pos="29">Master Interrupt Queue has flagged a PowerBus operational hang</bit>
+ <bit pos="30">Master Read Queue has flagged a PowerBus data hang</bit>
+ <bit pos="31">CI Store Queue has flagged a PowerBus data hang</bit>
+ <bit pos="32">CI Load Queue has flagged an AIB data hang - Once a CI Load request has been sent on AIB, I use the PowerBus data hang timer mechanism (the</bit>
+ <bit pos="33">Bad cResp received during a Master Write command.</bit>
+ <bit pos="34">Bad cResp received during a Master Read command.</bit>
+ <bit pos="35">Bad cResp received during a Master Interrupt command.</bit>
+ <bit pos="36">A Master Read machine received cResp of abort_trm or abort_trm_ed. In addition to setting this error bit, the Read machine behaved as if the cResp was</bit>
+ <bit pos="37">Master Interrupt Protocol Error - The PowerBus cResp to a master interrupt command was a response that should never happen. In the P10 INT Workbook,</bit>
+ <bit pos="38">Master Memory Op Targeted Secure Memory - VC or PC sent CQ a memory operation with the secure RA bit (bit 12) = 1 while SMF is enabled.</bit>
+ <bit pos="39">AIB Fence Raised - This bit is set whenever CQ, PC, or VC assert "AIB Fence". This bit is useful to know if AIB fence was raised before another FIR</bit>
+ <bit pos="40">Parity error detected on CQs configuration registers.</bit>
+ <bit pos="41">Reserved</bit>
+ <bit pos="42">Command Queue (FSM) severe error summary. See INT_CQ_ERR_INFO3 for details. This includes queue overflows and FSM parity errors.</bit>
+ <bit pos="43">PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)</bit>
+ <bit pos="44">PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)</bit>
+ <bit pos="45">PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)</bit>
+ <bit pos="46">PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)</bit>
+ <bit pos="47">PC recoverable error summary, as indicated on pc_cq_recov_error(0:3)</bit>
+ <bit pos="48">PC recoverable error summary, as indicated on pc_cq_recov_error(0:3)</bit>
+ <bit pos="49">PC recoverable error summary, as indicated on pc_cq_recov_error(0:3)</bit>
+ <bit pos="50">PC recoverable error summary, as indicated on pc_cq_recov_error(0:3)</bit>
+ <bit pos="51">PC informational error summary, as indicated on pc_cq_info_error(0:3)</bit>
+ <bit pos="52">PC informational error summary, as indicated on pc_cq_info_error(0:3)</bit>
+ <bit pos="53">PC informational error summary, as indicated on pc_cq_info_error(0:3)</bit>
+ <bit pos="54">PC informational error summary, as indicated on pc_cq_info_error(0:3)</bit>
+ <bit pos="55">VC fatal error summary, as indicated on vc_cq_fatal_error(0:2)</bit>
+ <bit pos="56">VC fatal error summary, as indicated on vc_cq_fatal_error(0:2)</bit>
+ <bit pos="57">VC fatal error summary, as indicated on vc_cq_fatal_error(0:2)</bit>
+ <bit pos="58">VC recoverable error summary, as indicated on vc_cq_recov_error(0:2)</bit>
+ <bit pos="59">VC recoverable error summary, as indicated on vc_cq_recov_error(0:2)</bit>
+ <bit pos="60">VC recoverable error summary, as indicated on vc_cq_recov_error(0:2)</bit>
+ <bit pos="61">VC informational error summary, as indicated on vc_cq_info_error(0:2)</bit>
+ <bit pos="62">VC informational error summary, as indicated on vc_cq_info_error(0:2)</bit>
+ <bit pos="63">VC informational error summary, as indicated on vc_cq_info_error(0:2)</bit>
+</attn_node>
diff --git a/xml/p10/node_iohs_dlp_fir.xml b/xml/p10/node_iohs_dlp_fir.xml
new file mode 100644
index 0000000..436a42c
--- /dev/null
+++ b/xml/p10/node_iohs_dlp_fir.xml
@@ -0,0 +1,78 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="IOHS_DLP_FIR" reg_type="SCOM">
+ <local_fir config="W" name="IOHS_DLP_FIR">
+ <instance addr="0x18011000" reg_inst="0"/>
+ <instance addr="0x19011000" reg_inst="1"/>
+ <instance addr="0x1A011000" reg_inst="2"/>
+ <instance addr="0x1B011000" reg_inst="3"/>
+ <instance addr="0x1C011000" reg_inst="4"/>
+ <instance addr="0x1D011000" reg_inst="5"/>
+ <instance addr="0x1E011000" reg_inst="6"/>
+ <instance addr="0x1F011000" reg_inst="7"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ <action attn_type="SPA" config="10"/>
+ </local_fir>
+ <bit pos="0">OLL link0 trained</bit>
+ <bit pos="1">OLL link1 trained</bit>
+ <bit pos="2">link0 op irq</bit>
+ <bit pos="3">link1 op irq</bit>
+ <bit pos="4">link0 replay threshold</bit>
+ <bit pos="5">link1 replay threshold</bit>
+ <bit pos="6">link0 crc error</bit>
+ <bit pos="7">link1 crc error</bit>
+ <bit pos="8">link0 nak received</bit>
+ <bit pos="9">link1 nak received</bit>
+ <bit pos="10">link0 replay buffer full</bit>
+ <bit pos="11">link1 replay buffer full</bit>
+ <bit pos="12">link0 sl ecc threshold</bit>
+ <bit pos="13">link1 sl ecc threshold</bit>
+ <bit pos="14">link0 sl ecc correctable</bit>
+ <bit pos="15">link1 sl ecc correctable</bit>
+ <bit pos="16">link0 sl ecc ue</bit>
+ <bit pos="17">link1 sl ecc ue</bit>
+ <bit pos="18">link0 retrain threshold</bit>
+ <bit pos="19">link1 retrain threshold</bit>
+ <bit pos="20">link0 loss block align</bit>
+ <bit pos="21">link1 loss block align</bit>
+ <bit pos="22">link0 invalid block</bit>
+ <bit pos="23">link1 invalid block</bit>
+ <bit pos="24">link0 deskew error</bit>
+ <bit pos="25">link1 deskew error</bit>
+ <bit pos="26">link0 deskew overflow</bit>
+ <bit pos="27">link1 deskew overflow</bit>
+ <bit pos="28">link0 sw retrain</bit>
+ <bit pos="29">link1 sw retrain</bit>
+ <bit pos="30">link0 ack queue overflow</bit>
+ <bit pos="31">link1 ack queue overflow</bit>
+ <bit pos="32">link0 ack queue underflow</bit>
+ <bit pos="33">link1 ack queue underflow</bit>
+ <bit pos="34">link0 num replay</bit>
+ <bit pos="35">link1 num replay</bit>
+ <bit pos="36">link0 training set received</bit>
+ <bit pos="37">link1 training set received</bit>
+ <bit pos="38">link0 prbs select error</bit>
+ <bit pos="39">link1 prbs select error</bit>
+ <bit pos="40">link0 tcomplete bad</bit>
+ <bit pos="41">link1 tcomplete bad</bit>
+ <bit pos="42">link0 no spare lane available</bit>
+ <bit pos="43">link1 no spare lane available</bit>
+ <bit pos="44">link0 spare done</bit>
+ <bit pos="45">link1 spare done</bit>
+ <bit pos="46">link0 too many crc errors</bit>
+ <bit pos="47">link1 too many crc errors</bit>
+ <bit pos="48">link0 npu/dlx error</bit>
+ <bit pos="49">link1 npu/dlx error</bit>
+ <bit pos="50">link0 osc switch</bit>
+ <bit pos="51">link1 osc switch</bit>
+ <bit pos="52">link0 correctable array error</bit>
+ <bit pos="53">link1 correctable array error</bit>
+ <bit pos="54">link0 uncorrectable array error</bit>
+ <bit pos="55">link1 uncorrectable array error</bit>
+ <bit pos="56">link0 training failed</bit>
+ <bit pos="57">link1 training failed</bit>
+ <bit pos="58">link0 unrecoverable error</bit>
+ <bit pos="59">link1 unrecoverable error</bit>
+ <bit pos="60">link0 internal error</bit>
+ <bit pos="61">link1 internal error</bit>
+</attn_node>
diff --git a/xml/p10/node_iohs_local_fir.xml b/xml/p10/node_iohs_local_fir.xml
new file mode 100644
index 0000000..dd90685
--- /dev/null
+++ b/xml/p10/node_iohs_local_fir.xml
@@ -0,0 +1,82 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="IOHS_LOCAL_FIR" reg_type="SCOM">
+ <local_fir config="W2" name="IOHS_LOCAL_FIR">
+ <instance addr="0x18040100" reg_inst="0"/>
+ <instance addr="0x19040100" reg_inst="1"/>
+ <instance addr="0x1A040100" reg_inst="2"/>
+ <instance addr="0x1B040100" reg_inst="3"/>
+ <instance addr="0x1C040100" reg_inst="4"/>
+ <instance addr="0x1D040100" reg_inst="5"/>
+ <instance addr="0x1E040100" reg_inst="6"/>
+ <instance addr="0x1F040100" reg_inst="7"/>
+ <action attn_type="CS" config="000"/>
+ <action attn_type="RE" config="010"/>
+ <action attn_type="SPA" config="100"/>
+ <action attn_type="UCS" config="110"/>
+ <action attn_type="HA" config="001"/>
+ </local_fir>
+ <bit pos="0">CFIR - Parity or PCB access error</bit>
+ <bit pos="1">CPLT_CTRL - PCB access error</bit>
+ <bit pos="2">CC - PCB access error - read and clear nn03000F</bit>
+ <bit pos="3">CC - Clock Control Error - read and clear nn03000F</bit>
+ <bit pos="4">PSC - PSCOM access error - read and clear nn01001</bit>
+ <bit pos="5">PSC - internal or ring interface error - read and clear nn01001</bit>
+ <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050013</bit>
+ <bit pos="7">THERM - pcb error</bit>
+ <bit pos="8">THERMTRIP - Critical temperature indicator</bit>
+ <bit pos="9">THERMTRIP - Fatal temperature indicator</bit>
+ <bit pos="10">VOLTTRIP - Voltage sense error</bit>
+ <bit pos="11">DBG - scom parity fail</bit>
+ <bit pos="12">reserved</bit>
+ <bit pos="13">reserved</bit>
+ <bit pos="14">reserved</bit>
+ <bit pos="15">reserved</bit>
+ <bit pos="16">reserved</bit>
+ <bit pos="17">reserved</bit>
+ <bit pos="18">reserved</bit>
+ <bit pos="19">reserved</bit>
+ <bit pos="20">Trace00 - scom parity err</bit>
+ <bit pos="21">Trace01 - scom parity err - Unused in Axon,PCI</bit>
+ <bit pos="22">unused</bit>
+ <bit pos="23">unused</bit>
+ <bit pos="24">unused</bit>
+ <bit pos="25">unused</bit>
+ <bit pos="26">unused</bit>
+ <bit pos="27">unused</bit>
+ <bit pos="28">unused</bit>
+ <bit pos="29">unused</bit>
+ <bit pos="30">unused</bit>
+ <bit pos="31">unused</bit>
+ <bit pos="32">unused</bit>
+ <bit pos="33">unused</bit>
+ <bit pos="34">unused</bit>
+ <bit pos="35">unused</bit>
+ <bit pos="36">unused</bit>
+ <bit pos="37">unused</bit>
+ <bit pos="38">unused</bit>
+ <bit pos="39">unused</bit>
+ <bit pos="40">unused</bit>
+ <bit pos="41">unused</bit>
+ <bit pos="42">unused</bit>
+ <bit pos="43">unused</bit>
+ <bit pos="44">unused</bit>
+ <bit pos="45">unused</bit>
+ <bit pos="46">unused</bit>
+ <bit pos="47">unused</bit>
+ <bit pos="48">unused</bit>
+ <bit pos="49">unused</bit>
+ <bit pos="50">unused</bit>
+ <bit pos="51">unused</bit>
+ <bit pos="52">unused</bit>
+ <bit pos="53">unused</bit>
+ <bit pos="54">unused</bit>
+ <bit pos="55">unused</bit>
+ <bit pos="56">unused</bit>
+ <bit pos="57">unused</bit>
+ <bit pos="58">unused</bit>
+ <bit pos="59">unused</bit>
+ <bit pos="60">unused</bit>
+ <bit pos="61">unused</bit>
+ <bit pos="62">unused</bit>
+ <bit pos="63">ext_local_xstop</bit>
+</attn_node>
diff --git a/xml/p10/node_lpc_fir.xml b/xml/p10/node_lpc_fir.xml
new file mode 100644
index 0000000..d8448b2
--- /dev/null
+++ b/xml/p10/node_lpc_fir.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="LPC_FIR" reg_type="SCOM">
+ <local_fir config="W" name="LPC_FIR">
+ <instance addr="0x03012000" reg_inst="0"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ </local_fir>
+ <bit pos="0">OPB_Master_LS_received_a_transfer_size_value_unequal_to_1-_or_2-_or_4-Byte</bit>
+ <bit pos="1">OPB_Master_LS_received_a_invalid_command_no_ci_store_and_no_ci_load</bit>
+ <bit pos="2">OPB_Master_LS_received_a_address_which_was_not_aligned_to_the_received_transfer_size</bit>
+ <bit pos="3">OPB_Master_LS_detected_OPB_ErrAck_which_was_activated_by_the_accessed_OPB_slave</bit>
+ <bit pos="4">the_OPB_arbiter_activated_the_OPB_Timeout_signal_Typical_reason_is_that_the_OPB_access_did_not_hit_any_available_OPB_slave</bit>
+ <bit pos="5">the_OPB_Master_LS_was_not_able_to_end_the_requested_OPB_access_within_the_OPB_Master_LS_hang_timeout_time</bit>
+ <bit pos="6">a parity_error_was_detected_in_the_OPB_Master_LS_command_buffer</bit>
+ <bit pos="7">a parity_error_was_detected_in_the_OPB_Master_LS_data_buffer</bit>
+ <bit pos="8">reserved_bit_1_tied_to_zero</bit>
+ <bit pos="9">reserved_bit_0_tied_to_zero</bit>
+</attn_node>
diff --git a/xml/p10/node_mc_dstl_fir.xml b/xml/p10/node_mc_dstl_fir.xml
new file mode 100644
index 0000000..5de66eb
--- /dev/null
+++ b/xml/p10/node_mc_dstl_fir.xml
@@ -0,0 +1,57 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="MC_DSTL_FIR" reg_type="SCOM">
+ <local_fir config="W2" name="MC_DSTL_FIR">
+ <instance addr="0x0C010D00" reg_inst="0"/>
+ <instance addr="0x0C010D40" reg_inst="1"/>
+ <instance addr="0x0D010D00" reg_inst="2"/>
+ <instance addr="0x0D010D40" reg_inst="3"/>
+ <instance addr="0x0E010D00" reg_inst="4"/>
+ <instance addr="0x0E010D40" reg_inst="5"/>
+ <instance addr="0x0F010D00" reg_inst="6"/>
+ <instance addr="0x0F010D40" reg_inst="7"/>
+ <action attn_type="CS" config="000"/>
+ <action attn_type="RE" config="010"/>
+ <action attn_type="SPA" config="100"/>
+ <action attn_type="UCS" config="110"/>
+ <action attn_type="HA" config="001"/>
+ </local_fir>
+ <bit pos="0">AFU initiated Checkstop on Subchannel A</bit>
+ <bit pos="1">AFU initiated Recoverable Attention on Subchannel A</bit>
+ <bit pos="2">AFU initiated Special Attention on Subchannel A</bit>
+ <bit pos="3">AFU initiated Application Interrupt Attention on Subchannel A</bit>
+ <bit pos="4">AFU initiated Checkstop on Subchannel B</bit>
+ <bit pos="5">AFU initiated Recoverable Attention on Subchannel B</bit>
+ <bit pos="6">AFU initiated Special Attention on Subchannel B</bit>
+ <bit pos="7">AFU initiated Application Interrupt Attention on Subchannel B</bit>
+ <bit pos="8">Error on parity bits protecting incoming command from MCS to DSTL.</bit>
+ <bit pos="9">A credit reset was attempted while rd and wdf buffers in use.</bit>
+ <bit pos="10">DSTL Configuration Register has taken a recoverable parity error.</bit>
+ <bit pos="11">DSTL Configuration Register has taken a fatal parity error.</bit>
+ <bit pos="12">DSTL Subchannel A, a counter took an underflow or overflow error.</bit>
+ <bit pos="13">DSTL Subchannel B, a counter took an underflow or overflow error.</bit>
+ <bit pos="14">DSTL Subchannel A timed out having valid commands and not sending any flits.</bit>
+ <bit pos="15">DSTL Subchannel B timed out having valid commands and not sending any flits.</bit>
+ <bit pos="16">DSTL has detected that attached buffer on subchannel A has used more tlxvc0 or tlxvc3 credits than it has been given.</bit>
+ <bit pos="17">DSTL has detected that attached buffer on subchannel B has used more tlxvc0 or tlxvc3 credits than it has been given.</bit>
+ <bit pos="18">DSTL Subchannel A observed link going down.</bit>
+ <bit pos="19">DSTL Subchannel B observed link going down.</bit>
+ <bit pos="20">DSTL Subchannel A has entered the fail state.</bit>
+ <bit pos="21">DSTL Subchannel B has entered the fail state.</bit>
+ <bit pos="22">Channel timeout has occured on Subchannel A index.</bit>
+ <bit pos="23">Channel timeout has occured on Subchannel B index.</bit>
+ <bit pos="24">Error info from decrypt</bit>
+ <bit pos="25">Error info from decrypt</bit>
+ <bit pos="26">Error info from decrypt</bit>
+ <bit pos="27">Error info from decrypt</bit>
+ <bit pos="28">Error info from decrypt</bit>
+ <bit pos="29">Error info from encrypt</bit>
+ <bit pos="30">Error info from encrypt</bit>
+ <bit pos="31">Error info from encrypt</bit>
+ <bit pos="32">Error info from encrypt</bit>
+ <bit pos="33">On Subchhanel A, received an AFU initiated Application Interrupt Attention when one was already being processed and issued a retry.</bit>
+ <bit pos="34">On Subchhanel B, received an AFU initiated Application Interrupt Attention when one was already being processed and issued a retry.</bit>
+ <bit pos="35">A parity error local to Subchhanel A occurred.</bit>
+ <bit pos="36">A parity error local to Subchhanel B occurred.</bit>
+ <bit pos="37">Spare FIR bit 37.</bit>
+ <bit pos="38">Spare FIR bit 38.</bit>
+</attn_node>
diff --git a/xml/p10/node_mc_fir.xml b/xml/p10/node_mc_fir.xml
new file mode 100644
index 0000000..18bcd59
--- /dev/null
+++ b/xml/p10/node_mc_fir.xml
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="MC_FIR" reg_type="SCOM">
+ <local_fir config="W2" name="MC_FIR">
+ <instance addr="0x0C010C00" reg_inst="0"/>
+ <instance addr="0x0D010C00" reg_inst="1"/>
+ <instance addr="0x0E010C00" reg_inst="2"/>
+ <instance addr="0x0F010C00" reg_inst="3"/>
+ <action attn_type="CS" config="000"/>
+ <action attn_type="RE" config="010"/>
+ <action attn_type="SPA" config="100"/>
+ <action attn_type="UCS" config="110"/>
+ <action attn_type="HA" config="001"/>
+ </local_fir>
+ <bit pos="0">If '1', a MC recoverable error was detected. See the MCERPTx register description for a list of errors that cause this FIR to be set.</bit>
+ <bit pos="1">If 1, a MC non-recoverable error was detected. See the MCERPTx register description for a list of errors that cause this FIR to be set.</bit>
+ <bit pos="2">If '1', an PowerBus protocol error was detected. (for example, a HPC_WR is snooped when a HPC_WR to the same address is active).</bit>
+ <bit pos="3">If '1', a command was issued to inband address space using a</bit>
+ <bit pos="4">If '1', an address match on more that one Memory BAR was detected.</bit>
+ <bit pos="5">Commandlist early hang trigger activated</bit>
+ <bit pos="6">Reserved[6].</bit>
+ <bit pos="7">Reserved[7].</bit>
+ <bit pos="8">If '1', a command list state machine has timed out.</bit>
+ <bit pos="9">Reserved[9].</bit>
+ <bit pos="10">Reserved[10].</bit>
+ <bit pos="11">If '1', a MCS WAT0 event has occurred.</bit>
+ <bit pos="12">If '1', a MCS WAT1 event has occurred.</bit>
+ <bit pos="13">If '1', a MCS WAT2 event has occurred.</bit>
+ <bit pos="14">If '1', a MCS WAT3 event has occurred.</bit>
+ <bit pos="15">Plus One Prefetch generated command did not hit any BARs</bit>
+ <bit pos="16">Plus One Prefetch generated command hit config or mmio BAR</bit>
+ <bit pos="17">Parity Error in WAT/Debug config register.</bit>
+ <bit pos="18">Reserved[18].</bit>
+ <bit pos="19">Reserved[19].</bit>
+ <bit pos="20">Incoming Powerbus Command hit multiple valid configured topology IDs</bit>
+ <bit pos="21">Reserved[21].</bit>
+ <bit pos="22">Access to secure memory facility failed. Improper access privilege by originating thread.</bit>
+ <bit pos="23">Caused by multiple sync commands being received by an MC at a time, or while one is pending</bit>
+</attn_node>
diff --git a/xml/p10/node_mc_local_fir.xml b/xml/p10/node_mc_local_fir.xml
new file mode 100644
index 0000000..6d2f021
--- /dev/null
+++ b/xml/p10/node_mc_local_fir.xml
@@ -0,0 +1,78 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="MC_LOCAL_FIR" reg_type="SCOM">
+ <local_fir config="W2" name="MC_LOCAL_FIR">
+ <instance addr="0x0C040100" reg_inst="0"/>
+ <instance addr="0x0D040100" reg_inst="1"/>
+ <instance addr="0x0E040100" reg_inst="2"/>
+ <instance addr="0x0F040100" reg_inst="3"/>
+ <action attn_type="CS" config="000"/>
+ <action attn_type="RE" config="010"/>
+ <action attn_type="SPA" config="100"/>
+ <action attn_type="UCS" config="110"/>
+ <action attn_type="HA" config="001"/>
+ </local_fir>
+ <bit pos="0">CFIR - Parity or PCB access error</bit>
+ <bit pos="1">CPLT_CTRL - PCB access error</bit>
+ <bit pos="2">CC - PCB access error - read and clear nn03000F</bit>
+ <bit pos="3">CC - Clock Control Error - read and clear nn03000F</bit>
+ <bit pos="4">PSC - PSCOM access error - read and clear nn01001</bit>
+ <bit pos="5">PSC - internal or ring interface error - read and clear nn01001</bit>
+ <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050013</bit>
+ <bit pos="7">THERM - pcb error</bit>
+ <bit pos="8">THERMTRIP - Critical temperature indicator</bit>
+ <bit pos="9">THERMTRIP - Fatal temperature indicator</bit>
+ <bit pos="10">VOLTTRIP - Voltage sense error</bit>
+ <bit pos="11">DBG - scom parity fail</bit>
+ <bit pos="12">reserved</bit>
+ <bit pos="13">reserved</bit>
+ <bit pos="14">reserved</bit>
+ <bit pos="15">reserved</bit>
+ <bit pos="16">reserved</bit>
+ <bit pos="17">reserved</bit>
+ <bit pos="18">reserved</bit>
+ <bit pos="19">reserved</bit>
+ <bit pos="20">Trace00 - scom parity err</bit>
+ <bit pos="21">Trace01 - scom parity err - Unused in Axon,PCI</bit>
+ <bit pos="22">unused</bit>
+ <bit pos="23">unused</bit>
+ <bit pos="24">unused</bit>
+ <bit pos="25">unused</bit>
+ <bit pos="26">unused</bit>
+ <bit pos="27">unused</bit>
+ <bit pos="28">unused</bit>
+ <bit pos="29">unused</bit>
+ <bit pos="30">unused</bit>
+ <bit pos="31">unused</bit>
+ <bit pos="32">unused</bit>
+ <bit pos="33">unused</bit>
+ <bit pos="34">unused</bit>
+ <bit pos="35">unused</bit>
+ <bit pos="36">unused</bit>
+ <bit pos="37">unused</bit>
+ <bit pos="38">unused</bit>
+ <bit pos="39">unused</bit>
+ <bit pos="40">unused</bit>
+ <bit pos="41">unused</bit>
+ <bit pos="42">unused</bit>
+ <bit pos="43">unused</bit>
+ <bit pos="44">unused</bit>
+ <bit pos="45">unused</bit>
+ <bit pos="46">unused</bit>
+ <bit pos="47">unused</bit>
+ <bit pos="48">unused</bit>
+ <bit pos="49">unused</bit>
+ <bit pos="50">unused</bit>
+ <bit pos="51">unused</bit>
+ <bit pos="52">unused</bit>
+ <bit pos="53">unused</bit>
+ <bit pos="54">unused</bit>
+ <bit pos="55">unused</bit>
+ <bit pos="56">unused</bit>
+ <bit pos="57">unused</bit>
+ <bit pos="58">unused</bit>
+ <bit pos="59">unused</bit>
+ <bit pos="60">unused</bit>
+ <bit pos="61">unused</bit>
+ <bit pos="62">unused</bit>
+ <bit pos="63">ext_local_xstop</bit>
+</attn_node>
diff --git a/xml/p10/node_mc_misc_fir.xml b/xml/p10/node_mc_misc_fir.xml
new file mode 100644
index 0000000..78681c5
--- /dev/null
+++ b/xml/p10/node_mc_misc_fir.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="MC_MISC_FIR" reg_type="SCOM">
+ <local_fir config="W2" name="MC_MISC_FIR">
+ <instance addr="0x0C010F00" reg_inst="0"/>
+ <instance addr="0x0D010F00" reg_inst="1"/>
+ <instance addr="0x0E010F00" reg_inst="2"/>
+ <instance addr="0x0F010F00" reg_inst="3"/>
+ <action attn_type="CS" config="000"/>
+ <action attn_type="RE" config="010"/>
+ <action attn_type="SPA" config="100"/>
+ <action attn_type="UCS" config="110"/>
+ <action attn_type="HA" config="001"/>
+ </local_fir>
+ <bit pos="0">WAT Debug Bus Attention. This is a way for the WAT debug bus to trigger an attention.</bit>
+ <bit pos="1">SCOM DBGSRC Register parity Error. Indicates that control register for Debug logic has taken a parity error.</bit>
+ <bit pos="2">SCOM Recoverable Register Parity Error. This bit is set when a recoverable parity error on SCOM registers AACR or MCDBG_SCOM_CFG takes place. These register errors are config-related, unable to corrupt data or mainline.</bit>
+ <bit pos="3">Spare fir; hooked up to the parity error dectect of the SPARE scom register</bit>
+ <bit pos="4">Indicates that an application interrupt was received from the OCMB on</bit>
+ <bit pos="5">Indicates that an application interrupt was received from the OCMB on</bit>
+ <bit pos="6">Indicates that an application interrupt was received from the OCMB on</bit>
+ <bit pos="7">Indicates that an application interrupt was received from the OCMB on</bit>
+ <bit pos="8">Parity Error taken on MCEBUSEN[0,1,2,3] regs.</bit>
+ <bit pos="9">Parity Error taken on WAT* Regs.</bit>
+ <bit pos="10">Reserved Fir Bit 10.</bit>
+ <bit pos="11">Reserved Fir Bit 11.</bit>
+</attn_node>
diff --git a/xml/p10/node_mc_omi_dl_fir.xml b/xml/p10/node_mc_omi_dl_fir.xml
new file mode 100644
index 0000000..6ba1924
--- /dev/null
+++ b/xml/p10/node_mc_omi_dl_fir.xml
@@ -0,0 +1,78 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="MC_OMI_DL_FIR" reg_type="SCOM">
+ <local_fir config="W" name="MC_OMI_DL_FIR">
+ <instance addr="0x0C011400" reg_inst="0"/>
+ <instance addr="0x0C011800" reg_inst="1"/>
+ <instance addr="0x0D011400" reg_inst="2"/>
+ <instance addr="0x0D011800" reg_inst="3"/>
+ <instance addr="0x0E011400" reg_inst="4"/>
+ <instance addr="0x0E011800" reg_inst="5"/>
+ <instance addr="0x0F011400" reg_inst="6"/>
+ <instance addr="0x0F011800" reg_inst="7"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ <action attn_type="SPA" config="10"/>
+ </local_fir>
+ <bit pos="0">OMI-DL0 fatal_error - see error hold register(54 to 63) for details</bit>
+ <bit pos="1">OMI-DL0 UE on data flit - see error hold register(50 to 51) for details</bit>
+ <bit pos="2">OMI-DL0 CE on TL flit - see error hold register(48 to 49) for details</bit>
+ <bit pos="3">OMI-DL0 detected a CRC error</bit>
+ <bit pos="4">OMI-DL0 received a nack</bit>
+ <bit pos="5">OMI-DL0 running in degraded mode - see error hold register(44 to 45) for details</bit>
+ <bit pos="6">OMI-DL0 parity error detection on a lane - see error hold register(34 to 43) for details</bit>
+ <bit pos="7">OMI-DL0 retrained due to no forward progress</bit>
+ <bit pos="8">OMI-DL0 remote side initiated a retrain</bit>
+ <bit pos="9">OMI-DL0 retrain due to internal error or software initiated - see error hold register(28 to 31) for details</bit>
+ <bit pos="10">OMI-DL0 threshold reached - see error hold register(25 to 27) for details</bit>
+ <bit pos="11">OMI-DL0 trained</bit>
+ <bit pos="12">OMI-DL0 endpoint error bit 0</bit>
+ <bit pos="13">OMI-DL0 endpoint error bit 1</bit>
+ <bit pos="14">OMI-DL0 endpoint error bit 2</bit>
+ <bit pos="15">OMI-DL0 endpoint error bit 3</bit>
+ <bit pos="16">OMI-DL0 endpoint error bit 4</bit>
+ <bit pos="17">OMI-DL0 endpoint error bit 5</bit>
+ <bit pos="18">OMI-DL0 endpoint error bit 6</bit>
+ <bit pos="19">OMI-DL0 endpoint error bit 7</bit>
+ <bit pos="20">OMI-DL1 fatal_error - see error hold register(54 to 63) for details</bit>
+ <bit pos="21">OMI-DL1 UE on data flit - see error hold register(50 to 51) for details</bit>
+ <bit pos="22">OMI-DL1 CE on TL flit - see error hold register(48 to 49) for details</bit>
+ <bit pos="23">OMI-DL1 detected a CRC error</bit>
+ <bit pos="24">OMI-DL1 received a nack</bit>
+ <bit pos="25">OMI-DL1 running in degraded mode - see error hold register(44 to 45) for details</bit>
+ <bit pos="26">OMI-DL1 parity error detection on a lane - see error hold register(34 to 43) for details</bit>
+ <bit pos="27">OMI-DL1 retrained due to no forward progress</bit>
+ <bit pos="28">OMI-DL1 remote side initiated a retrain</bit>
+ <bit pos="29">OMI-DL1 retrain due to internal error or software initiated - see error hold register(28 to 31) for details</bit>
+ <bit pos="30">OMI-DL1 threshold reached - see error hold register(25 to 27) for details</bit>
+ <bit pos="31">OMI-DL1 trained</bit>
+ <bit pos="32">OMI-DL1 endpoint error bit 0</bit>
+ <bit pos="33">OMI-DL1 endpoint error bit 1</bit>
+ <bit pos="34">OMI-DL1 endpoint error bit 2</bit>
+ <bit pos="35">OMI-DL1 endpoint error bit 3</bit>
+ <bit pos="36">OMI-DL1 endpoint error bit 4</bit>
+ <bit pos="37">OMI-DL1 endpoint error bit 5</bit>
+ <bit pos="38">OMI-DL1 endpoint error bit 6</bit>
+ <bit pos="39">OMI-DL1 endpoint error bit 7</bit>
+ <bit pos="40">OMI-DL2 unused</bit>
+ <bit pos="41">OMI-DL2 unused</bit>
+ <bit pos="42">OMI-DL2 unused</bit>
+ <bit pos="43">OMI-DL2 unused</bit>
+ <bit pos="44">OMI-DL2 unused</bit>
+ <bit pos="45">OMI-DL2 unused</bit>
+ <bit pos="46">OMI-DL2 unused</bit>
+ <bit pos="47">OMI-DL2 unused</bit>
+ <bit pos="48">OMI-DL2 unused</bit>
+ <bit pos="49">OMI-DL2 unused</bit>
+ <bit pos="50">OMI-DL2 unused</bit>
+ <bit pos="51">OMI-DL2 unused</bit>
+ <bit pos="52">OMI-DL2 unused</bit>
+ <bit pos="53">OMI-DL2 unused</bit>
+ <bit pos="54">OMI-DL2 unused</bit>
+ <bit pos="55">OMI-DL2 unused</bit>
+ <bit pos="56">OMI-DL2 unused</bit>
+ <bit pos="57">OMI-DL2 unused</bit>
+ <bit pos="58">OMI-DL2 unused</bit>
+ <bit pos="59">OMI-DL2 unused</bit>
+ <bit pos="60">performance monitor wrapped</bit>
+ <bit pos="61">OMI-DL common FIR Register</bit>
+</attn_node>
diff --git a/xml/p10/node_mc_ustl_fir.xml b/xml/p10/node_mc_ustl_fir.xml
new file mode 100644
index 0000000..c487b59
--- /dev/null
+++ b/xml/p10/node_mc_ustl_fir.xml
@@ -0,0 +1,80 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="MC_USTL_FIR" reg_type="SCOM">
+ <local_fir config="W2" name="MC_USTL_FIR">
+ <instance addr="0x0C010E00" reg_inst="0"/>
+ <instance addr="0x0C010E40" reg_inst="1"/>
+ <instance addr="0x0D010E00" reg_inst="2"/>
+ <instance addr="0x0D010E40" reg_inst="3"/>
+ <instance addr="0x0E010E00" reg_inst="4"/>
+ <instance addr="0x0E010E40" reg_inst="5"/>
+ <instance addr="0x0F010E00" reg_inst="6"/>
+ <instance addr="0x0F010E40" reg_inst="7"/>
+ <action attn_type="CS" config="000"/>
+ <action attn_type="RE" config="010"/>
+ <action attn_type="SPA" config="100"/>
+ <action attn_type="UCS" config="110"/>
+ <action attn_type="HA" config="001"/>
+ </local_fir>
+ <bit pos="0">Unexpected Flit Data showed up for Chana</bit>
+ <bit pos="1">Unexpected Flit Data showed up for Chanb</bit>
+ <bit pos="2">A unsupported template for a command flit for chana</bit>
+ <bit pos="3">A unsupported template for a command flit for chanb</bit>
+ <bit pos="4">Reserved.</bit>
+ <bit pos="5">Reserved.</bit>
+ <bit pos="6">WDF CE detected on buffer output</bit>
+ <bit pos="7">WDF UE detected on buffer output</bit>
+ <bit pos="8">WDF SUE detected on buffer output</bit>
+ <bit pos="9">WDF buffer overrun detected</bit>
+ <bit pos="10">WDF detected parity on USTL tag interface</bit>
+ <bit pos="11">WDF detected a scom sequencer error</bit>
+ <bit pos="12">WDF detected a pwctl sequencer error</bit>
+ <bit pos="13">WDF detected a parity error on the misc_reg scom register</bit>
+ <bit pos="14">Parity Error detected in WDF for CL pop</bit>
+ <bit pos="15">WDF detected a non-zero syndrome (CE ore UE) from USTL</bit>
+ <bit pos="16">WDF UE detected a parity error on the CMT interface from USTL, cmd parity err, or buffer manager parity error</bit>
+ <bit pos="17">Unused</bit>
+ <bit pos="18">Unused</bit>
+ <bit pos="19">Read Buffers overflowed/underflowed (more than 64 in use)</bit>
+ <bit pos="20">WRT CE detected on buffer output</bit>
+ <bit pos="21">WRT UE detected on buffer output</bit>
+ <bit pos="22">WRT SUE detected on buffer output</bit>
+ <bit pos="23">WRT detected a scom sequencer error</bit>
+ <bit pos="24">WRT detected a parity error on the misc_reg scom register</bit>
+ <bit pos="25">WRT Data Syndrome not equal to 0 for input for write buffer.</bit>
+ <bit pos="26">No buffer error; Buffer manager parity error.</bit>
+ <bit pos="27">A fail response set as checkstop occurred for chana</bit>
+ <bit pos="28">A fail response set as checkstop occurred for chanb</bit>
+ <bit pos="29">A fail response set as recoverable occurred for chana</bit>
+ <bit pos="30">A fail response set as recoverable occurred for chanb</bit>
+ <bit pos="31">A lol drop set as checkstop occurred for chana</bit>
+ <bit pos="32">A lol drop set as checkstop occurred for chanb</bit>
+ <bit pos="33">A lol drop set as recoverable occurred for chana</bit>
+ <bit pos="34">A lol drop set as recoverable occurred for chanb</bit>
+ <bit pos="35">flit data pariry error from dl for chana</bit>
+ <bit pos="36">flit data pariry error from dl for chanb</bit>
+ <bit pos="37">internal fifo parity error for chana</bit>
+ <bit pos="38">internal fifo parity error for chanb</bit>
+ <bit pos="39">Bad response detected from chana. See cerrrpts and USTLBADRESP reg for more info</bit>
+ <bit pos="40">Bad response detected from chanb. See cerrrpts and USTLBADRESP reg for more info</bit>
+ <bit pos="41">Bad data set for data that is not valid chana</bit>
+ <bit pos="42">Bad data set for data that is not valid chanb</bit>
+ <bit pos="43">Memory read data returned in template 0, chana</bit>
+ <bit pos="44">Memory read data returned in template 0, chanb</bit>
+ <bit pos="45">Recieved mmio response while in LOL mode chana</bit>
+ <bit pos="46">Recieved mmio response while in LOL mode chanb</bit>
+ <bit pos="47">valid bad data or SUE received channel a</bit>
+ <bit pos="48">Valid bad data or SUE received chanb</bit>
+ <bit pos="49">Data is valid in data buffers without a matching response, or more than 2 data flits with template 9</bit>
+ <bit pos="50">Data is valid in data buffers without a matching response,or more than 2 data flits with template 9</bit>
+ <bit pos="51">Commit state where commit data is not marked as valid</bit>
+ <bit pos="52">Commit state where commit data is not marked as valid</bit>
+ <bit pos="53">A fifo in the ustl chana overflowed</bit>
+ <bit pos="54">A fifo in the ustl chanb overflowed</bit>
+ <bit pos="55">Invalid command decoded in USTL FF subchannel A</bit>
+ <bit pos="56">Invalid command decoded in USTL FF subchannel B</bit>
+ <bit pos="57">Fatal register parity error</bit>
+ <bit pos="58">recov register parity error</bit>
+ <bit pos="59">A chana response with an invalid combination of dlength and/or dpart received</bit>
+ <bit pos="60">A chanb response with an invalid combination of dlength and/or dpart received</bit>
+ <bit pos="61">USTL spare FIR bits</bit>
+</attn_node>
diff --git a/xml/p10/node_mcd_fir.xml b/xml/p10/node_mcd_fir.xml
new file mode 100644
index 0000000..21e7678
--- /dev/null
+++ b/xml/p10/node_mcd_fir.xml
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="MCD_FIR" reg_type="SCOM">
+ <local_fir config="W" name="MCD_FIR">
+ <instance addr="0x03010800" reg_inst="0"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ <action attn_type="SPA" config="10"/>
+ </local_fir>
+ <bit pos="0">MCD array ECC uncorrectable error</bit>
+ <bit pos="1">MCD array ECC uncorrectable error</bit>
+ <bit pos="2">MCD PowerBus address Parity error</bit>
+ <bit pos="3">MCD invalid state error</bit>
+ <bit pos="4">Hang poll timer expired on cl_probe</bit>
+ <bit pos="5">PowerBus address error cresp received</bit>
+ <bit pos="6">MCD recieved a unsoliceted CRESP</bit>
+ <bit pos="7">MCD powerbus ttag parity error</bit>
+ <bit pos="8">MCD scom register update error</bit>
+ <bit pos="9">MCD recieved a ack_dead_cresp</bit>
+ <bit pos="10">MCD configuration register had a parity error</bit>
+</attn_node>
diff --git a/xml/p10/node_n0_local_fir.xml b/xml/p10/node_n0_local_fir.xml
new file mode 100644
index 0000000..ac7b953
--- /dev/null
+++ b/xml/p10/node_n0_local_fir.xml
@@ -0,0 +1,75 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="N0_LOCAL_FIR" reg_type="SCOM">
+ <local_fir config="W2" name="N0_LOCAL_FIR">
+ <instance addr="0x02040100" reg_inst="0"/>
+ <action attn_type="CS" config="000"/>
+ <action attn_type="RE" config="010"/>
+ <action attn_type="SPA" config="100"/>
+ <action attn_type="UCS" config="110"/>
+ <action attn_type="HA" config="001"/>
+ </local_fir>
+ <bit pos="0">CFIR - Parity or PCB access error</bit>
+ <bit pos="1">CPLT_CTRL - PCB access error</bit>
+ <bit pos="2">CC - PCB access error - read and clear nn03000F</bit>
+ <bit pos="3">CC - Clock Control Error - read and clear nn03000F</bit>
+ <bit pos="4">PSC - PSCOM access error - read and clear nn01001</bit>
+ <bit pos="5">PSC - internal or ring interface error - read and clear nn01001</bit>
+ <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050013</bit>
+ <bit pos="7">THERM - pcb error</bit>
+ <bit pos="8">THERMTRIP - Critical temperature indicator</bit>
+ <bit pos="9">THERMTRIP - Fatal temperature indicator</bit>
+ <bit pos="10">VOLTTRIP - Voltage sense error</bit>
+ <bit pos="11">DBG - scom parity fail</bit>
+ <bit pos="12">reserved</bit>
+ <bit pos="13">reserved</bit>
+ <bit pos="14">reserved</bit>
+ <bit pos="15">reserved</bit>
+ <bit pos="16">reserved</bit>
+ <bit pos="17">reserved</bit>
+ <bit pos="18">reserved</bit>
+ <bit pos="19">reserved</bit>
+ <bit pos="20">Trace00 - scom parity err</bit>
+ <bit pos="21">Trace01 - scom parity err - Unused in Axon,PCI</bit>
+ <bit pos="22">unused</bit>
+ <bit pos="23">unused</bit>
+ <bit pos="24">unused</bit>
+ <bit pos="25">unused</bit>
+ <bit pos="26">unused</bit>
+ <bit pos="27">unused</bit>
+ <bit pos="28">unused</bit>
+ <bit pos="29">unused</bit>
+ <bit pos="30">unused</bit>
+ <bit pos="31">unused</bit>
+ <bit pos="32">unused</bit>
+ <bit pos="33">unused</bit>
+ <bit pos="34">unused</bit>
+ <bit pos="35">unused</bit>
+ <bit pos="36">unused</bit>
+ <bit pos="37">unused</bit>
+ <bit pos="38">unused</bit>
+ <bit pos="39">unused</bit>
+ <bit pos="40">unused</bit>
+ <bit pos="41">unused</bit>
+ <bit pos="42">unused</bit>
+ <bit pos="43">unused</bit>
+ <bit pos="44">unused</bit>
+ <bit pos="45">unused</bit>
+ <bit pos="46">unused</bit>
+ <bit pos="47">unused</bit>
+ <bit pos="48">unused</bit>
+ <bit pos="49">unused</bit>
+ <bit pos="50">unused</bit>
+ <bit pos="51">unused</bit>
+ <bit pos="52">unused</bit>
+ <bit pos="53">unused</bit>
+ <bit pos="54">unused</bit>
+ <bit pos="55">unused</bit>
+ <bit pos="56">unused</bit>
+ <bit pos="57">unused</bit>
+ <bit pos="58">unused</bit>
+ <bit pos="59">unused</bit>
+ <bit pos="60">unused</bit>
+ <bit pos="61">unused</bit>
+ <bit pos="62">unused</bit>
+ <bit pos="63">ext_local_xstop</bit>
+</attn_node>
diff --git a/xml/p10/node_n1_local_fir.xml b/xml/p10/node_n1_local_fir.xml
new file mode 100644
index 0000000..850f8a4
--- /dev/null
+++ b/xml/p10/node_n1_local_fir.xml
@@ -0,0 +1,75 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="N1_LOCAL_FIR" reg_type="SCOM">
+ <local_fir config="W2" name="N1_LOCAL_FIR">
+ <instance addr="0x03040100" reg_inst="0"/>
+ <action attn_type="CS" config="000"/>
+ <action attn_type="RE" config="010"/>
+ <action attn_type="SPA" config="100"/>
+ <action attn_type="UCS" config="110"/>
+ <action attn_type="HA" config="001"/>
+ </local_fir>
+ <bit pos="0">CFIR - Parity or PCB access error</bit>
+ <bit pos="1">CPLT_CTRL - PCB access error</bit>
+ <bit pos="2">CC - PCB access error - read and clear nn03000F</bit>
+ <bit pos="3">CC - Clock Control Error - read and clear nn03000F</bit>
+ <bit pos="4">PSC - PSCOM access error - read and clear nn01001</bit>
+ <bit pos="5">PSC - internal or ring interface error - read and clear nn01001</bit>
+ <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050013</bit>
+ <bit pos="7">THERM - pcb error</bit>
+ <bit pos="8">THERMTRIP - Critical temperature indicator</bit>
+ <bit pos="9">THERMTRIP - Fatal temperature indicator</bit>
+ <bit pos="10">VOLTTRIP - Voltage sense error</bit>
+ <bit pos="11">DBG - scom parity fail</bit>
+ <bit pos="12">reserved</bit>
+ <bit pos="13">reserved</bit>
+ <bit pos="14">reserved</bit>
+ <bit pos="15">reserved</bit>
+ <bit pos="16">reserved</bit>
+ <bit pos="17">reserved</bit>
+ <bit pos="18">reserved</bit>
+ <bit pos="19">reserved</bit>
+ <bit pos="20">Trace00 - scom parity err</bit>
+ <bit pos="21">Trace01 - scom parity err - Unused in Axon,PCI</bit>
+ <bit pos="22">unused</bit>
+ <bit pos="23">unused</bit>
+ <bit pos="24">unused</bit>
+ <bit pos="25">unused</bit>
+ <bit pos="26">unused</bit>
+ <bit pos="27">unused</bit>
+ <bit pos="28">unused</bit>
+ <bit pos="29">unused</bit>
+ <bit pos="30">unused</bit>
+ <bit pos="31">unused</bit>
+ <bit pos="32">unused</bit>
+ <bit pos="33">unused</bit>
+ <bit pos="34">unused</bit>
+ <bit pos="35">unused</bit>
+ <bit pos="36">unused</bit>
+ <bit pos="37">unused</bit>
+ <bit pos="38">unused</bit>
+ <bit pos="39">unused</bit>
+ <bit pos="40">unused</bit>
+ <bit pos="41">unused</bit>
+ <bit pos="42">unused</bit>
+ <bit pos="43">unused</bit>
+ <bit pos="44">unused</bit>
+ <bit pos="45">unused</bit>
+ <bit pos="46">unused</bit>
+ <bit pos="47">unused</bit>
+ <bit pos="48">unused</bit>
+ <bit pos="49">unused</bit>
+ <bit pos="50">unused</bit>
+ <bit pos="51">unused</bit>
+ <bit pos="52">unused</bit>
+ <bit pos="53">unused</bit>
+ <bit pos="54">unused</bit>
+ <bit pos="55">unused</bit>
+ <bit pos="56">unused</bit>
+ <bit pos="57">unused</bit>
+ <bit pos="58">unused</bit>
+ <bit pos="59">unused</bit>
+ <bit pos="60">unused</bit>
+ <bit pos="61">unused</bit>
+ <bit pos="62">unused</bit>
+ <bit pos="63">ext_local_xstop</bit>
+</attn_node>
diff --git a/xml/p10/node_nmmu_cq_fir.xml b/xml/p10/node_nmmu_cq_fir.xml
new file mode 100644
index 0000000..8cca801
--- /dev/null
+++ b/xml/p10/node_nmmu_cq_fir.xml
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="NMMU_CQ_FIR" reg_type="SCOM">
+ <local_fir config="W" name="NMMU_CQ_FIR">
+ <instance addr="0x02010C00" reg_inst="0"/>
+ <instance addr="0x03010C00" reg_inst="1"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ <action attn_type="UCS" config="11"/>
+ </local_fir>
+ <bit pos="0">PBI internal parity error</bit>
+ <bit pos="1">PowerBus command hang error</bit>
+ <bit pos="2">PowerBus read address error</bit>
+ <bit pos="3">PowerBus write address error</bit>
+ <bit pos="4">PowerBus miscellaneous error</bit>
+ <bit pos="5">Reserved</bit>
+ <bit pos="6">PowerBus Xlate UE error</bit>
+ <bit pos="7">PowerBus Xlate SUE error</bit>
+ <bit pos="8">PowerBus CE error</bit>
+ <bit pos="9">PowerBus UE error</bit>
+ <bit pos="10">PowerBus SUE error</bit>
+ <bit pos="11">Inbound LCO_ARRAY CE error</bit>
+ <bit pos="12">Inbound LCO_ARRAY UE error</bit>
+ <bit pos="13">Inbound LCO_ARRAY SUE error</bit>
+ <bit pos="14">Inbound array CE error</bit>
+ <bit pos="15">Inbound array UE error</bit>
+ <bit pos="16">internal state error</bit>
+ <bit pos="17">ACK_DEAD cresp received by read command</bit>
+ <bit pos="18">ACK_DEAD cresp received by write command</bit>
+ <bit pos="19">Link check aborted while waiting on data</bit>
+</attn_node>
diff --git a/xml/p10/node_nmmu_fir.xml b/xml/p10/node_nmmu_fir.xml
new file mode 100644
index 0000000..de561b1
--- /dev/null
+++ b/xml/p10/node_nmmu_fir.xml
@@ -0,0 +1,56 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="NMMU_FIR" reg_type="SCOM">
+ <local_fir config="W" name="NMMU_FIR">
+ <instance addr="0x02010C40" reg_inst="0"/>
+ <instance addr="0x03010C40" reg_inst="1"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ <action attn_type="UCS" config="11"/>
+ </local_fir>
+ <bit pos="0">Fabric DIn xlat array CE error detected.</bit>
+ <bit pos="1">Fabric DIn xlat array UE error detected.</bit>
+ <bit pos="2">Fabric DIn xlat array SUE error detected.</bit>
+ <bit pos="3">Fabric mst rd array CE error detected.</bit>
+ <bit pos="4">Fabric mst rd array UE error detected.</bit>
+ <bit pos="5">Fabric mst rd array SUE error detected.</bit>
+ <bit pos="6">Fabric xlat protocol error detected.</bit>
+ <bit pos="7">Fabric xlat op timeout detected.</bit>
+ <bit pos="8">SLB directory parity error detected.</bit>
+ <bit pos="9">SLB cache parity error detected.</bit>
+ <bit pos="10">SLB lru parity error detected.</bit>
+ <bit pos="11">SLB multi-hit error detected.</bit>
+ <bit pos="12">TLB directory parity error detected.</bit>
+ <bit pos="13">TLB cache parity error detected.</bit>
+ <bit pos="14">TLB lru parity error detected.</bit>
+ <bit pos="15">TLB multi-hit error detected.</bit>
+ <bit pos="16">Segment fault detected .</bit>
+ <bit pos="17">Page fault detected due to no matching pte.</bit>
+ <bit pos="18">Page fault detected due to basic prot chk fail.</bit>
+ <bit pos="19">Page fault detected due to virt prot chk fail.</bit>
+ <bit pos="20">Page fault detected due to seid mismatch .</bit>
+ <bit pos="21">Address error cresp detected by twsm for read .</bit>
+ <bit pos="22">PTE update fail due to armwf mismatch.</bit>
+ <bit pos="23">Address error cresp detected by twsm for write.</bit>
+ <bit pos="24">Unsupported radix cfg for guest-side .</bit>
+ <bit pos="25">Unsupported radix cfg for host-side .</bit>
+ <bit pos="26">Invalid wimg setting detected .</bit>
+ <bit pos="27">Invalid radix quad access detected .</bit>
+ <bit pos="28">Unexpected access to foreign address space .</bit>
+ <bit pos="29">Prefetch abort/fail detected .</bit>
+ <bit pos="30">Context cache array parity error detected .</bit>
+ <bit pos="31">Radix pwc array parity error detected .</bit>
+ <bit pos="32">Tablewalk sm control error detected .</bit>
+ <bit pos="33">Castout sm control error detected .</bit>
+ <bit pos="34">Check-in sm control error detected .</bit>
+ <bit pos="35">Invalidate sm control error detected .</bit>
+ <bit pos="36">Tablewalk sm timeout error detected .</bit>
+ <bit pos="37">Castout sm timeout error detected .</bit>
+ <bit pos="38">Check-in sm timeout error detected .</bit>
+ <bit pos="39">Invalidate sm timeout error detected .</bit>
+ <bit pos="40">NX local checkstop error detected .</bit>
+ <bit pos="41">CP0 local checkstop error detected .</bit>
+ <bit pos="42">CP1 local checkstop error detected .</bit>
+ <bit pos="43">NPU local checkstop error detected .</bit>
+ <bit pos="44">FBC local checkstop error detected .</bit>
+ <bit pos="45">FBC local checkstop error detected .</bit>
+</attn_node>
diff --git a/xml/p10/node_nx_cq_fir.xml b/xml/p10/node_nx_cq_fir.xml
new file mode 100644
index 0000000..6f6ccca
--- /dev/null
+++ b/xml/p10/node_nx_cq_fir.xml
@@ -0,0 +1,51 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="NX_CQ_FIR" reg_type="SCOM">
+ <local_fir config="W" name="NX_CQ_FIR">
+ <instance addr="0x02011080" reg_inst="0"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ <action attn_type="UCS" config="11"/>
+ </local_fir>
+ <bit pos="0">PBI internal parity error</bit>
+ <bit pos="1">PowerBus CE error</bit>
+ <bit pos="2">PowerBus UE error</bit>
+ <bit pos="3">PowerBus SUE error</bit>
+ <bit pos="4">Inbound array CE error</bit>
+ <bit pos="5">Inbound array UE error</bit>
+ <bit pos="6">Paste request rejected</bit>
+ <bit pos="7">PowerBus command hang error</bit>
+ <bit pos="8">PowerBus read address error</bit>
+ <bit pos="9">PowerBus write address error</bit>
+ <bit pos="10">PowerBus miscellaneous error</bit>
+ <bit pos="11">MMIO BAR parity error</bit>
+ <bit pos="12">UMAC detected SUE on WC Interrupt</bit>
+ <bit pos="13">ACK_DEAD cresp received by read command</bit>
+ <bit pos="14">ACK_DEAD cresp received by write command</bit>
+ <bit pos="15">Reserved. Used to be PowerBus Link Abort in P9</bit>
+ <bit pos="16">Hang poll time expired on internal transfer</bit>
+ <bit pos="17">Parity error on ERAT arrays</bit>
+ <bit pos="18">Correctable error on ERAT arrays</bit>
+ <bit pos="19">Uncorrectable error on ERAT arrays</bit>
+ <bit pos="20">Special uncorrectable error on ERAT arrays</bit>
+ <bit pos="21">Hang on checkin/checkout request to NMMU</bit>
+ <bit pos="22">ERAT control logic error</bit>
+ <bit pos="23">Uncorrectable error on the Powerbus data for xlate</bit>
+ <bit pos="24">Special uncorrectable error on the Powerbus data for xlate</bit>
+ <bit pos="25">ACK_DEAD cresp received by UMAC read command</bit>
+ <bit pos="26">Link check aborted while waiting on UMAC data</bit>
+ <bit pos="27">Uncorrectable error on CRB QW0/4</bit>
+ <bit pos="28">Special uncorrectable error on CRB QW0/4</bit>
+ <bit pos="29">UMAC has detected a control logic error</bit>
+ <bit pos="30">Other SCOM satellite parity error</bit>
+ <bit pos="31">SCOM write to RNG when not allowed</bit>
+ <bit pos="32">A first noise source in the RNG has failed</bit>
+ <bit pos="33">A second noise source in the RNG has failed</bit>
+ <bit pos="34">RNG has detected a control logic error</bit>
+ <bit pos="35">NMMU has signaled local checkstop</bit>
+ <bit pos="36">VAS has signaled local checkstop</bit>
+ <bit pos="37">PBCQ has detected a control logic error</bit>
+ <bit pos="38">PBCQ has detected a failed link on an interrupt</bit>
+ <bit pos="39">UMAC has detected an SUE on interrupt address</bit>
+ <bit pos="40">SMF error</bit>
+ <bit pos="41">Topology index error detected in NX</bit>
+</attn_node>
diff --git a/xml/p10/node_nx_dma_eng_fir.xml b/xml/p10/node_nx_dma_eng_fir.xml
new file mode 100644
index 0000000..811c4d3
--- /dev/null
+++ b/xml/p10/node_nx_dma_eng_fir.xml
@@ -0,0 +1,57 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="NX_DMA_ENG_FIR" reg_type="SCOM">
+ <local_fir config="W" name="NX_DMA_ENG_FIR">
+ <instance addr="0x02011100" reg_inst="0"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ <action attn_type="UCS" config="11"/>
+ </local_fir>
+ <bit pos="0">DMA Hang Timer FIR bit</bit>
+ <bit pos="1">SHM invalid state error FIR bit</bit>
+ <bit pos="2">Reserved FIR bit 2</bit>
+ <bit pos="3">Reserved FIR bit 3</bit>
+ <bit pos="4">Channel 0 842 array corrected ECC error FIR bit</bit>
+ <bit pos="5">Channel 0 842 array uncorrectable ECC error FIR bit</bit>
+ <bit pos="6">Channel 1 842 array corrected ECC error FIR bit</bit>
+ <bit pos="7">Channel 1 842 array uncorrectable ECC error FIR bit</bit>
+ <bit pos="8">DMA non-zero CSB CC detected FIR bit. Lab use only. Masked.</bit>
+ <bit pos="9">DMA array correctable ECC error FIR bit</bit>
+ <bit pos="10">DMA outbound write/inbound read correctable ECC error FIR bit</bit>
+ <bit pos="11">Channel 4 Gzip array corrected ECC error FIR bit</bit>
+ <bit pos="12">Channel 4 Gzip array corrected ECC error FIR bit</bit>
+ <bit pos="13">Channel 4 Gzip array parity error FIR bit</bit>
+ <bit pos="14">Error from other SCOM satellites FIR bit</bit>
+ <bit pos="15">DMA invalid state error FIR bit</bit>
+ <bit pos="16">DMA invalid state error FIR bit. Unrecoverable despite name</bit>
+ <bit pos="17">DMA array uncorrectable ECC error FIR bit</bit>
+ <bit pos="18">DMA outbound write/inbound read uncorrectable ECC error FIR bit</bit>
+ <bit pos="19">DMA inbound read error FIR bit</bit>
+ <bit pos="20">Channel 0 842 invalid state error FIR bit</bit>
+ <bit pos="21">Channel 1 842 invalid state error FIR bit</bit>
+ <bit pos="22">Channel 2 SYM invalid state error FIR bit</bit>
+ <bit pos="23">Channel 3 SYMinvalid state error FIR bit</bit>
+ <bit pos="24">Channel 4 Gzip invalid state error FIR bit</bit>
+ <bit pos="25">Reserved FIR bit 25</bit>
+ <bit pos="26">Reserved FIR bit 26</bit>
+ <bit pos="27">Reserved FIR bit 27</bit>
+ <bit pos="28">Reserved FIR bit 28</bit>
+ <bit pos="29">Reserved FIR bit 29</bit>
+ <bit pos="30">Reserved FIR bit 30</bit>
+ <bit pos="31">UE error on CRB QW0 or QW4 FIR bit</bit>
+ <bit pos="32">SUE error on CRB QW0 or QW4 FIR bit</bit>
+ <bit pos="33">SUE error on something other than CRB QW0 or QW4 FIR bit</bit>
+ <bit pos="34">Channel 0 842 watchdog timer expired FIR bit</bit>
+ <bit pos="35">Channel 1 842 watchdog timer expired FIR bit</bit>
+ <bit pos="36">Channel 2 SYM watchdog timer expired FIR bit</bit>
+ <bit pos="37">Channel 3 SYM watchdog timer expired FIR bit</bit>
+ <bit pos="38">Reserved FIR bit 38. Hypervisor can use to signal local xstop to FSP.</bit>
+ <bit pos="39">Channel 4 Gzip watchdog timer expired FIR bit</bit>
+ <bit pos="40">Reserved FIR bit 40</bit>
+ <bit pos="41">Reserved FIR bit 41</bit>
+ <bit pos="42">Reserved FIR bit 42</bit>
+ <bit pos="43">Reserved FIR bit 43</bit>
+ <bit pos="44">Reserved FIR bit 44</bit>
+ <bit pos="45">Reserved FIR bit 45</bit>
+ <bit pos="46">Reserved FIR bit 46</bit>
+ <bit pos="47">Reserved FIR bit 47</bit>
+</attn_node>
diff --git a/xml/p10/node_occ_fir.xml b/xml/p10/node_occ_fir.xml
new file mode 100644
index 0000000..35f1bac
--- /dev/null
+++ b/xml/p10/node_occ_fir.xml
@@ -0,0 +1,70 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="OCC_FIR" reg_type="SCOM">
+ <local_fir config="" name="OCC_FIR">
+ <instance addr="0x01010800" reg_inst="0"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ </local_fir>
+ <bit pos="0">Input tied to 0. Used by OCC Firmware to produce an attention to the FSP.</bit>
+ <bit pos="1">Input tied to 0. Used by OCC Firmware to produce an attention tothe FSP.</bit>
+ <bit pos="2">Input tied to 0. Used by STOP GPE code to indicated to HYP that a QME has indicated a fault.</bit>
+ <bit pos="3">Input tied to 0. Written by stop recovery firmware to indicate that the host side actions are complete and that FFDC information is available for</bit>
+ <bit pos="4">OCC Heartbeat Error</bit>
+ <bit pos="5">GPE0 asserted a watchdog timeout condition</bit>
+ <bit pos="6">GPE1 asserted a watchdog timeout condition</bit>
+ <bit pos="7">GPE2 asserted a watchdog timeout condition</bit>
+ <bit pos="8">GPE3 asserted a watchdog timeout condition</bit>
+ <bit pos="9">GPE0 asserted an error condition that caused it to halt.</bit>
+ <bit pos="10">GPE1 asserted an error condition that caused it to halt.</bit>
+ <bit pos="11">GPE2 asserted an error condition that caused it to halt.</bit>
+ <bit pos="12">GPE3 asserted an error condition that caused it to halt.</bit>
+ <bit pos="13">OCB Error (recoverable error)</bit>
+ <bit pos="14">SRAM Uncorrectable Error (recoverable error)</bit>
+ <bit pos="15">SRAM Correctable Error (masked (product); recoverable error (mfg)</bit>
+ <bit pos="16">GPE0 asserted a halt condition</bit>
+ <bit pos="17">GPE1 asserted a halt condition</bit>
+ <bit pos="18">GPE2 asserted a halt condition</bit>
+ <bit pos="19">GPE3 asserted a halt condition</bit>
+ <bit pos="20">GPE0 attempted to write outside the region defined in GPESWPR</bit>
+ <bit pos="21">GPE1 attempted to write outside the region defined in GPESWPR</bit>
+ <bit pos="22">GPE2 attempted to write outside the region defined in GPESWPR</bit>
+ <bit pos="23">GPE3 attempted to write outside the region defined in GPESWPR</bit>
+ <bit pos="24">Implemented but not used, inputs tied to 0</bit>
+ <bit pos="25">Implemented but not used, inputs tied to 0</bit>
+ <bit pos="26">External Trigger pin active (recoverable (product)</bit>
+ <bit pos="27">PPC405 Core Reset Output asserted (??? firmware)</bit>
+ <bit pos="28">PPC405 Chip Reset Output asserted (??? firmware)</bit>
+ <bit pos="29">PPC405 System Reset Output asserted (??? firmware)</bit>
+ <bit pos="30">PPC405 Wait State asserted (??? firmware)</bit>
+ <bit pos="31">PPC405 Stop Ack output asserted (recoverable -> logging)</bit>
+ <bit pos="32">OCB Direct Bridge Error - See OCCERRRPT2[8:11] for error source</bit>
+ <bit pos="33">OCB PIB Address Parity Error - (PIB read or write operation). Note: may be set for either direct bridge or indirect channel operations.</bit>
+ <bit pos="34">Indirect Channel Error</bit>
+ <bit pos="35">Parity error detected on OPIT interrupt bus. Interrupts are hung.</bit>
+ <bit pos="36">OPIT interrupt state machine error occurred.</bit>
+ <bit pos="37">Implemented but not used. Input tied to 0</bit>
+ <bit pos="38">Implemented but not used. Input tied to 0</bit>
+ <bit pos="39">Implemented but not used. Input tied to 0</bit>
+ <bit pos="40">Implemented but not used. Input tied to 0</bit>
+ <bit pos="41">Implemented but not used. Input tied to 0</bit>
+ <bit pos="42">JTAG accelerator error</bit>
+ <bit pos="43">Any OCI Slave error occurreds</bit>
+ <bit pos="44">PPC405 cache UE</bit>
+ <bit pos="45">PPC405 cache CE</bit>
+ <bit pos="46">PPC405 Machine Check</bit>
+ <bit pos="47">SRAM spare direct error Summary. See OCCERRRPT2[0:3] for details</bit>
+ <bit pos="48">SRAM Controller Error - A read, write, or parity error occurred in the SRAM tank controller. See OCCERRRPT2[12:18] for more information</bit>
+ <bit pos="49">Implemented but notused. Input tied to 0</bit>
+ <bit pos="50">Implemented but notused. Input tied to 0</bit>
+ <bit pos="51">OCI slave error for GPE0 (see OCCERRPT for details)</bit>
+ <bit pos="52">OCI slave error for GPE1 (see OCCERRPT for details)</bit>
+ <bit pos="53">OCI slave error for GPE2 (see OCCERRPT for details)</bit>
+ <bit pos="54">OCI slave error for GPE3 (see OCCERRPT for details)</bit>
+ <bit pos="55">PPC405 ICU timeout on OCI request</bit>
+ <bit pos="56">PPC405 DCU timeout on OCI request</bit>
+ <bit pos="57">Used by OCC to indicate that a fault occurred (to achieve safe mode). Connected to OCCMISC[firmware_fault].</bit>
+ <bit pos="58">Used by OCC to notify another firmware entity that an event occurred. Connected to OCCMISC[firmware_notify].</bit>
+ <bit pos="59">Implemented but not used. Inputs tied to 0.</bit>
+ <bit pos="60">Implemented but not used. Inputs tied to 0.</bit>
+ <bit pos="61">Implemented but not used. Inputs tied to 0.</bit>
+</attn_node>
diff --git a/xml/p10/node_pau_dl_fir.xml b/xml/p10/node_pau_dl_fir.xml
new file mode 100644
index 0000000..7684976
--- /dev/null
+++ b/xml/p10/node_pau_dl_fir.xml
@@ -0,0 +1,39 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PAU_DL_FIR" reg_type="SCOM">
+ <local_fir config="W" name="PAU_DL_FIR">
+ <instance addr="0x10012C40" reg_inst="0"/>
+ <instance addr="0x11012C40" reg_inst="1"/>
+ <instance addr="0x12012C40" reg_inst="2"/>
+ <instance addr="0x13012C40" reg_inst="3"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ <action attn_type="SPA" config="10"/>
+ <action attn_type="UCS" config="11"/>
+ </local_fir>
+ <bit pos="0">FIR Register - A RX state machine parity or mode register parity error has occurred (IOO0).</bit>
+ <bit pos="1">FIR Register - A RX state machine parity or mode register parity error has occurred (IOO1).</bit>
+ <bit pos="2">FIR Register - A RX state machine parity or mode register parity error has occurred (OMI0).</bit>
+ <bit pos="3">FIR Register - A RX state machine parity or mode register parity error has occurred (OMI1).</bit>
+ <bit pos="4">FIR Register - A TX state machine parity or mode register parity error has occurred (IOO0).</bit>
+ <bit pos="5">FIR Register - A TX state machine parity or mode register parity error has occurred (IOO1).</bit>
+ <bit pos="6">FIR Register - A TX state machine parity or mode register parity error has occurred (OMI0).</bit>
+ <bit pos="7">FIR Register - A TX state machine parity or mode register parity error has occurred (OMI1).</bit>
+ <bit pos="8">FIR Register - A TX ZCAL state machine parity or mode register parity error has occurred.</bit>
+ <bit pos="9">FIR Register - A PPE internal error has occurred.</bit>
+ <bit pos="10">FIR Register - A PPE external error has occurred.</bit>
+ <bit pos="11">FIR Register - A PPE Halt due to Watchdog or Interrupt has occurred.</bit>
+ <bit pos="12">FIR Register - A PPE Halt due to Debug has occurred.</bit>
+ <bit pos="13">FIR Register - PPE Halted.</bit>
+ <bit pos="14">FIR Register - A PPE Watchdog Timeout has occurred.</bit>
+ <bit pos="15">FIR Register - A PPE Array Scrub was missed.</bit>
+ <bit pos="16">FIR Register - A PPE Array uncorrectable error has occurred.</bit>
+ <bit pos="17">FIR Register - A PPE Array correctable error has occurred.</bit>
+ <bit pos="18">FIR Register - A PPE Code Recal Abort has occurred.</bit>
+ <bit pos="19">FIR Register - A PPE Code Fatal Error has occurred.</bit>
+ <bit pos="20">FIR Register - A PPE Code Warning has occurred.</bit>
+ <bit pos="21">FIR Register - A PPE Code DFT Error has occurred.</bit>
+ <bit pos="22">FIR Register - A PPE Code Recal Not Run has occurred.</bit>
+ <bit pos="23">FIR Register - A PPE Code Thread Locked has occurred.</bit>
+ <bit pos="24">FIR Register - A PPE Code FIR 6 has occurred.</bit>
+ <bit pos="25">FIR Register - A PPE Code FIR 7 has occurred.</bit>
+</attn_node>
diff --git a/xml/p10/node_pau_fir_0.xml b/xml/p10/node_pau_fir_0.xml
new file mode 100644
index 0000000..01cdddf
--- /dev/null
+++ b/xml/p10/node_pau_fir_0.xml
@@ -0,0 +1,78 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PAU_FIR_0" reg_type="SCOM">
+ <local_fir config="" name="PAU_FIR_0">
+ <instance addr="0x10010C00" reg_inst="0"/>
+ <instance addr="0x11010C00" reg_inst="3"/>
+ <instance addr="0x12010C00" reg_inst="4"/>
+ <instance addr="0x12011400" reg_inst="5"/>
+ <instance addr="0x13010C00" reg_inst="6"/>
+ <instance addr="0x13011400" reg_inst="7"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ <action attn_type="UCS" config="11"/>
+ </local_fir>
+ <bit pos="0">NTL array CE</bit>
+ <bit pos="1">NTL header array UE</bit>
+ <bit pos="2">NTL data array UE</bit>
+ <bit pos="3">NTL NVLInk Control/Header/AE Parity error</bit>
+ <bit pos="4">NTL NVLink Data Parity error</bit>
+ <bit pos="5">NTL NVLink Malformed Packet (illegal Cmd encode, etc.)</bit>
+ <bit pos="6">NTL NVLink Unsupported Packet (receiving DGD, receiving Atomic with unsupported DatLen, etc)</bit>
+ <bit pos="7">NTL NVLink Config errors (Credits received > max configured)</bit>
+ <bit pos="8">NTL NVLink CRC errors or LMD=Stomp</bit>
+ <bit pos="9">NTL PRI errors (errors returned by NDL Wrapper on PRI interface)</bit>
+ <bit pos="10">NTL logic error (overflow, underflow, etc)</bit>
+ <bit pos="11">NTL LMD=Data Poison</bit>
+ <bit pos="12">NTL data array SUE</bit>
+ <bit pos="13">CQ CTL/SM ASBE Array single-bit correctable error</bit>
+ <bit pos="14">CQ CTL/SM PBR PowerBus Recoverable (ex: abort_trm CResp)</bit>
+ <bit pos="15">CQ CTL/SM REG Register ring error (ie noack)</bit>
+ <bit pos="16">CQ CTL/SM DUE Data Uncorrectable error for MMIO store data</bit>
+ <bit pos="17">CQ CTL/SM UT=1 to frozen PE (for naples this was in AT as part of the PCT lookup).</bit>
+ <bit pos="18">CQ CTL/SM NCF NVLink configuration error (ex: Probe missed its GPUBAR)</bit>
+ <bit pos="19">CQ CTL/SM NVF NVLink fatal (ex: rcv data resp to write req)</bit>
+ <bit pos="20">CQ CTL/SM OCR OpenCAPI Recoverable, Command failed (ex: SUE data to memory, a*_failed response to AFU, etc) and brick not fenced.</bit>
+ <bit pos="21">CQ CTL/SM AUE Array uncorrectable error</bit>
+ <bit pos="22">CQ CTL/SM PBP PowerBus parity error</bit>
+ <bit pos="23">CQ CTL/SM PBF PowerBus Fatal (ex: addr_error CResp)</bit>
+ <bit pos="24">CQ CTL/SM PBC PowerBus configuration error (ex: group > 3)</bit>
+ <bit pos="25">CQ CTL/SM FWD Forward-Progress (internal timer or rpt_hang.data)</bit>
+ <bit pos="26">CQ CTL/SM NLG PAU Logic error (ex: invalid state, missed table lookup, etc.)</bit>
+ <bit pos="27">Cresp=Addr_Error received for a load command (PowerBus LD_cresp_addr_error)</bit>
+ <bit pos="28">Cresp=Addr_Error received for a store command (PowerBus ST_cresp_addr_error)</bit>
+ <bit pos="29">CQ DAT ECC UE on data/BE arrays. Relevant word is marked with SUE</bit>
+ <bit pos="30">CQ DAT ECC CE on data/BE arrays</bit>
+ <bit pos="31">CQ DAT parity error on data/BE latches. Relevant word is marked with SUE</bit>
+ <bit pos="32">CQ DAT parity errors on configuration registers</bit>
+ <bit pos="33">CQ DAT parity errors on received PowerBus rtag</bit>
+ <bit pos="34">CQ DAT parity errors on internal state latches</bit>
+ <bit pos="35">CQ DAT logic error (invalid state bit patterns, credit overflow, etc.)</bit>
+ <bit pos="36">CQ_DAT ECC SUE on data/BE arrays that can be due to poisoned data from GPU</bit>
+ <bit pos="37">CQ_DAT ECC SUE on PB receive data (CANNOT be due to poisoned data from GPU)</bit>
+ <bit pos="38">CQ DAT Reserved, macro bit 9</bit>
+ <bit pos="39">CQ DAT Reserved, macro bit 10</bit>
+ <bit pos="40">XTS internal logic error</bit>
+ <bit pos="41">XTS correctable errors in XTS internal SRAM</bit>
+ <bit pos="42">XTS uncorrectable errors in XTS internal SRAM</bit>
+ <bit pos="43">XTS correctable error on incoming stack transactions</bit>
+ <bit pos="44">XTS uncorrectable/protocol errors on incoming stack transaction</bit>
+ <bit pos="45">XTS protocol errors on incoming PBUS transaction</bit>
+ <bit pos="46">XTS Translate Request Fail</bit>
+ <bit pos="47">XTS informational fir that is set when the snooper retries a rpt_hang.check or rpt_hang.poll command.</bit>
+ <bit pos="48">XTS Reserved, macro bit 8</bit>
+ <bit pos="49">XTS Reserved, macro bit 9</bit>
+ <bit pos="50">XTS Reserved, macro bit 10</bit>
+ <bit pos="51">XTS Reserved, macro bit 11</bit>
+ <bit pos="52">XTS Reserved, macro bit 12</bit>
+ <bit pos="53">XTS Reserved, macro bit 13</bit>
+ <bit pos="54">XTS Reserved, macro bit 14</bit>
+ <bit pos="55">XTS Reserved, macro bit 15</bit>
+ <bit pos="56">XTS Reserved, macro bit 16</bit>
+ <bit pos="57">XTS Reserved, macro bit 17</bit>
+ <bit pos="58">XTS Reserved, macro bit 18</bit>
+ <bit pos="59">AME Reserved, interrupt</bit>
+ <bit pos="60">AME data ECC UE</bit>
+ <bit pos="61">AME data SUE</bit>
+ <bit pos="62">Unused FIR</bit>
+ <bit pos="63">Unused FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_pau_fir_1.xml b/xml/p10/node_pau_fir_1.xml
new file mode 100644
index 0000000..cacea0e
--- /dev/null
+++ b/xml/p10/node_pau_fir_1.xml
@@ -0,0 +1,78 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PAU_FIR_1" reg_type="SCOM">
+ <local_fir config="" name="PAU_FIR_1">
+ <instance addr="0x10010C40" reg_inst="0"/>
+ <instance addr="0x11010C40" reg_inst="3"/>
+ <instance addr="0x12010C40" reg_inst="4"/>
+ <instance addr="0x12011440" reg_inst="5"/>
+ <instance addr="0x13010C40" reg_inst="6"/>
+ <instance addr="0x13011440" reg_inst="7"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ <action attn_type="UCS" config="11"/>
+ </local_fir>
+ <bit pos="0">NDL Brick0 stall</bit>
+ <bit pos="1">NDL Brick0 nostall</bit>
+ <bit pos="2">NDL Brick1 stall</bit>
+ <bit pos="3">NDL Brick1 nostall</bit>
+ <bit pos="4">NDL Brick2 stall</bit>
+ <bit pos="5">NDL Brick2 nostall</bit>
+ <bit pos="6">NDL Brick3 stall</bit>
+ <bit pos="7">NDL Brick3 nostall</bit>
+ <bit pos="8">NDL Brick4 stall</bit>
+ <bit pos="9">NDL Brick4 nostall</bit>
+ <bit pos="10">NDL Brick5 stall</bit>
+ <bit pos="11">NDL Brick5 nostall</bit>
+ <bit pos="12">MISC Register ring error (noack, >1 ack)</bit>
+ <bit pos="13">MISC Parity error from interrupt base real address register</bit>
+ <bit pos="14">MISC Parity error on Indirect SCOM Address register</bit>
+ <bit pos="15">MISC Parity error on MISC Control register</bit>
+ <bit pos="16">FIR1 Reserved, bit 16</bit>
+ <bit pos="17">ATS Invalid TVT entry (TCE Table Size = 0b00000)</bit>
+ <bit pos="18">ATS TVT Address range error (no xlate: EA out of range; xlate: unused EA bits non-zero, TVE uses > max # EA bits)</bit>
+ <bit pos="19">ATS TCE Page access error during TCE cache lookup</bit>
+ <bit pos="20">ATS Effective Address hit multiple TCE cache entries</bit>
+ <bit pos="21">ATS TCE Page access error during TCE table-walk</bit>
+ <bit pos="22">ATS Timeout on TCE tree walk</bit>
+ <bit pos="23">ATS Parity error on TCE cache directory array</bit>
+ <bit pos="24">ATS Parity error on TCE cache data array</bit>
+ <bit pos="25">ATS ECC UE on Effective Address array</bit>
+ <bit pos="26">ATS ECC CE on Effective Address array</bit>
+ <bit pos="27">ATS ECC UE on TDRmem array (table-walk state machine also hangs)</bit>
+ <bit pos="28">ATS ECC CE on TDRmem array</bit>
+ <bit pos="29">ATS ECC UE on CQ CTL DMA Read data to TDR_mem array during table-walk</bit>
+ <bit pos="30">ATS ECC CE on CQ CTL DMA Read data to TDR_mem array during table-walk</bit>
+ <bit pos="31">ATS Parity error on TVT entry</bit>
+ <bit pos="32">ATS Parity error on IODA Address Register</bit>
+ <bit pos="33">ATS Parity error on ATS Control Register</bit>
+ <bit pos="34">ATS Parity error on ATS Timeout Control register</bit>
+ <bit pos="35">ATS Invalid IODA Table Address Register Table Select entry</bit>
+ <bit pos="36">ATS Reserved, macro bit 19</bit>
+ <bit pos="37">kill xlate epoch timeout.</bit>
+ <bit pos="38">XSL Reserved, macro bit 19.</bit>
+ <bit pos="39">XSL Reserved, macro bit 20.</bit>
+ <bit pos="40">XSL Reserved, macro bit 21.</bit>
+ <bit pos="41">XSL Reserved, macro bit 22.</bit>
+ <bit pos="42">XSL Reserved, macro bit 23.</bit>
+ <bit pos="43">XSL Reserved, macro bit 24.</bit>
+ <bit pos="44">XSL Reserved, macro bit 25.</bit>
+ <bit pos="45">XSL Reserved, macro bit 26.</bit>
+ <bit pos="46">XSL Reserved, macro bit 27.</bit>
+ <bit pos="47">NDL Brick6 stall</bit>
+ <bit pos="48">NDL Brick6 nostall</bit>
+ <bit pos="49">NDL Brick7 stall</bit>
+ <bit pos="50">NDL Brick7 nostall</bit>
+ <bit pos="51">NDL Brick8 stall</bit>
+ <bit pos="52">NDL Brick8 nostall</bit>
+ <bit pos="53">NDL Brick9 stall</bit>
+ <bit pos="54">NDL Brick9 nostall</bit>
+ <bit pos="55">NDL Brick10 stall</bit>
+ <bit pos="56">NDL Brick10 nostall</bit>
+ <bit pos="57">NDL Brick11 stall</bit>
+ <bit pos="58">NDL Brick11 nostall</bit>
+ <bit pos="59">AME ECC CE</bit>
+ <bit pos="60">MISC Pervasive SCOM satellite signaled internal FSM error (ring 0, sat 0)</bit>
+ <bit pos="61">MISC Pervasive SCOM satellite signaled internal FSM error (ring 0, sat 1)</bit>
+ <bit pos="62">Unused FIR</bit>
+ <bit pos="63">Unused FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_pau_fir_2.xml b/xml/p10/node_pau_fir_2.xml
new file mode 100644
index 0000000..94c1492
--- /dev/null
+++ b/xml/p10/node_pau_fir_2.xml
@@ -0,0 +1,78 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PAU_FIR_2" reg_type="SCOM">
+ <local_fir config="" name="PAU_FIR_2">
+ <instance addr="0x10010C80" reg_inst="0"/>
+ <instance addr="0x11010C80" reg_inst="3"/>
+ <instance addr="0x12010C80" reg_inst="4"/>
+ <instance addr="0x12011480" reg_inst="5"/>
+ <instance addr="0x13010C80" reg_inst="6"/>
+ <instance addr="0x13011480" reg_inst="7"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ <action attn_type="UCS" config="11"/>
+ </local_fir>
+ <bit pos="0">OTL Brick2 translation fault</bit>
+ <bit pos="1">OTL Brick3 translation fault</bit>
+ <bit pos="2">OTL Brick4 translation fault</bit>
+ <bit pos="3">OTL Brick5 translation fault</bit>
+ <bit pos="4">OTL TL credit counter overflow caused by return_tl_credits.</bit>
+ <bit pos="5">OTL RX acTag specified in a command is outside the configured specification set.</bit>
+ <bit pos="6">OTL RX acTag specified in the command points to an invalid entry.</bit>
+ <bit pos="7">OTL RX reserved opcode used.</bit>
+ <bit pos="8">OTL RX return_tl_credit command found outside slot0.</bit>
+ <bit pos="9">OTL RX bad opcode and template combination.</bit>
+ <bit pos="10">OTL RX unsupported template format.</bit>
+ <bit pos="11">OTL RX bad template x00 format.</bit>
+ <bit pos="12">OTL RX control flit overrun.</bit>
+ <bit pos="13">OTL RX unexpected data flit.</bit>
+ <bit pos="14">OTL RX DL link down.</bit>
+ <bit pos="15">OTL RX bad data received on command.</bit>
+ <bit pos="16">OTL RX bad data received on response.</bit>
+ <bit pos="17">OTL RX AP response not allowed (CAPPTag not recognized).</bit>
+ <bit pos="18">OR of all OTL parity errors.</bit>
+ <bit pos="19">OR of all OTL ECC CE errors.</bit>
+ <bit pos="20">OR of all OTL ECC UE errors.</bit>
+ <bit pos="21">RXO OP Errors.</bit>
+ <bit pos="22">RXO Internal Errors.</bit>
+ <bit pos="23">OTL RXI fifo overrun.</bit>
+ <bit pos="24">OTL RXI control flit data run length invalid.</bit>
+ <bit pos="25">OTL RXI opcode utilizing dLength specifies dL=0b00.</bit>
+ <bit pos="26">OTL RXI bad data received vc2.</bit>
+ <bit pos="27">OTL RXI dcp2 fifo overrun.</bit>
+ <bit pos="28">OTL RXI vc1 fifo overrun.</bit>
+ <bit pos="29">OTL RXI vc2 fifo overrun.</bit>
+ <bit pos="30">Opcode data length not supported.</bit>
+ <bit pos="31">OTL TXI opcode error.</bit>
+ <bit pos="32">malformed packet error type 4 (rxi_misc_error_fieldrsvdne0_tlvc2).</bit>
+ <bit pos="33">OTL Happi no bar match</bit>
+ <bit pos="34">OTL Reserved, macro bit 30.</bit>
+ <bit pos="35">OTL Reserved, macro bit 31.</bit>
+ <bit pos="36">MMIO invalidate requested while one is in progress.</bit>
+ <bit pos="37">Unexpected ITAG returned on itag completion port 0.</bit>
+ <bit pos="38">Unexpected ITAG returned on itag completion port 1.</bit>
+ <bit pos="39">Unexpected Read PEE completion.</bit>
+ <bit pos="40">Unexpected Checkout response.</bit>
+ <bit pos="41">Translation request while SPAP is invalid.</bit>
+ <bit pos="42">Read a PEE which was not valid.</bit>
+ <bit pos="43">Bloom filter protection error.</bit>
+ <bit pos="44">Translation request to non-valid TA.</bit>
+ <bit pos="45">TA Translation request to an invalid TA.</bit>
+ <bit pos="46">correctable array error (SBE).</bit>
+ <bit pos="47">uncorrectable array error (UE or parity).</bit>
+ <bit pos="48">S/TLBI buffer overflow.</bit>
+ <bit pos="49">SBE correctable error on Powerbus checkout response data or Powerbus PEE read data.</bit>
+ <bit pos="50">UE uncorrectable error on Powerbus checkout response data or Powerbus PEE read data.</bit>
+ <bit pos="51">SUE error on Powerbus checkout response data or Powerbus PEE read data.</bit>
+ <bit pos="52">PA mem_hit when bar mode is nonzero .</bit>
+ <bit pos="53">XSL Reserved, macro bit 17.</bit>
+ <bit pos="54">OTL Brick0 translation fault</bit>
+ <bit pos="55">OTL Brick1 translation fault</bit>
+ <bit pos="56">AME ECC UE on control information or state bit errors that are contained within AME and ATL</bit>
+ <bit pos="57">AME ECC UE on control information or state bit errors that can affect correctness of external logic such as XSL castout</bit>
+ <bit pos="58">AME Logic errors that are contained within AME and ATL</bit>
+ <bit pos="59">AME Logic errors that can affect correctness of external logic such as XSL castout</bit>
+ <bit pos="60">AME firmware-detected fatal error conditions</bit>
+ <bit pos="61">AME Reserved</bit>
+ <bit pos="62">Unused FIR</bit>
+ <bit pos="63">Unused FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_pau_local_fir.xml b/xml/p10/node_pau_local_fir.xml
new file mode 100644
index 0000000..9156e0a
--- /dev/null
+++ b/xml/p10/node_pau_local_fir.xml
@@ -0,0 +1,78 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PAU_LOCAL_FIR" reg_type="SCOM">
+ <local_fir config="W2" name="PAU_LOCAL_FIR">
+ <instance addr="0x10040100" reg_inst="0"/>
+ <instance addr="0x11040100" reg_inst="1"/>
+ <instance addr="0x12040100" reg_inst="2"/>
+ <instance addr="0x13040100" reg_inst="3"/>
+ <action attn_type="CS" config="000"/>
+ <action attn_type="RE" config="010"/>
+ <action attn_type="SPA" config="100"/>
+ <action attn_type="UCS" config="110"/>
+ <action attn_type="HA" config="001"/>
+ </local_fir>
+ <bit pos="0">CFIR - Parity or PCB access error</bit>
+ <bit pos="1">CPLT_CTRL - PCB access error</bit>
+ <bit pos="2">CC - PCB access error - read and clear nn03000F</bit>
+ <bit pos="3">CC - Clock Control Error - read and clear nn03000F</bit>
+ <bit pos="4">PSC - PSCOM access error - read and clear nn01001</bit>
+ <bit pos="5">PSC - internal or ring interface error - read and clear nn01001</bit>
+ <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050013</bit>
+ <bit pos="7">THERM - pcb error</bit>
+ <bit pos="8">THERMTRIP - Critical temperature indicator</bit>
+ <bit pos="9">THERMTRIP - Fatal temperature indicator</bit>
+ <bit pos="10">VOLTTRIP - Voltage sense error</bit>
+ <bit pos="11">DBG - scom parity fail</bit>
+ <bit pos="12">reserved</bit>
+ <bit pos="13">reserved</bit>
+ <bit pos="14">reserved</bit>
+ <bit pos="15">reserved</bit>
+ <bit pos="16">reserved</bit>
+ <bit pos="17">reserved</bit>
+ <bit pos="18">reserved</bit>
+ <bit pos="19">reserved</bit>
+ <bit pos="20">Trace00 - scom parity err</bit>
+ <bit pos="21">Trace01 - scom parity err - Unused in Axon,PCI</bit>
+ <bit pos="22">unused</bit>
+ <bit pos="23">unused</bit>
+ <bit pos="24">unused</bit>
+ <bit pos="25">unused</bit>
+ <bit pos="26">unused</bit>
+ <bit pos="27">unused</bit>
+ <bit pos="28">unused</bit>
+ <bit pos="29">unused</bit>
+ <bit pos="30">unused</bit>
+ <bit pos="31">unused</bit>
+ <bit pos="32">unused</bit>
+ <bit pos="33">unused</bit>
+ <bit pos="34">unused</bit>
+ <bit pos="35">unused</bit>
+ <bit pos="36">unused</bit>
+ <bit pos="37">unused</bit>
+ <bit pos="38">unused</bit>
+ <bit pos="39">unused</bit>
+ <bit pos="40">unused</bit>
+ <bit pos="41">unused</bit>
+ <bit pos="42">unused</bit>
+ <bit pos="43">unused</bit>
+ <bit pos="44">unused</bit>
+ <bit pos="45">unused</bit>
+ <bit pos="46">unused</bit>
+ <bit pos="47">unused</bit>
+ <bit pos="48">unused</bit>
+ <bit pos="49">unused</bit>
+ <bit pos="50">unused</bit>
+ <bit pos="51">unused</bit>
+ <bit pos="52">unused</bit>
+ <bit pos="53">unused</bit>
+ <bit pos="54">unused</bit>
+ <bit pos="55">unused</bit>
+ <bit pos="56">unused</bit>
+ <bit pos="57">unused</bit>
+ <bit pos="58">unused</bit>
+ <bit pos="59">unused</bit>
+ <bit pos="60">unused</bit>
+ <bit pos="61">unused</bit>
+ <bit pos="62">unused</bit>
+ <bit pos="63">ext_local_xstop</bit>
+</attn_node>
diff --git a/xml/p10/node_pau_phy_fir.xml b/xml/p10/node_pau_phy_fir.xml
new file mode 100644
index 0000000..7993d08
--- /dev/null
+++ b/xml/p10/node_pau_phy_fir.xml
@@ -0,0 +1,39 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PAU_PHY_FIR" reg_type="SCOM">
+ <local_fir config="W" name="PAU_PHY_FIR">
+ <instance addr="0x10012C00" reg_inst="0"/>
+ <instance addr="0x11012C00" reg_inst="1"/>
+ <instance addr="0x12012C00" reg_inst="2"/>
+ <instance addr="0x13012C00" reg_inst="3"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ <action attn_type="SPA" config="10"/>
+ <action attn_type="UCS" config="11"/>
+ </local_fir>
+ <bit pos="0">FIR Register - A RX state machine parity or mode register parity error has occurred (IOO0).</bit>
+ <bit pos="1">FIR Register - A RX state machine parity or mode register parity error has occurred (IOO1).</bit>
+ <bit pos="2">FIR Register - A RX state machine parity or mode register parity error has occurred (OMI0).</bit>
+ <bit pos="3">FIR Register - A RX state machine parity or mode register parity error has occurred (OMI1).</bit>
+ <bit pos="4">FIR Register - A TX state machine parity or mode register parity error has occurred (IOO0).</bit>
+ <bit pos="5">FIR Register - A TX state machine parity or mode register parity error has occurred (IOO1).</bit>
+ <bit pos="6">FIR Register - A TX state machine parity or mode register parity error has occurred (OMI0).</bit>
+ <bit pos="7">FIR Register - A TX state machine parity or mode register parity error has occurred (OMI1).</bit>
+ <bit pos="8">FIR Register - A TX ZCAL state machine parity or mode register parity error has occurred.</bit>
+ <bit pos="9">FIR Register - A PPE internal error has occurred.</bit>
+ <bit pos="10">FIR Register - A PPE external error has occurred.</bit>
+ <bit pos="11">FIR Register - A PPE Halt due to Watchdog or Interrupt has occurred.</bit>
+ <bit pos="12">FIR Register - A PPE Halt due to Debug has occurred.</bit>
+ <bit pos="13">FIR Register - PPE Halted.</bit>
+ <bit pos="14">FIR Register - A PPE Watchdog Timeout has occurred.</bit>
+ <bit pos="15">FIR Register - A PPE Array Scrub was missed.</bit>
+ <bit pos="16">FIR Register - A PPE Array uncorrectable error has occurred.</bit>
+ <bit pos="17">FIR Register - A PPE Array correctable error has occurred.</bit>
+ <bit pos="18">FIR Register - A PPE Code Recal Abort has occurred.</bit>
+ <bit pos="19">FIR Register - A PPE Code Fatal Error has occurred.</bit>
+ <bit pos="20">FIR Register - A PPE Code Warning has occurred.</bit>
+ <bit pos="21">FIR Register - A PPE Code DFT Error has occurred.</bit>
+ <bit pos="22">FIR Register - A PPE Code Recal Not Run has occurred.</bit>
+ <bit pos="23">FIR Register - A PPE Code Thread Locked has occurred.</bit>
+ <bit pos="24">FIR Register - A PPE Code FIR 6 has occurred.</bit>
+ <bit pos="25">FIR Register - A PPE Code FIR 7 has occurred.</bit>
+</attn_node>
diff --git a/xml/p10/node_pau_ptl_fir.xml b/xml/p10/node_pau_ptl_fir.xml
new file mode 100644
index 0000000..6c89c18
--- /dev/null
+++ b/xml/p10/node_pau_ptl_fir.xml
@@ -0,0 +1,52 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PAU_PTL_FIR" reg_type="SCOM">
+ <local_fir config="W" name="PAU_PTL_FIR">
+ <instance addr="0x10011800" reg_inst="0"/>
+ <instance addr="0x11011800" reg_inst="1"/>
+ <instance addr="0x12011800" reg_inst="2"/>
+ <instance addr="0x13011800" reg_inst="3"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ <action attn_type="SPA" config="10"/>
+ </local_fir>
+ <bit pos="0">fmr00 trained. Even PTL, even half.</bit>
+ <bit pos="1">fmr01 trained. Even PTL, odd half.</bit>
+ <bit pos="2">fmr02 trained. Odd PTL, even half.</bit>
+ <bit pos="3">fmr03 trained. Odd PTL, odd half.</bit>
+ <bit pos="4">dob01 ue</bit>
+ <bit pos="5">dob01 ce</bit>
+ <bit pos="6">dob01 sue</bit>
+ <bit pos="7">data outbound switch internal error - even PTL.</bit>
+ <bit pos="8">dob23 ue</bit>
+ <bit pos="9">dob23 ce</bit>
+ <bit pos="10">dob23 sue</bit>
+ <bit pos="11">data outbound switch internal error - odd PTL.</bit>
+ <bit pos="12">Even PTL, even framer internal error</bit>
+ <bit pos="13">Even PTL, outbound switch cmd/presp/cresp internal error</bit>
+ <bit pos="14">Even PTL, odd framer internal error</bit>
+ <bit pos="15">Odd PTL, even framer internal error</bit>
+ <bit pos="16">Odd PTL, outbound switch cmd/presp/cresp internal error</bit>
+ <bit pos="17">Odd PTL, odd framer internal error</bit>
+ <bit pos="18">Even PTL, even parser internal error</bit>
+ <bit pos="19">Even PTL, odd parser internal error</bit>
+ <bit pos="20">Odd PTL, even parser internal error</bit>
+ <bit pos="21">Odd PTL, odd parser internal error</bit>
+ <bit pos="22">Even PTL, even link down</bit>
+ <bit pos="23">Even PTL, odd link down</bit>
+ <bit pos="24">Odd PTL, even link down</bit>
+ <bit pos="25">Odd PTL, odd link down</bit>
+ <bit pos="26">Even PTL data inbound switch internal error</bit>
+ <bit pos="27">Odd PTL data inbound switch internal error</bit>
+ <bit pos="28">mailbox 00 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_00_REG.</bit>
+ <bit pos="29">mailbox 01 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_01_REG.</bit>
+ <bit pos="30">mailbox 10 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_10_REG.</bit>
+ <bit pos="31">mailbox 11 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_11_REG.</bit>
+ <bit pos="32">mailbox 20 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_20_REG.</bit>
+ <bit pos="33">mailbox 21 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_21_REG.</bit>
+ <bit pos="34">mailbox 30 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_30_REG.</bit>
+ <bit pos="35">mailbox 31 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_31_REG.</bit>
+ <bit pos="36">ptl0 spare</bit>
+ <bit pos="37">ptl1 spare</bit>
+ <bit pos="38">ptl2 spare</bit>
+ <bit pos="39">ptl3 spare</bit>
+</attn_node>
diff --git a/xml/p10/node_pb_ext_fir.xml b/xml/p10/node_pb_ext_fir.xml
new file mode 100644
index 0000000..cfc1b5e
--- /dev/null
+++ b/xml/p10/node_pb_ext_fir.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PB_EXT_FIR" reg_type="SCOM">
+ <local_fir config="" name="PB_EXT_FIR">
+ <instance addr="0x030113AE" reg_inst="0"/>
+ <action attn_type="CS" config="00"/>
+ </local_fir>
+ <bit pos="0">pb_x0_fir_err</bit>
+ <bit pos="1">pb_x1_fir_err</bit>
+ <bit pos="2">pb_x2_fir_err</bit>
+ <bit pos="3">pb_x3_fir_err</bit>
+ <bit pos="4">pb_x4_fir_err</bit>
+ <bit pos="5">pb_x5_fir_err</bit>
+ <bit pos="6">pb_x6_fir_err</bit>
+ <bit pos="7">pb_x7_fir_err</bit>
+</attn_node>
diff --git a/xml/p10/node_pb_station_fir.xml b/xml/p10/node_pb_station_fir.xml
new file mode 100644
index 0000000..5ec21f1
--- /dev/null
+++ b/xml/p10/node_pb_station_fir.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PB_STATION_FIR" reg_type="SCOM">
+ <local_fir config="" name="PB_STATION_FIR">
+ <instance addr="0x03011200" reg_inst="0"/>
+ <instance addr="0x03011240" reg_inst="1"/>
+ <instance addr="0x03011280" reg_inst="2"/>
+ <instance addr="0x030112C0" reg_inst="3"/>
+ <instance addr="0x03011000" reg_inst="4"/>
+ <instance addr="0x03011040" reg_inst="5"/>
+ <instance addr="0x03011080" reg_inst="6"/>
+ <instance addr="0x030110C0" reg_inst="7"/>
+ <instance addr="0x03011100" reg_inst="8"/>
+ <instance addr="0x03011140" reg_inst="9"/>
+ <instance addr="0x03011180" reg_inst="10"/>
+ <instance addr="0x030111C0" reg_inst="11"/>
+ <instance addr="0x03011300" reg_inst="12"/>
+ <instance addr="0x03011340" reg_inst="13"/>
+ <instance addr="0x03011380" reg_inst="14"/>
+ <instance addr="0x030113C0" reg_inst="15"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ <action attn_type="SPA" config="10"/>
+ </local_fir>
+ <bit pos="0">protocol_error</bit>
+ <bit pos="1">overflow_error</bit>
+ <bit pos="2">hw_parity_error</bit>
+ <bit pos="3">fir_spare_3</bit>
+ <bit pos="4">coherency_error</bit>
+ <bit pos="5">cresp_addr_error</bit>
+ <bit pos="6">cresp_error</bit>
+ <bit pos="7">hang_recovery_limit_error</bit>
+ <bit pos="8">fir_spare_8</bit>
+ <bit pos="9">hang_recovery_gte_level1</bit>
+ <bit pos="10">force_mp_ipl</bit>
+ <bit pos="11">pb_cmd_snooper_error</bit>
+ <bit pos="12">data_overflow_error</bit>
+ <bit pos="13">data_protocol_error</bit>
+ <bit pos="14">data_route_error</bit>
+ <bit pos="15">fir_compab_trigger</bit>
+ <bit pos="16">link0_protocol_error</bit>
+ <bit pos="17">link0_overflow_error</bit>
+ <bit pos="18">link0_hw_parity_error</bit>
+ <bit pos="19">link1_protocol_error</bit>
+ <bit pos="20">link1_overflow_error</bit>
+ <bit pos="21">link1_hw_parity_error</bit>
+</attn_node>
diff --git a/xml/p10/node_pbaf_fir.xml b/xml/p10/node_pbaf_fir.xml
new file mode 100644
index 0000000..0eb283d
--- /dev/null
+++ b/xml/p10/node_pbaf_fir.xml
@@ -0,0 +1,48 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PBAF_FIR" reg_type="SCOM">
+ <local_fir config="" name="PBAF_FIR">
+ <instance addr="0x03011DC0" reg_inst="0"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ </local_fir>
+ <bit pos="0">PB CRESP Addr Error Received for Forwarded Read Request.</bit>
+ <bit pos="1">PB Read Data Timeout for Forwarded Request</bit>
+ <bit pos="2">PB Read Data SUE Error for Forwarded Request</bit>
+ <bit pos="3">PB Read Data UE Error for Forwarded Request</bit>
+ <bit pos="4">PB Read Data CE Error for Forwarded Request</bit>
+ <bit pos="5">PB Unexpected CRESP</bit>
+ <bit pos="6">PB Unexpected Data</bit>
+ <bit pos="7">PB Tag parity Error Detected</bit>
+ <bit pos="8">PB CRESP Addr Error Received for Forwarded Write Request</bit>
+ <bit pos="9">PB Invalid CRESP</bit>
+ <bit pos="10">PB CRESP ACK Dead response received for Forwarded Read request to a foreign link. The Buffer allocated for this request will continue unless</bit>
+ <bit pos="11">PB OPERATIONAL Timeout detected when PBACFG[EXIT_ON_HANG]=1. The powerbus request is terminated so the OCI request can complete.</bit>
+ <bit pos="12">BCUE PowerBus Link Dead</bit>
+ <bit pos="13">PB CRESP Addr Error Received for BCUE Write Request</bit>
+ <bit pos="14">BCDE PowerBus Link Dead</bit>
+ <bit pos="15">PB CRESP Addr Error Received for BCDE Read Request</bit>
+ <bit pos="16">PB Read Data Timeout for BCDE Request</bit>
+ <bit pos="17">PB Read Data SUE Error for BCDE Request</bit>
+ <bit pos="18">PB Read Data UE Error for BCDE Request</bit>
+ <bit pos="19">PB Read Data CE Error for BCDE Request</bit>
+ <bit pos="20">Internal Logic Error. See PBAERRRPT2 for more detailed information.</bit>
+ <bit pos="21">Byte count is less than full cache line: Write operation did not start gathering on a cache line boundary OR the write address was not contiguous</bit>
+ <bit pos="22">PBAXRCV Low data before High Data. See PBAXRCVSTAT[rcv_capture] for more information.</bit>
+ <bit pos="23">PBAXRCV Low data timeout. See PBAXRCVSTAT[rcv_capture] for more information.</bit>
+ <bit pos="24">PBAXRCV Reservation data timeout. Reservation acquired but phase1 data never seen. This could happen if PBAXSND is unable to get access to the</bit>
+ <bit pos="25">Illegal PBAX Flow. See PBAERRRPT2 for more info</bit>
+ <bit pos="26">PBAXSND engine retry threshold reached sending Phase 1</bit>
+ <bit pos="27">PBAXSND engine retry threshold reached sending Phase 2</bit>
+ <bit pos="28">PBAXSND Reservation Timeout</bit>
+ <bit pos="29">PB CRESP ACK Dead response received for Forwarded Write request to a foreign link. The Buffer allocated for this request will continue unless</bit>
+ <bit pos="30">PBAXIRCV Low data before High Data. See PBAXIRCVSTAT[rcv_capture] for more information.</bit>
+ <bit pos="31">PBAXIRCV Low data timeout. See PBAXIRCVSTAT[rcv_capture] for more information.</bit>
+ <bit pos="32">PBAXIRCV Reservation data timeout. Reservation acquired but phase1 data never seen. This could happen if PBAXISND is unable to get access to the</bit>
+ <bit pos="33">Illegal PBAX Flow. See PBAERRRPT2 for more info.</bit>
+ <bit pos="34">PBAXISND engine retry threshold reached sending Phase 1</bit>
+ <bit pos="35">PBAXISND engine retry threshold reached sending Phase 2</bit>
+ <bit pos="36">PBAXISND Reservation Timeout</bit>
+ <bit pos="37">Spare</bit>
+ <bit pos="38">Spare</bit>
+ <bit pos="39">Spare</bit>
+</attn_node>
diff --git a/xml/p10/node_pbao_fir.xml b/xml/p10/node_pbao_fir.xml
new file mode 100644
index 0000000..6e2318f
--- /dev/null
+++ b/xml/p10/node_pbao_fir.xml
@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PBAO_FIR" reg_type="SCOM">
+ <local_fir config="" name="PBAO_FIR">
+ <instance addr="0x01010CC0" reg_inst="0"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ </local_fir>
+ <bit pos="0">OCI Address Parity Error Det</bit>
+ <bit pos="1">PBA OCI Slave Initialization Error</bit>
+ <bit pos="2">OCI Write Data Parity Error Detected</bit>
+ <bit pos="3">Spare -was OCI Re-Request Timeout</bit>
+ <bit pos="4">BCUE Setup Error</bit>
+ <bit pos="5">BCUE Read Data Parity Error OR MRDERR Asserted</bit>
+ <bit pos="6">BCDE Setup Error</bit>
+ <bit pos="7">BCDE Write Data error indicated by OCI Slave</bit>
+ <bit pos="8">Internal Logic Error. See PBAERRRPT2 for more detailed information.</bit>
+ <bit pos="9">Illegal access to OCI Register. Invalid address, read to write-only, write to read-only.</bit>
+ <bit pos="10">Push Write Error. Push queue did not get OCI ADDRACK for push write request. Either the address is invalid or the targeted detected and address</bit>
+ <bit pos="11">Push Write Error. Push queue did not get OCI ADDRACK for push write request. Either the address is invalid or the targeted detected and address</bit>
+ <bit pos="12">Illegal PBAX Flow. See PBAERRRPT2 for more info.</bit>
+ <bit pos="13">Illegal PBAX Flow. See PBAERRRPT2 for more info.</bit>
+ <bit pos="14">PBAXSND Reservation Error. Reservation request and Reservations not enabled, push queue not enabled, or push queue is full.</bit>
+ <bit pos="15">PBAXISND Reservation Error. Reservation request and Reservations not enabled, push queue not enabled, or push queue is full.</bit>
+ <bit pos="16">The htm fifo interface was not able to keep up with the frequency variation between PBAO and PBAF and has overflowed and lost htm trace records.</bit>
+ <bit pos="17">The PBA has been configured to use the PowerBus Topology Translate tables, and the request did not hit a valid entry.</bit>
+ <bit pos="18">Spare</bit>
+ <bit pos="19">Spare</bit>
+</attn_node>
diff --git a/xml/p10/node_pci_etu_fir.xml b/xml/p10/node_pci_etu_fir.xml
new file mode 100644
index 0000000..65d43c4
--- /dev/null
+++ b/xml/p10/node_pci_etu_fir.xml
@@ -0,0 +1,77 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PCI_ETU_FIR" reg_type="SCOM">
+ <local_fir config="W" name="PCI_ETU_FIR">
+ <instance addr="0x08010908" reg_inst="0"/>
+ <instance addr="0x08010948" reg_inst="1"/>
+ <instance addr="0x08010988" reg_inst="2"/>
+ <instance addr="0x09010908" reg_inst="3"/>
+ <instance addr="0x09010948" reg_inst="4"/>
+ <instance addr="0x09010988" reg_inst="5"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ </local_fir>
+ <bit pos="0">See Outbound Error Status Register, bit 0 for details.</bit>
+ <bit pos="1">See Outbound Error Status Register, bit 1/2 for details.</bit>
+ <bit pos="2">See Outbound Error Status Register, bit 3/8 for details.</bit>
+ <bit pos="3">See Outbound Error Status Register, bit 28 for details.</bit>
+ <bit pos="4">See Outbound Error Status Register, bit 4/5/9/10/11/14/15 for details.</bit>
+ <bit pos="5">ETU FIR Register</bit>
+ <bit pos="6">See Outbound Error Status Register, bit 6 for details.</bit>
+ <bit pos="7">See Outbound Error Status Register, bit 13/22 for details.</bit>
+ <bit pos="8">See Outbound Error Status Register, bit 23/37/38/40/43/44/45/47/48/49 for details.</bit>
+ <bit pos="9">See Outbound Error Status Register, bit 50/51/52 for details.</bit>
+ <bit pos="10">See Outbound Error Status Register, bit 19/20/21/53/54/55 for details.</bit>
+ <bit pos="11">See Outbound Error Status Register, bit 16 for details.</bit>
+ <bit pos="12">See Outbound Error Status Register, bit 17 for details.</bit>
+ <bit pos="13">See Outbound Error Status Register, bit 18 for details.</bit>
+ <bit pos="14">See Outbound Error Status Register, bit 56/57 for details.</bit>
+ <bit pos="15">See Outbound Error Status Register, bit 17 for details.</bit>
+ <bit pos="16">See RSB Error Status Register, bit 00 for details.</bit>
+ <bit pos="17">See RSB Error Status Register, bit 2/3/5 for details.</bit>
+ <bit pos="18">See RSB Error Status Register, bit 1/4 for details.</bit>
+ <bit pos="19">See RSB Error Status Register, bit 9/10 for details.</bit>
+ <bit pos="20">See RSB Error Status Register, bit 8 for details.</bit>
+ <bit pos="21">See RSB Error Status Register, bit 7 for details.</bit>
+ <bit pos="22">See RSB Error Status Register, bit 6 for details.</bit>
+ <bit pos="23">See RSB Error Status Register, bit 13/14 for details.</bit>
+ <bit pos="24">See RSB Error Status Register, bit 12 for details.</bit>
+ <bit pos="25">See Outbound Error Status Register, bit 11 for details.</bit>
+ <bit pos="26">See Outbound Error Status Register, bit 15/27 for details.</bit>
+ <bit pos="27">See RSB Error Status Register, bit 17/19 for details.</bit>
+ <bit pos="28">See RSB Error Status Register, bit 16/18 for details.</bit>
+ <bit pos="29">See RSB Error Status Register, bit 30/31 for details.</bit>
+ <bit pos="30">See RSB Error Status Register, bit 28/29 for details.</bit>
+ <bit pos="31">See RSB Error Status Register, bit 24/25/26 for details.</bit>
+ <bit pos="32">See ARB Error Status Register, bit 33 for details.</bit>
+ <bit pos="33">See ARB Error Status Register, bit 27 for details.</bit>
+ <bit pos="34">See ARB Error Status Register, bit 02/03 for details.</bit>
+ <bit pos="35">See ARB Error Status Register, bit 26/28 for details.</bit>
+ <bit pos="36">See ARB Error Status Register, bit 57 for details.</bit>
+ <bit pos="37">See ARB Error Status Register, bit 58 for details.</bit>
+ <bit pos="38">See ARB Error Status Register, bit 59 for details.</bit>
+ <bit pos="39">See Outbound Error Status Register, bit 39 for details.</bit>
+ <bit pos="40">See ARB Error Status Register, bit 4/7/8/9/10/11/12/13/14/15/16/17/18/22/23/36/37/38/42/43/44/45/46/47/48/59/55/56 for details.</bit>
+ <bit pos="41">See ARB Error Status Register, bit 32/41 for details.</bit>
+ <bit pos="42">See ARB Error Status Register, bit 00/01/19 for details.</bit>
+ <bit pos="43">See ARB Error Status Register, bit 34/35 for details.</bit>
+ <bit pos="44">See ARB Error Status Register, bit 5/20/25/29 for details.</bit>
+ <bit pos="45">See ARB Error Status Register, bit 6/26/30/31 for details.</bit>
+ <bit pos="46">See ARB Error Status Register, bit 24 for details.</bit>
+ <bit pos="47">See ARB Error Status Register, bit 40 for details.</bit>
+ <bit pos="48">See MRG Error Status Register, bit 08-16/22/23/26/28/30-37/40-50 for details.</bit>
+ <bit pos="49">See MRG Error Status Register, bit 51 for details.</bit>
+ <bit pos="50">See MRG Error Status Register, bit 40/56/58/60 for details.</bit>
+ <bit pos="51">See MRG Error Status Register, bit 41/57/59/61 for details.</bit>
+ <bit pos="52">See MRG Error Status Register, bit 24 for details.</bit>
+ <bit pos="53">See MRG Error Status Register, bit 17/18 for details.</bit>
+ <bit pos="54">ETU FIR Register</bit>
+ <bit pos="55">ETU FIR Register</bit>
+ <bit pos="56">See TCE Error Status Register, bit 01/02 for details.</bit>
+ <bit pos="57">See TCE Error Status Register, bit 08 for details.</bit>
+ <bit pos="58">See TCE Error Status Register, bit 13 for details.</bit>
+ <bit pos="59">See TCE Error Status Register for details.</bit>
+ <bit pos="60">See TCE Error Status Register, bit 09/11/25/27 for details.</bit>
+ <bit pos="61">See TCE Error Status Register, bit 10/12/26/28 for details.</bit>
+ <bit pos="62">ETU FIR Register</bit>
+ <bit pos="63">FIR Internal Parity Error.</bit>
+</attn_node>
diff --git a/xml/p10/node_pci_fir.xml b/xml/p10/node_pci_fir.xml
new file mode 100644
index 0000000..bd72203
--- /dev/null
+++ b/xml/p10/node_pci_fir.xml
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PCI_FIR" reg_type="SCOM">
+ <local_fir config="W" name="PCI_FIR">
+ <instance addr="0x08010840" reg_inst="0"/>
+ <instance addr="0x08010880" reg_inst="1"/>
+ <instance addr="0x080108C0" reg_inst="2"/>
+ <instance addr="0x09010840" reg_inst="3"/>
+ <instance addr="0x09010880" reg_inst="4"/>
+ <instance addr="0x090108C0" reg_inst="5"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ </local_fir>
+ <bit pos="0">PCI FIR</bit>
+ <bit pos="1">PCI FIR</bit>
+ <bit pos="2">PCI FIR</bit>
+ <bit pos="3">PCI FIR</bit>
+ <bit pos="4">PCI FIR</bit>
+ <bit pos="5">PCI FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_pci_iop_fir.xml b/xml/p10/node_pci_iop_fir.xml
new file mode 100644
index 0000000..97cce0a
--- /dev/null
+++ b/xml/p10/node_pci_iop_fir.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PCI_IOP_FIR" reg_type="SCOM">
+ <local_fir config="" name="PCI_IOP_FIR">
+ <instance addr="0x08011100" reg_inst="0"/>
+ <instance addr="0x08011500" reg_inst="1"/>
+ <instance addr="0x09011100" reg_inst="2"/>
+ <instance addr="0x09011500" reg_inst="3"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ <action attn_type="UCS" config="11"/>
+ </local_fir>
+ <bit pos="0">Correctable error in PH0 arrays</bit>
+ <bit pos="1">Uncorrectable error in PH0 arrays</bit>
+ <bit pos="2">Correctable error in PH1 arrays</bit>
+ <bit pos="3">Uncorrectable error in PH1 arrays</bit>
+ <bit pos="4">Correctable error from SCOM in WRAP0</bit>
+ <bit pos="5">Uncorrectable error from SCOM in WRAP0</bit>
+ <bit pos="6">Correctable error from SCOM in WRAP1</bit>
+ <bit pos="7">Uncorrectable error from SCOM in WRAP1</bit>
+ <bit pos="8">Correctable error from SCRUB in WRAP0</bit>
+ <bit pos="9">Uncorrectable error from SCRUB in WRAP0</bit>
+ <bit pos="10">Correctable error from SCRUB in WRAP1</bit>
+ <bit pos="11">Uncorrectable error from SCRUB in WRAP1</bit>
+</attn_node>
diff --git a/xml/p10/node_pci_local_fir.xml b/xml/p10/node_pci_local_fir.xml
new file mode 100644
index 0000000..b992eff
--- /dev/null
+++ b/xml/p10/node_pci_local_fir.xml
@@ -0,0 +1,76 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PCI_LOCAL_FIR" reg_type="SCOM">
+ <local_fir config="W2" name="PCI_LOCAL_FIR">
+ <instance addr="0x08040100" reg_inst="0"/>
+ <instance addr="0x09040100" reg_inst="1"/>
+ <action attn_type="CS" config="000"/>
+ <action attn_type="RE" config="010"/>
+ <action attn_type="SPA" config="100"/>
+ <action attn_type="UCS" config="110"/>
+ <action attn_type="HA" config="001"/>
+ </local_fir>
+ <bit pos="0">CFIR - Parity or PCB access error</bit>
+ <bit pos="1">CPLT_CTRL - PCB access error</bit>
+ <bit pos="2">CC - PCB access error - read and clear nn03000F</bit>
+ <bit pos="3">CC - Clock Control Error - read and clear nn03000F</bit>
+ <bit pos="4">PSC - PSCOM access error - read and clear nn01001</bit>
+ <bit pos="5">PSC - internal or ring interface error - read and clear nn01001</bit>
+ <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050013</bit>
+ <bit pos="7">THERM - pcb error</bit>
+ <bit pos="8">THERMTRIP - Critical temperature indicator</bit>
+ <bit pos="9">THERMTRIP - Fatal temperature indicator</bit>
+ <bit pos="10">VOLTTRIP - Voltage sense error</bit>
+ <bit pos="11">DBG - scom parity fail</bit>
+ <bit pos="12">reserved</bit>
+ <bit pos="13">reserved</bit>
+ <bit pos="14">reserved</bit>
+ <bit pos="15">reserved</bit>
+ <bit pos="16">reserved</bit>
+ <bit pos="17">reserved</bit>
+ <bit pos="18">reserved</bit>
+ <bit pos="19">reserved</bit>
+ <bit pos="20">Trace00 - scom parity err</bit>
+ <bit pos="21">Trace01 - scom parity err - Unused in Axon,PCI</bit>
+ <bit pos="22">unused</bit>
+ <bit pos="23">unused</bit>
+ <bit pos="24">unused</bit>
+ <bit pos="25">unused</bit>
+ <bit pos="26">unused</bit>
+ <bit pos="27">unused</bit>
+ <bit pos="28">unused</bit>
+ <bit pos="29">unused</bit>
+ <bit pos="30">unused</bit>
+ <bit pos="31">unused</bit>
+ <bit pos="32">unused</bit>
+ <bit pos="33">unused</bit>
+ <bit pos="34">unused</bit>
+ <bit pos="35">unused</bit>
+ <bit pos="36">unused</bit>
+ <bit pos="37">unused</bit>
+ <bit pos="38">unused</bit>
+ <bit pos="39">unused</bit>
+ <bit pos="40">unused</bit>
+ <bit pos="41">unused</bit>
+ <bit pos="42">unused</bit>
+ <bit pos="43">unused</bit>
+ <bit pos="44">unused</bit>
+ <bit pos="45">unused</bit>
+ <bit pos="46">unused</bit>
+ <bit pos="47">unused</bit>
+ <bit pos="48">unused</bit>
+ <bit pos="49">unused</bit>
+ <bit pos="50">unused</bit>
+ <bit pos="51">unused</bit>
+ <bit pos="52">unused</bit>
+ <bit pos="53">unused</bit>
+ <bit pos="54">unused</bit>
+ <bit pos="55">unused</bit>
+ <bit pos="56">unused</bit>
+ <bit pos="57">unused</bit>
+ <bit pos="58">unused</bit>
+ <bit pos="59">unused</bit>
+ <bit pos="60">unused</bit>
+ <bit pos="61">unused</bit>
+ <bit pos="62">unused</bit>
+ <bit pos="63">ext_local_xstop</bit>
+</attn_node>
diff --git a/xml/p10/node_pci_nest_fir.xml b/xml/p10/node_pci_nest_fir.xml
new file mode 100644
index 0000000..6f5b261
--- /dev/null
+++ b/xml/p10/node_pci_nest_fir.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PCI_NEST_FIR" reg_type="SCOM">
+ <local_fir config="W" name="PCI_NEST_FIR">
+ <instance addr="0x03011840" reg_inst="0"/>
+ <instance addr="0x03011880" reg_inst="1"/>
+ <instance addr="0x030118C0" reg_inst="2"/>
+ <instance addr="0x02011840" reg_inst="3"/>
+ <instance addr="0x02011880" reg_inst="4"/>
+ <instance addr="0x020118C0" reg_inst="5"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ </local_fir>
+ <bit pos="0">PCI Nest FIR NFIR</bit>
+ <bit pos="1">PCI Nest FIR NFIR</bit>
+ <bit pos="2">PCI Nest FIR NFIR</bit>
+ <bit pos="3">PCI Nest FIR NFIR</bit>
+ <bit pos="4">PCI Nest FIR NFIR</bit>
+ <bit pos="5">PCI Nest FIR NFIR</bit>
+ <bit pos="6">PCI Nest FIR NFIR</bit>
+ <bit pos="7">PCI Nest FIR NFIR</bit>
+ <bit pos="8">PCI Nest FIR NFIR</bit>
+ <bit pos="9">PCI Nest FIR NFIR</bit>
+ <bit pos="10">PCI Nest FIR NFIR</bit>
+ <bit pos="11">PCI Nest FIR NFIR</bit>
+ <bit pos="12">PCI Nest FIR NFIR</bit>
+ <bit pos="13">PCI Nest FIR NFIR</bit>
+ <bit pos="14">PCI Nest FIR NFIR</bit>
+ <bit pos="15">PCI Nest FIR NFIR</bit>
+ <bit pos="16">PCI Nest FIR NFIR</bit>
+ <bit pos="17">PCI Nest FIR NFIR</bit>
+ <bit pos="18">PCI Nest FIR NFIR</bit>
+ <bit pos="19">PCI Nest FIR NFIR</bit>
+ <bit pos="20">PCI Nest FIR NFIR</bit>
+ <bit pos="21">PCI Nest FIR NFIR</bit>
+ <bit pos="22">PCI Nest FIR NFIR</bit>
+ <bit pos="23">PCI Nest FIR NFIR</bit>
+ <bit pos="24">PCI Nest FIR NFIR</bit>
+ <bit pos="25">PCI Nest FIR NFIR</bit>
+ <bit pos="26">PCI Nest FIR NFIR</bit>
+ <bit pos="27">PCI Nest FIR NFIR</bit>
+</attn_node>
diff --git a/xml/p10/node_psihb_fir.xml b/xml/p10/node_psihb_fir.xml
new file mode 100644
index 0000000..fa696a5
--- /dev/null
+++ b/xml/p10/node_psihb_fir.xml
@@ -0,0 +1,36 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PSIHB_FIR" reg_type="SCOM">
+ <local_fir config="" name="PSIHB_FIR">
+ <instance addr="0x03011D00" reg_inst="0"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ </local_fir>
+ <bit pos="0">CE from PowerBus data</bit>
+ <bit pos="1">UE from PowerBus data</bit>
+ <bit pos="2">SUE from PowerBus data</bit>
+ <bit pos="3">Interrupt Condition present in PSIHB</bit>
+ <bit pos="4">Interrupt from FSP is being processed</bit>
+ <bit pos="5">CE from PSILL data</bit>
+ <bit pos="6">UE from PSILL data</bit>
+ <bit pos="7">Error bit set, ignores the interrupt mask</bit>
+ <bit pos="8">Invalid TType Hit on PHB or FSP bar</bit>
+ <bit pos="9">Invalid CResp returned to command issued by PSIHB</bit>
+ <bit pos="10">PowerBus time out waiting for data grant</bit>
+ <bit pos="11">PB parity error</bit>
+ <bit pos="12">FSP tried access to trusted space</bit>
+ <bit pos="13">Unexpected PB CRESP or DATA</bit>
+ <bit pos="14">Interrupt register change while interrupt still pending</bit>
+ <bit pos="15">PSI Interrupt address Error</bit>
+ <bit pos="16">OCC Interrupt address Error</bit>
+ <bit pos="17">FSI Interrupt address Error</bit>
+ <bit pos="18">LPC Interrupt address Error</bit>
+ <bit pos="19">LOCAL ERROR Interrupt address Error</bit>
+ <bit pos="20">HOST ERROR Interrupt address Error</bit>
+ <bit pos="21">PSI global error bit 0</bit>
+ <bit pos="22">PSI global error bit 1</bit>
+ <bit pos="23">Upstream error</bit>
+ <bit pos="24">Spare fir</bit>
+ <bit pos="25">Spare fir</bit>
+ <bit pos="26">Spare fir</bit>
+ <bit pos="27">fir parity Error</bit>
+</attn_node>
diff --git a/xml/p10/node_tp_local_fir.xml b/xml/p10/node_tp_local_fir.xml
new file mode 100644
index 0000000..6c82c2f
--- /dev/null
+++ b/xml/p10/node_tp_local_fir.xml
@@ -0,0 +1,75 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="TP_LOCAL_FIR" reg_type="SCOM">
+ <local_fir config="W2" name="TP_LOCAL_FIR">
+ <instance addr="0x01040100" reg_inst="0"/>
+ <action attn_type="CS" config="000"/>
+ <action attn_type="RE" config="010"/>
+ <action attn_type="SPA" config="100"/>
+ <action attn_type="UCS" config="110"/>
+ <action attn_type="HA" config="001"/>
+ </local_fir>
+ <bit pos="0">CFIR - Parity or PCB access error</bit>
+ <bit pos="1">CPLT_CTRL - PCB access error</bit>
+ <bit pos="2">CC - PCB access error - read and clear nn03000F</bit>
+ <bit pos="3">CC - Clock Control Error - read and clear nn03000F</bit>
+ <bit pos="4">PSC - PSCOM access error - read and clear nn01001</bit>
+ <bit pos="5">PSC - internal or ring interface error - read and clear nn01001</bit>
+ <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050013</bit>
+ <bit pos="7">THERM - pcb error</bit>
+ <bit pos="8">THERMTRIP - Critical temperature indicator</bit>
+ <bit pos="9">THERMTRIP - Fatal temperature indicator</bit>
+ <bit pos="10">VOLTTRIP - Voltage sense error</bit>
+ <bit pos="11">DBG - scom parity fail</bit>
+ <bit pos="12">reserved</bit>
+ <bit pos="13">reserved</bit>
+ <bit pos="14">reserved</bit>
+ <bit pos="15">reserved</bit>
+ <bit pos="16">reserved</bit>
+ <bit pos="17">reserved</bit>
+ <bit pos="18">reserved</bit>
+ <bit pos="19">reserved</bit>
+ <bit pos="20">Trace00 - scom parity err</bit>
+ <bit pos="21">ITR - FMU error</bit>
+ <bit pos="22">ITR - PCB error</bit>
+ <bit pos="23">PCB Master - timeout - read and clear 000F001F - RECOV</bit>
+ <bit pos="24">I2CM - Parity errors, Can be considered as recoverable error</bit>
+ <bit pos="25">TOD - any error</bit>
+ <bit pos="26">TOD - access error PIB</bit>
+ <bit pos="27">TOD - unused tie0</bit>
+ <bit pos="28">PCB Slave - read and clear nn0F001F RECOV</bit>
+ <bit pos="29">SBE - PPE int hardware error</bit>
+ <bit pos="30">SBE - PPE ext hardware error</bit>
+ <bit pos="31">SBE- PPE code error</bit>
+ <bit pos="32">SBE - PPE debug code breakpoint</bit>
+ <bit pos="33">SBE - PPE in halted state</bit>
+ <bit pos="34">SBE - PPE watchdog timeout</bit>
+ <bit pos="35">SBE - unused tie0</bit>
+ <bit pos="36">SBE - unused tie0</bit>
+ <bit pos="37">SBE - PPE triggers DBG</bit>
+ <bit pos="38">OTP - SCOM access errors & single ecc correctable errors. Can be considered as Recoverable type.</bit>
+ <bit pos="39">TPIO External Trigger</bit>
+ <bit pos="40">PCB Master - DECMCAST_GRP_ERR - read and clear 000F001F - RECOV</bit>
+ <bit pos="41">PCB Master - Parity ERR - read and clear 000F001F - RECOV</bit>
+ <bit pos="42">RCS - OSC0 Error</bit>
+ <bit pos="43">RCS - OSC1 Error</bit>
+ <bit pos="44">RCS - Delay line 0 unlock</bit>
+ <bit pos="45">RCS - Delay line 1 unlock</bit>
+ <bit pos="46">PIBMEM</bit>
+ <bit pos="47">PIBMEM</bit>
+ <bit pos="48">OTP - Combination of ecc uncorrectable error and correctable error counter overflow - Can be considered as checkstop</bit>
+ <bit pos="49">DPLL_FIR_NEST_DCO_EMPTY</bit>
+ <bit pos="50">DPLL_FIR_NEST_DCO_FULL</bit>
+ <bit pos="51">DPLL_FIR_NEST_INT_ERROR</bit>
+ <bit pos="52">DPLL_FIR_PAU_DCO_EMPTY</bit>
+ <bit pos="53">DPLL_FIR_PAU_DCO_FULL</bit>
+ <bit pos="54">DPLL_FIR_PAU_INT_ERROR</bit>
+ <bit pos="55">SPI Master 0 Err</bit>
+ <bit pos="56">SPI Master 1 Err</bit>
+ <bit pos="57">SPI Master 2 Err</bit>
+ <bit pos="58">SPI Master 3 Err</bit>
+ <bit pos="59">SPI Master 4 Err</bit>
+ <bit pos="60">unused</bit>
+ <bit pos="61">unused</bit>
+ <bit pos="62">unused</bit>
+ <bit pos="63">ext_local_xstop</bit>
+</attn_node>
diff --git a/xml/p10/node_vas_fir.xml b/xml/p10/node_vas_fir.xml
new file mode 100644
index 0000000..0a90314
--- /dev/null
+++ b/xml/p10/node_vas_fir.xml
@@ -0,0 +1,61 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="VAS_FIR" reg_type="SCOM">
+ <local_fir config="W" name="VAS_FIR">
+ <instance addr="0x02011400" reg_inst="0"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ <action attn_type="UCS" config="11"/>
+ </local_fir>
+ <bit pos="0">Hardware error detected in Egress logic</bit>
+ <bit pos="1">Hardware error detected in Ingress logic</bit>
+ <bit pos="2">Hardware error detected in CQ logic</bit>
+ <bit pos="3">Hardware error detected in WC logic</bit>
+ <bit pos="4">Hardware error detected in RG logic</bit>
+ <bit pos="5">PowerBus parity error detected on CQ logic interface</bit>
+ <bit pos="6">CQ logic detected PowerBus address error on CRESP from a read operation</bit>
+ <bit pos="7">CQ logic detected PowerBus address error on CRESP from a write operation</bit>
+ <bit pos="8">Correctable ECC error detected in Egress logic</bit>
+ <bit pos="9">Correctable ECC error detected in Ingress logic</bit>
+ <bit pos="10">Correctable ECC error detected in CQ logic</bit>
+ <bit pos="11">Correctable ECC error detected in WC logic</bit>
+ <bit pos="12">Correctable ECC error detected in RG logic</bit>
+ <bit pos="13">ECC Correctable Error detected on CQ outbound PowerBus interface</bit>
+ <bit pos="14">ECC UNCorrectable Error detected on CQ outbound PowerBus interface</bit>
+ <bit pos="15">PowerBus state machine hang detected in CQ logic</bit>
+ <bit pos="16">Uncorrectable ECC error detected in Egress logic</bit>
+ <bit pos="17">Uncorrectable ECC error detected in Ingress logic</bit>
+ <bit pos="18">Uncorrectable ECC error detected in CQ logic</bit>
+ <bit pos="19">Uncorrectable ECC error detected in WC logic</bit>
+ <bit pos="20">Uncorrectable ECC error detected in RG logic</bit>
+ <bit pos="21">Parity error detected in Ingress logic</bit>
+ <bit pos="22">Software cast error detected in Ingress logic</bit>
+ <bit pos="23">VAS attempted to access a memory address which has the secure memory bit set</bit>
+ <bit pos="24">ECC sue error detected in Egress logic</bit>
+ <bit pos="25">ECC sue error detected in Ingress logic</bit>
+ <bit pos="26">ECC sue error detected in CQ logic</bit>
+ <bit pos="27">ECC sue error detected in WC logic</bit>
+ <bit pos="28">ECC sue error detected in RG logic</bit>
+ <bit pos="29">PowerBus link error detected on read operation in CQ logic</bit>
+ <bit pos="30">PowerBus link error detected on write operation in CQ logic</bit>
+ <bit pos="31">PowerBus link abort operation received in CQ logic</bit>
+ <bit pos="32">Address error detected on hypervisor MMIO read</bit>
+ <bit pos="33">Address error detected on OS MMIO read</bit>
+ <bit pos="34">Address error detected on hypervisor MMIO write</bit>
+ <bit pos="35">Address error detected on OS MMIO write</bit>
+ <bit pos="36">non-8-Byte MMIO detected by hypervisor</bit>
+ <bit pos="37">non-8-Byte MMIO detected by user or OS</bit>
+ <bit pos="38">Unused - Was Write monitor operation attempted on a window that is not open</bit>
+ <bit pos="39">Unused - Was Multiple write monotor registers match the same snooped PB operation</bit>
+ <bit pos="40">Unused - Was Page Migration Register is not valid</bit>
+ <bit pos="41">Unused - Was Page Migration Register size does not match corresponding FIFO</bit>
+ <bit pos="42">ASB_Notify sent but not claimed and interrupts were disabled in window context</bit>
+ <bit pos="43">Unused - Was Write monitor operation hit a window which has notification disabled</bit>
+ <bit pos="44">VAS rejected a PB paste command. See window status register for details</bit>
+ <bit pos="45">VAS hung waiting for data from PowerBus</bit>
+ <bit pos="46">Incoming PowerBus parity error</bit>
+ <bit pos="47">HW error from SCOM Satellite 1</bit>
+ <bit pos="48">NX Local Checkstop</bit>
+ <bit pos="49">SCOM MMIO address offset error. SCOM-initiated MMIO address did not decode to valid address.</bit>
+ <bit pos="50">TopoID Error Bit</bit>
+ <bit pos="51">Unused bit</bit>
+</attn_node>