Copied Chip Data XML from Hostboot project
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I0a230be8ba2840768e2097fd4e479c8feb8fc452
diff --git a/xml/p10/node_eq_core_thread_state.xml b/xml/p10/node_eq_core_thread_state.xml
new file mode 100644
index 0000000..49a68d5
--- /dev/null
+++ b/xml/p10/node_eq_core_thread_state.xml
@@ -0,0 +1,66 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="EQ_CORE_THREAD_STATE" reg_type="SCOM">
+ <register name="CORE_THREAD_STATE">
+ <instance addr="0x20028412" reg_inst="0"/>
+ <instance addr="0x20024412" reg_inst="1"/>
+ <instance addr="0x20022412" reg_inst="2"/>
+ <instance addr="0x20021412" reg_inst="3"/>
+ <instance addr="0x21028412" reg_inst="4"/>
+ <instance addr="0x21024412" reg_inst="5"/>
+ <instance addr="0x21022412" reg_inst="6"/>
+ <instance addr="0x21021412" reg_inst="7"/>
+ <instance addr="0x22028412" reg_inst="8"/>
+ <instance addr="0x22024412" reg_inst="9"/>
+ <instance addr="0x22022412" reg_inst="10"/>
+ <instance addr="0x22021412" reg_inst="11"/>
+ <instance addr="0x23028412" reg_inst="12"/>
+ <instance addr="0x23024412" reg_inst="13"/>
+ <instance addr="0x23022412" reg_inst="14"/>
+ <instance addr="0x23021412" reg_inst="15"/>
+ <instance addr="0x24028412" reg_inst="16"/>
+ <instance addr="0x24024412" reg_inst="17"/>
+ <instance addr="0x24022412" reg_inst="18"/>
+ <instance addr="0x24021412" reg_inst="19"/>
+ <instance addr="0x25028412" reg_inst="20"/>
+ <instance addr="0x25024412" reg_inst="21"/>
+ <instance addr="0x25022412" reg_inst="22"/>
+ <instance addr="0x25021412" reg_inst="23"/>
+ <instance addr="0x26028412" reg_inst="24"/>
+ <instance addr="0x26024412" reg_inst="25"/>
+ <instance addr="0x26022412" reg_inst="26"/>
+ <instance addr="0x26021412" reg_inst="27"/>
+ <instance addr="0x27028412" reg_inst="28"/>
+ <instance addr="0x27024412" reg_inst="29"/>
+ <instance addr="0x27022412" reg_inst="30"/>
+ <instance addr="0x27021412" reg_inst="31"/>
+ </register>
+ <!-- Each EQ_SPATTN will only report 4 of the possible 8 threads back to the
+ CFIR_EQ_SPA. The reported threads are dependent on the core mode. In
+ Normal Core Mode (CORE_THREAD_STATE[63]=0), only threads 0-3 report to
+ the CFIR_EQ_SPA. In Fused Core Mode (CORE_THREAD_STATE[63]=1), both
+ EQ_SPATTN in the fused core pair display the exact same information for
+ all eight threads in the pair. However, only the even threads on the
+ even cores and the odd threads on the odd cores report to the
+ CFIR_EQ_SPA. -->
+ <rule attn_type="SPA" node_inst="0:31">
+ <!-- (~CORE_THREAD_STATE[63] << 63) | (CORE_THREAD_STATE[63] << 62) -->
+ <expr type="or">
+ <expr type="lshift" value1="63">
+ <expr type="and">
+ <expr type="not">
+ <expr type="reg" value1="CORE_THREAD_STATE"/>
+ </expr>
+ <expr type="int" value1="0x0000000000000001"/>
+ </expr>
+ </expr>
+ <expr type="lshift" value1="62">
+ <expr type="and">
+ <expr type="reg" value1="CORE_THREAD_STATE"/>
+ <expr type="int" value1="0x0000000000000001"/>
+ </expr>
+ </expr>
+ </expr>
+ </rule>
+ <bit child_node="EQ_SPATTN_NORMAL" node_inst="0:31" pos="0">EQ_SPATTN normal core mode</bit>
+ <bit child_node="EQ_SPATTN_FUSED" node_inst="0:31" pos="1">EQ_SPATTN fused core mode</bit>
+</attn_node>