Copied Chip Data XML from Hostboot project
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I0a230be8ba2840768e2097fd4e479c8feb8fc452
diff --git a/xml/p10/node_eq_l2_fir.xml b/xml/p10/node_eq_l2_fir.xml
new file mode 100644
index 0000000..4256626
--- /dev/null
+++ b/xml/p10/node_eq_l2_fir.xml
@@ -0,0 +1,79 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="EQ_L2_FIR" reg_type="SCOM">
+ <local_fir config="" name="EQ_L2_FIR">
+ <instance addr="0x20028000" reg_inst="0"/>
+ <instance addr="0x20024000" reg_inst="1"/>
+ <instance addr="0x20022000" reg_inst="2"/>
+ <instance addr="0x20021000" reg_inst="3"/>
+ <instance addr="0x21028000" reg_inst="4"/>
+ <instance addr="0x21024000" reg_inst="5"/>
+ <instance addr="0x21022000" reg_inst="6"/>
+ <instance addr="0x21021000" reg_inst="7"/>
+ <instance addr="0x22028000" reg_inst="8"/>
+ <instance addr="0x22024000" reg_inst="9"/>
+ <instance addr="0x22022000" reg_inst="10"/>
+ <instance addr="0x22021000" reg_inst="11"/>
+ <instance addr="0x23028000" reg_inst="12"/>
+ <instance addr="0x23024000" reg_inst="13"/>
+ <instance addr="0x23022000" reg_inst="14"/>
+ <instance addr="0x23021000" reg_inst="15"/>
+ <instance addr="0x24028000" reg_inst="16"/>
+ <instance addr="0x24024000" reg_inst="17"/>
+ <instance addr="0x24022000" reg_inst="18"/>
+ <instance addr="0x24021000" reg_inst="19"/>
+ <instance addr="0x25028000" reg_inst="20"/>
+ <instance addr="0x25024000" reg_inst="21"/>
+ <instance addr="0x25022000" reg_inst="22"/>
+ <instance addr="0x25021000" reg_inst="23"/>
+ <instance addr="0x26028000" reg_inst="24"/>
+ <instance addr="0x26024000" reg_inst="25"/>
+ <instance addr="0x26022000" reg_inst="26"/>
+ <instance addr="0x26021000" reg_inst="27"/>
+ <instance addr="0x27028000" reg_inst="28"/>
+ <instance addr="0x27024000" reg_inst="29"/>
+ <instance addr="0x27022000" reg_inst="30"/>
+ <instance addr="0x27021000" reg_inst="31"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ </local_fir>
+ <bit pos="0">H/W Trigger Mechanism at point cache read occurs that detects a CE by ECCCK on RC/CO/SN read. Note: PRD counts the number of these and then will trigger LineDelete.</bit>
+ <bit pos="1">H/W Trigger Mechanism at point cache read occurs that detects a UE(non SUE) by ECCCK on RC/CO/SN read.</bit>
+ <bit pos="2">H/W Trigger Mechanism at point cache read occurs that detects a SUE by ECCCK on RC/CO/SN read.</bit>
+ <bit pos="3">H/W intiated Line Delete occured (Id state injected into the dir) by RC or SN machine.</bit>
+ <bit pos="4">L2 Castout where L2 cache read detected UE/SUE and Line is M,Mu,T,Tn</bit>
+ <bit pos="5">L2 Castout where L2 cache read detected UE/SUE and Line is Me,Te,Ten,Sl,S</bit>
+ <bit pos="6">L2 corrected a CE in the L2 directory</bit>
+ <bit pos="7">L2 detected a UE in the L2 directory</bit>
+ <bit pos="8">L2 detected a SBCE in the L2 directory</bit>
+ <bit pos="9">PEC attempted to repair and CO a SBCE condition but failed(eg CO disp failed). Cache line was lost.</bit>
+ <bit pos="10">DEPRICATED: THIS FIR BIT SHOULD ALWAYS BE MASKED. Multiple CE/UE deteceted between 2 hang 'early hang' pulse time window</bit>
+ <bit pos="11">LRU array has illegal valu in it(due to flipped bit)</bit>
+ <bit pos="12">RC timed out waiting for powerbus to return data.</bit>
+ <bit pos="13">NCU timed out waiting for powerbus to return data.</bit>
+ <bit pos="14">Internal h/w control error</bit>
+ <bit pos="15">All members in a single congruence class has been deleted</bit>
+ <bit pos="16">Cache Inhibited Ld/St hit a line in the L2 cache. SW error</bit>
+ <bit pos="17">RC was doing a fabric op on behalf of a load and got an cresp=addr_err</bit>
+ <bit pos="18">RC was doing a fabric op on behalf of a store and got an cresp=addr_err</bit>
+ <bit pos="19">RC incoming Power Bus data had a CE error.</bit>
+ <bit pos="20">RC incoming Power Bus data had a UE error.</bit>
+ <bit pos="21">RC incoming Power Bus data had a SUE error.</bit>
+ <bit pos="22">Targetted nodal request got rty_inc cresp.</bit>
+ <bit pos="23">RC was doing a fabric op on behalf of a load and got an cresp=addr_err for hyp memory</bit>
+ <bit pos="24">RCDAT read parity error.</bit>
+ <bit pos="25">CO or SNP was doing a fabric op on behalf of a store and got an cresp=addr_err</bit>
+ <bit pos="26">LVDIR took a parity error.</bit>
+ <bit pos="27">bad topology table config software error</bit>
+ <bit pos="28">Darn timed out waiting for data.</bit>
+ <bit pos="29">Early hang in L2.</bit>
+ <bit pos="30">Unexpected cast-out or push during chip_contained mode, maybe also during host-boot before memory available. Mask after host-boot memory ipl.</bit>
+ <bit pos="31">L2 FIR Register</bit>
+ <bit pos="32">PEC Phase3 timeout, recoverable problem, information only.</bit>
+ <bit pos="33">L2 FIR Register</bit>
+ <bit pos="34">L2 FIR Register</bit>
+ <bit pos="35">L2 FIR Register</bit>
+ <bit pos="36">Cache read CE and UE popped within a short hang pulse. Could be a triple bit error.</bit>
+ <bit pos="37">L2 FIR Register</bit>
+ <bit pos="38">L2 FIR Register</bit>
+ <bit pos="39">L2 FIR Register</bit>
+</attn_node>