Copied Chip Data XML from Hostboot project
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I0a230be8ba2840768e2097fd4e479c8feb8fc452
diff --git a/xml/p10/node_eq_spattn_normal.xml b/xml/p10/node_eq_spattn_normal.xml
new file mode 100644
index 0000000..fa83655
--- /dev/null
+++ b/xml/p10/node_eq_spattn_normal.xml
@@ -0,0 +1,97 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="EQ_SPATTN_NORMAL" reg_type="SCOM">
+ <register name="EQ_SPATTN">
+ <instance addr="0x20028499" reg_inst="0"/>
+ <instance addr="0x20024499" reg_inst="1"/>
+ <instance addr="0x20022499" reg_inst="2"/>
+ <instance addr="0x20021499" reg_inst="3"/>
+ <instance addr="0x21028499" reg_inst="4"/>
+ <instance addr="0x21024499" reg_inst="5"/>
+ <instance addr="0x21022499" reg_inst="6"/>
+ <instance addr="0x21021499" reg_inst="7"/>
+ <instance addr="0x22028499" reg_inst="8"/>
+ <instance addr="0x22024499" reg_inst="9"/>
+ <instance addr="0x22022499" reg_inst="10"/>
+ <instance addr="0x22021499" reg_inst="11"/>
+ <instance addr="0x23028499" reg_inst="12"/>
+ <instance addr="0x23024499" reg_inst="13"/>
+ <instance addr="0x23022499" reg_inst="14"/>
+ <instance addr="0x23021499" reg_inst="15"/>
+ <instance addr="0x24028499" reg_inst="16"/>
+ <instance addr="0x24024499" reg_inst="17"/>
+ <instance addr="0x24022499" reg_inst="18"/>
+ <instance addr="0x24021499" reg_inst="19"/>
+ <instance addr="0x25028499" reg_inst="20"/>
+ <instance addr="0x25024499" reg_inst="21"/>
+ <instance addr="0x25022499" reg_inst="22"/>
+ <instance addr="0x25021499" reg_inst="23"/>
+ <instance addr="0x26028499" reg_inst="24"/>
+ <instance addr="0x26024499" reg_inst="25"/>
+ <instance addr="0x26022499" reg_inst="26"/>
+ <instance addr="0x26021499" reg_inst="27"/>
+ <instance addr="0x27028499" reg_inst="28"/>
+ <instance addr="0x27024499" reg_inst="29"/>
+ <instance addr="0x27022499" reg_inst="30"/>
+ <instance addr="0x27021499" reg_inst="31"/>
+ </register>
+ <register name="EQ_SPATTN_MASK">
+ <instance addr="0x2002849a" reg_inst="0"/>
+ <instance addr="0x2002449a" reg_inst="1"/>
+ <instance addr="0x2002249a" reg_inst="2"/>
+ <instance addr="0x2002149a" reg_inst="3"/>
+ <instance addr="0x2102849a" reg_inst="4"/>
+ <instance addr="0x2102449a" reg_inst="5"/>
+ <instance addr="0x2102249a" reg_inst="6"/>
+ <instance addr="0x2102149a" reg_inst="7"/>
+ <instance addr="0x2202849a" reg_inst="8"/>
+ <instance addr="0x2202449a" reg_inst="9"/>
+ <instance addr="0x2202249a" reg_inst="10"/>
+ <instance addr="0x2202149a" reg_inst="11"/>
+ <instance addr="0x2302849a" reg_inst="12"/>
+ <instance addr="0x2302449a" reg_inst="13"/>
+ <instance addr="0x2302249a" reg_inst="14"/>
+ <instance addr="0x2302149a" reg_inst="15"/>
+ <instance addr="0x2402849a" reg_inst="16"/>
+ <instance addr="0x2402449a" reg_inst="17"/>
+ <instance addr="0x2402249a" reg_inst="18"/>
+ <instance addr="0x2402149a" reg_inst="19"/>
+ <instance addr="0x2502849a" reg_inst="20"/>
+ <instance addr="0x2502449a" reg_inst="21"/>
+ <instance addr="0x2502249a" reg_inst="22"/>
+ <instance addr="0x2502149a" reg_inst="23"/>
+ <instance addr="0x2602849a" reg_inst="24"/>
+ <instance addr="0x2602449a" reg_inst="25"/>
+ <instance addr="0x2602249a" reg_inst="26"/>
+ <instance addr="0x2602149a" reg_inst="27"/>
+ <instance addr="0x2702849a" reg_inst="28"/>
+ <instance addr="0x2702449a" reg_inst="29"/>
+ <instance addr="0x2702249a" reg_inst="30"/>
+ <instance addr="0x2702149a" reg_inst="31"/>
+ </register>
+ <!-- In Normal Core mode, only threads 0-3 report to the CFIR_EQ_SPA. -->
+ <rule attn_type="SPA" node_inst="0:31">
+ <expr type="and">
+ <expr type="reg" value1="EQ_SPATTN"/>
+ <expr type="not">
+ <expr type="reg" value1="EQ_SPATTN_MASK"/>
+ </expr>
+ <expr type="int" value1="0xffff000000000000"/>
+ </expr>
+ </rule>
+ <bit pos="0">lt0_spr_instr_stop</bit>
+ <bit pos="1">lt0_attn_complete</bit>
+ <bit pos="2">lt0_core_checkstop_recovery_handshake</bit>
+ <bit pos="3">lt0_core_code_to_sp</bit>
+ <bit pos="4">lt1_spr_instr_stop</bit>
+ <bit pos="5">lt1_attn_complete</bit>
+ <bit pos="6">lt1_core_checkstop_recovery_handshake</bit>
+ <bit pos="7">lt1_core_code_to_sp</bit>
+ <bit pos="8">lt2_spr_instr_stop</bit>
+ <bit pos="9">lt2_attn_complete</bit>
+ <bit pos="10">lt2_core_checkstop_recovery_handshake</bit>
+ <bit pos="11">lt2_core_code_to_sp</bit>
+ <bit pos="12">lt3_spr_instr_stop</bit>
+ <bit pos="13">lt3_attn_complete</bit>
+ <bit pos="14">lt3_core_checkstop_recovery_handshake</bit>
+ <bit pos="15">lt3_core_code_to_sp</bit>
+</attn_node>