Copied Chip Data XML from Hostboot project

Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I0a230be8ba2840768e2097fd4e479c8feb8fc452
diff --git a/xml/p10/node_iohs_dlp_fir.xml b/xml/p10/node_iohs_dlp_fir.xml
new file mode 100644
index 0000000..436a42c
--- /dev/null
+++ b/xml/p10/node_iohs_dlp_fir.xml
@@ -0,0 +1,78 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="IOHS_DLP_FIR" reg_type="SCOM">
+    <local_fir config="W" name="IOHS_DLP_FIR">
+        <instance addr="0x18011000" reg_inst="0"/>
+        <instance addr="0x19011000" reg_inst="1"/>
+        <instance addr="0x1A011000" reg_inst="2"/>
+        <instance addr="0x1B011000" reg_inst="3"/>
+        <instance addr="0x1C011000" reg_inst="4"/>
+        <instance addr="0x1D011000" reg_inst="5"/>
+        <instance addr="0x1E011000" reg_inst="6"/>
+        <instance addr="0x1F011000" reg_inst="7"/>
+        <action attn_type="CS" config="00"/>
+        <action attn_type="RE" config="01"/>
+        <action attn_type="SPA" config="10"/>
+    </local_fir>
+    <bit pos="0">OLL link0 trained</bit>
+    <bit pos="1">OLL link1 trained</bit>
+    <bit pos="2">link0 op irq</bit>
+    <bit pos="3">link1 op irq</bit>
+    <bit pos="4">link0 replay threshold</bit>
+    <bit pos="5">link1 replay threshold</bit>
+    <bit pos="6">link0 crc error</bit>
+    <bit pos="7">link1 crc error</bit>
+    <bit pos="8">link0 nak received</bit>
+    <bit pos="9">link1 nak received</bit>
+    <bit pos="10">link0 replay buffer full</bit>
+    <bit pos="11">link1 replay buffer full</bit>
+    <bit pos="12">link0 sl ecc threshold</bit>
+    <bit pos="13">link1 sl ecc threshold</bit>
+    <bit pos="14">link0 sl ecc correctable</bit>
+    <bit pos="15">link1 sl ecc correctable</bit>
+    <bit pos="16">link0 sl ecc ue</bit>
+    <bit pos="17">link1 sl ecc ue</bit>
+    <bit pos="18">link0 retrain threshold</bit>
+    <bit pos="19">link1 retrain threshold</bit>
+    <bit pos="20">link0 loss block align</bit>
+    <bit pos="21">link1 loss block align</bit>
+    <bit pos="22">link0 invalid block</bit>
+    <bit pos="23">link1 invalid block</bit>
+    <bit pos="24">link0 deskew error</bit>
+    <bit pos="25">link1 deskew error</bit>
+    <bit pos="26">link0 deskew overflow</bit>
+    <bit pos="27">link1 deskew overflow</bit>
+    <bit pos="28">link0 sw retrain</bit>
+    <bit pos="29">link1 sw retrain</bit>
+    <bit pos="30">link0 ack queue overflow</bit>
+    <bit pos="31">link1 ack queue overflow</bit>
+    <bit pos="32">link0 ack queue underflow</bit>
+    <bit pos="33">link1 ack queue underflow</bit>
+    <bit pos="34">link0 num replay</bit>
+    <bit pos="35">link1 num replay</bit>
+    <bit pos="36">link0 training set received</bit>
+    <bit pos="37">link1 training set received</bit>
+    <bit pos="38">link0 prbs select error</bit>
+    <bit pos="39">link1 prbs select error</bit>
+    <bit pos="40">link0 tcomplete bad</bit>
+    <bit pos="41">link1 tcomplete bad</bit>
+    <bit pos="42">link0 no spare lane available</bit>
+    <bit pos="43">link1 no spare lane available</bit>
+    <bit pos="44">link0 spare done</bit>
+    <bit pos="45">link1 spare done</bit>
+    <bit pos="46">link0 too many crc errors</bit>
+    <bit pos="47">link1 too many crc errors</bit>
+    <bit pos="48">link0 npu/dlx error</bit>
+    <bit pos="49">link1 npu/dlx error</bit>
+    <bit pos="50">link0 osc switch</bit>
+    <bit pos="51">link1 osc switch</bit>
+    <bit pos="52">link0 correctable array error</bit>
+    <bit pos="53">link1 correctable array error</bit>
+    <bit pos="54">link0 uncorrectable array error</bit>
+    <bit pos="55">link1 uncorrectable array error</bit>
+    <bit pos="56">link0 training failed</bit>
+    <bit pos="57">link1 training failed</bit>
+    <bit pos="58">link0 unrecoverable error</bit>
+    <bit pos="59">link1 unrecoverable error</bit>
+    <bit pos="60">link0 internal error</bit>
+    <bit pos="61">link1 internal error</bit>
+</attn_node>