Copied Chip Data XML from Hostboot project
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I0a230be8ba2840768e2097fd4e479c8feb8fc452
diff --git a/xml/p10/node_occ_fir.xml b/xml/p10/node_occ_fir.xml
new file mode 100644
index 0000000..35f1bac
--- /dev/null
+++ b/xml/p10/node_occ_fir.xml
@@ -0,0 +1,70 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="OCC_FIR" reg_type="SCOM">
+ <local_fir config="" name="OCC_FIR">
+ <instance addr="0x01010800" reg_inst="0"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ </local_fir>
+ <bit pos="0">Input tied to 0. Used by OCC Firmware to produce an attention to the FSP.</bit>
+ <bit pos="1">Input tied to 0. Used by OCC Firmware to produce an attention tothe FSP.</bit>
+ <bit pos="2">Input tied to 0. Used by STOP GPE code to indicated to HYP that a QME has indicated a fault.</bit>
+ <bit pos="3">Input tied to 0. Written by stop recovery firmware to indicate that the host side actions are complete and that FFDC information is available for</bit>
+ <bit pos="4">OCC Heartbeat Error</bit>
+ <bit pos="5">GPE0 asserted a watchdog timeout condition</bit>
+ <bit pos="6">GPE1 asserted a watchdog timeout condition</bit>
+ <bit pos="7">GPE2 asserted a watchdog timeout condition</bit>
+ <bit pos="8">GPE3 asserted a watchdog timeout condition</bit>
+ <bit pos="9">GPE0 asserted an error condition that caused it to halt.</bit>
+ <bit pos="10">GPE1 asserted an error condition that caused it to halt.</bit>
+ <bit pos="11">GPE2 asserted an error condition that caused it to halt.</bit>
+ <bit pos="12">GPE3 asserted an error condition that caused it to halt.</bit>
+ <bit pos="13">OCB Error (recoverable error)</bit>
+ <bit pos="14">SRAM Uncorrectable Error (recoverable error)</bit>
+ <bit pos="15">SRAM Correctable Error (masked (product); recoverable error (mfg)</bit>
+ <bit pos="16">GPE0 asserted a halt condition</bit>
+ <bit pos="17">GPE1 asserted a halt condition</bit>
+ <bit pos="18">GPE2 asserted a halt condition</bit>
+ <bit pos="19">GPE3 asserted a halt condition</bit>
+ <bit pos="20">GPE0 attempted to write outside the region defined in GPESWPR</bit>
+ <bit pos="21">GPE1 attempted to write outside the region defined in GPESWPR</bit>
+ <bit pos="22">GPE2 attempted to write outside the region defined in GPESWPR</bit>
+ <bit pos="23">GPE3 attempted to write outside the region defined in GPESWPR</bit>
+ <bit pos="24">Implemented but not used, inputs tied to 0</bit>
+ <bit pos="25">Implemented but not used, inputs tied to 0</bit>
+ <bit pos="26">External Trigger pin active (recoverable (product)</bit>
+ <bit pos="27">PPC405 Core Reset Output asserted (??? firmware)</bit>
+ <bit pos="28">PPC405 Chip Reset Output asserted (??? firmware)</bit>
+ <bit pos="29">PPC405 System Reset Output asserted (??? firmware)</bit>
+ <bit pos="30">PPC405 Wait State asserted (??? firmware)</bit>
+ <bit pos="31">PPC405 Stop Ack output asserted (recoverable -> logging)</bit>
+ <bit pos="32">OCB Direct Bridge Error - See OCCERRRPT2[8:11] for error source</bit>
+ <bit pos="33">OCB PIB Address Parity Error - (PIB read or write operation). Note: may be set for either direct bridge or indirect channel operations.</bit>
+ <bit pos="34">Indirect Channel Error</bit>
+ <bit pos="35">Parity error detected on OPIT interrupt bus. Interrupts are hung.</bit>
+ <bit pos="36">OPIT interrupt state machine error occurred.</bit>
+ <bit pos="37">Implemented but not used. Input tied to 0</bit>
+ <bit pos="38">Implemented but not used. Input tied to 0</bit>
+ <bit pos="39">Implemented but not used. Input tied to 0</bit>
+ <bit pos="40">Implemented but not used. Input tied to 0</bit>
+ <bit pos="41">Implemented but not used. Input tied to 0</bit>
+ <bit pos="42">JTAG accelerator error</bit>
+ <bit pos="43">Any OCI Slave error occurreds</bit>
+ <bit pos="44">PPC405 cache UE</bit>
+ <bit pos="45">PPC405 cache CE</bit>
+ <bit pos="46">PPC405 Machine Check</bit>
+ <bit pos="47">SRAM spare direct error Summary. See OCCERRRPT2[0:3] for details</bit>
+ <bit pos="48">SRAM Controller Error - A read, write, or parity error occurred in the SRAM tank controller. See OCCERRRPT2[12:18] for more information</bit>
+ <bit pos="49">Implemented but notused. Input tied to 0</bit>
+ <bit pos="50">Implemented but notused. Input tied to 0</bit>
+ <bit pos="51">OCI slave error for GPE0 (see OCCERRPT for details)</bit>
+ <bit pos="52">OCI slave error for GPE1 (see OCCERRPT for details)</bit>
+ <bit pos="53">OCI slave error for GPE2 (see OCCERRPT for details)</bit>
+ <bit pos="54">OCI slave error for GPE3 (see OCCERRPT for details)</bit>
+ <bit pos="55">PPC405 ICU timeout on OCI request</bit>
+ <bit pos="56">PPC405 DCU timeout on OCI request</bit>
+ <bit pos="57">Used by OCC to indicate that a fault occurred (to achieve safe mode). Connected to OCCMISC[firmware_fault].</bit>
+ <bit pos="58">Used by OCC to notify another firmware entity that an event occurred. Connected to OCCMISC[firmware_notify].</bit>
+ <bit pos="59">Implemented but not used. Inputs tied to 0.</bit>
+ <bit pos="60">Implemented but not used. Inputs tied to 0.</bit>
+ <bit pos="61">Implemented but not used. Inputs tied to 0.</bit>
+</attn_node>