commit abc51c2b6fca6ed704c6fd70426faf0038f2e807
author Zane Shelley <zshelle@us.ibm.com> Mon Nov 09 21:35:35 2020 -0600
committer Zane Shelley <zshelle@us.ibm.com> Mon Nov 09 21:41:22 2020 -0600
tree eeba8af0e35390f743f059a51a1ccab52895c4fa
parent 2e38ae5778103c1c74bc8554453efc978fa53f79

Copied Chip Data XML from Hostboot project

Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I0a230be8ba2840768e2097fd4e479c8feb8fc452

xml/p10/node_pau_fir_1.xml

diff --git a/xml/p10/node_pau_fir_1.xml b/xml/p10/node_pau_fir_1.xml
new file mode 100644
index 0000000..cacea0e
--- /dev/null
+++ b/xml/p10/node_pau_fir_1.xml
@@ -0,0 +1,78 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PAU_FIR_1" reg_type="SCOM">
+    <local_fir config="" name="PAU_FIR_1">
+        <instance addr="0x10010C40" reg_inst="0"/>
+        <instance addr="0x11010C40" reg_inst="3"/>
+        <instance addr="0x12010C40" reg_inst="4"/>
+        <instance addr="0x12011440" reg_inst="5"/>
+        <instance addr="0x13010C40" reg_inst="6"/>
+        <instance addr="0x13011440" reg_inst="7"/>
+        <action attn_type="CS" config="00"/>
+        <action attn_type="RE" config="01"/>
+        <action attn_type="UCS" config="11"/>
+    </local_fir>
+    <bit pos="0">NDL Brick0 stall</bit>
+    <bit pos="1">NDL Brick0 nostall</bit>
+    <bit pos="2">NDL Brick1 stall</bit>
+    <bit pos="3">NDL Brick1 nostall</bit>
+    <bit pos="4">NDL Brick2 stall</bit>
+    <bit pos="5">NDL Brick2 nostall</bit>
+    <bit pos="6">NDL Brick3 stall</bit>
+    <bit pos="7">NDL Brick3 nostall</bit>
+    <bit pos="8">NDL Brick4 stall</bit>
+    <bit pos="9">NDL Brick4 nostall</bit>
+    <bit pos="10">NDL Brick5 stall</bit>
+    <bit pos="11">NDL Brick5 nostall</bit>
+    <bit pos="12">MISC Register ring error (noack, &gt;1 ack)</bit>
+    <bit pos="13">MISC Parity error from interrupt base real address register</bit>
+    <bit pos="14">MISC Parity error on Indirect SCOM Address register</bit>
+    <bit pos="15">MISC Parity error on MISC Control register</bit>
+    <bit pos="16">FIR1 Reserved, bit 16</bit>
+    <bit pos="17">ATS Invalid TVT entry (TCE Table Size = 0b00000)</bit>
+    <bit pos="18">ATS TVT Address range error (no xlate: EA out of range; xlate: unused EA bits non-zero, TVE uses &gt; max # EA bits)</bit>
+    <bit pos="19">ATS TCE Page access error during TCE cache lookup</bit>
+    <bit pos="20">ATS Effective Address hit multiple TCE cache entries</bit>
+    <bit pos="21">ATS TCE Page access error during TCE table-walk</bit>
+    <bit pos="22">ATS Timeout on TCE tree walk</bit>
+    <bit pos="23">ATS Parity error on TCE cache directory array</bit>
+    <bit pos="24">ATS Parity error on TCE cache data array</bit>
+    <bit pos="25">ATS ECC UE on Effective Address array</bit>
+    <bit pos="26">ATS ECC CE on Effective Address array</bit>
+    <bit pos="27">ATS ECC UE on TDRmem array (table-walk state machine also hangs)</bit>
+    <bit pos="28">ATS ECC CE on TDRmem array</bit>
+    <bit pos="29">ATS ECC UE on CQ CTL DMA Read data to TDR_mem array during table-walk</bit>
+    <bit pos="30">ATS ECC CE on CQ CTL DMA Read data to TDR_mem array during table-walk</bit>
+    <bit pos="31">ATS Parity error on TVT entry</bit>
+    <bit pos="32">ATS Parity error on IODA Address Register</bit>
+    <bit pos="33">ATS Parity error on ATS Control Register</bit>
+    <bit pos="34">ATS Parity error on ATS Timeout Control register</bit>
+    <bit pos="35">ATS Invalid IODA Table Address Register Table Select entry</bit>
+    <bit pos="36">ATS Reserved, macro bit 19</bit>
+    <bit pos="37">kill xlate epoch timeout.</bit>
+    <bit pos="38">XSL Reserved, macro bit 19.</bit>
+    <bit pos="39">XSL Reserved, macro bit 20.</bit>
+    <bit pos="40">XSL Reserved, macro bit 21.</bit>
+    <bit pos="41">XSL Reserved, macro bit 22.</bit>
+    <bit pos="42">XSL Reserved, macro bit 23.</bit>
+    <bit pos="43">XSL Reserved, macro bit 24.</bit>
+    <bit pos="44">XSL Reserved, macro bit 25.</bit>
+    <bit pos="45">XSL Reserved, macro bit 26.</bit>
+    <bit pos="46">XSL Reserved, macro bit 27.</bit>
+    <bit pos="47">NDL Brick6 stall</bit>
+    <bit pos="48">NDL Brick6 nostall</bit>
+    <bit pos="49">NDL Brick7 stall</bit>
+    <bit pos="50">NDL Brick7 nostall</bit>
+    <bit pos="51">NDL Brick8 stall</bit>
+    <bit pos="52">NDL Brick8 nostall</bit>
+    <bit pos="53">NDL Brick9 stall</bit>
+    <bit pos="54">NDL Brick9 nostall</bit>
+    <bit pos="55">NDL Brick10 stall</bit>
+    <bit pos="56">NDL Brick10 nostall</bit>
+    <bit pos="57">NDL Brick11 stall</bit>
+    <bit pos="58">NDL Brick11 nostall</bit>
+    <bit pos="59">AME ECC CE</bit>
+    <bit pos="60">MISC Pervasive SCOM satellite signaled internal FSM error (ring 0, sat 0)</bit>
+    <bit pos="61">MISC Pervasive SCOM satellite signaled internal FSM error (ring 0, sat 1)</bit>
+    <bit pos="62">Unused FIR</bit>
+    <bit pos="63">Unused FIR</bit>
+</attn_node>