Copied Chip Data XML from Hostboot project
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I0a230be8ba2840768e2097fd4e479c8feb8fc452
diff --git a/xml/p10/node_pci_etu_fir.xml b/xml/p10/node_pci_etu_fir.xml
new file mode 100644
index 0000000..65d43c4
--- /dev/null
+++ b/xml/p10/node_pci_etu_fir.xml
@@ -0,0 +1,77 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PCI_ETU_FIR" reg_type="SCOM">
+ <local_fir config="W" name="PCI_ETU_FIR">
+ <instance addr="0x08010908" reg_inst="0"/>
+ <instance addr="0x08010948" reg_inst="1"/>
+ <instance addr="0x08010988" reg_inst="2"/>
+ <instance addr="0x09010908" reg_inst="3"/>
+ <instance addr="0x09010948" reg_inst="4"/>
+ <instance addr="0x09010988" reg_inst="5"/>
+ <action attn_type="CS" config="00"/>
+ <action attn_type="RE" config="01"/>
+ </local_fir>
+ <bit pos="0">See Outbound Error Status Register, bit 0 for details.</bit>
+ <bit pos="1">See Outbound Error Status Register, bit 1/2 for details.</bit>
+ <bit pos="2">See Outbound Error Status Register, bit 3/8 for details.</bit>
+ <bit pos="3">See Outbound Error Status Register, bit 28 for details.</bit>
+ <bit pos="4">See Outbound Error Status Register, bit 4/5/9/10/11/14/15 for details.</bit>
+ <bit pos="5">ETU FIR Register</bit>
+ <bit pos="6">See Outbound Error Status Register, bit 6 for details.</bit>
+ <bit pos="7">See Outbound Error Status Register, bit 13/22 for details.</bit>
+ <bit pos="8">See Outbound Error Status Register, bit 23/37/38/40/43/44/45/47/48/49 for details.</bit>
+ <bit pos="9">See Outbound Error Status Register, bit 50/51/52 for details.</bit>
+ <bit pos="10">See Outbound Error Status Register, bit 19/20/21/53/54/55 for details.</bit>
+ <bit pos="11">See Outbound Error Status Register, bit 16 for details.</bit>
+ <bit pos="12">See Outbound Error Status Register, bit 17 for details.</bit>
+ <bit pos="13">See Outbound Error Status Register, bit 18 for details.</bit>
+ <bit pos="14">See Outbound Error Status Register, bit 56/57 for details.</bit>
+ <bit pos="15">See Outbound Error Status Register, bit 17 for details.</bit>
+ <bit pos="16">See RSB Error Status Register, bit 00 for details.</bit>
+ <bit pos="17">See RSB Error Status Register, bit 2/3/5 for details.</bit>
+ <bit pos="18">See RSB Error Status Register, bit 1/4 for details.</bit>
+ <bit pos="19">See RSB Error Status Register, bit 9/10 for details.</bit>
+ <bit pos="20">See RSB Error Status Register, bit 8 for details.</bit>
+ <bit pos="21">See RSB Error Status Register, bit 7 for details.</bit>
+ <bit pos="22">See RSB Error Status Register, bit 6 for details.</bit>
+ <bit pos="23">See RSB Error Status Register, bit 13/14 for details.</bit>
+ <bit pos="24">See RSB Error Status Register, bit 12 for details.</bit>
+ <bit pos="25">See Outbound Error Status Register, bit 11 for details.</bit>
+ <bit pos="26">See Outbound Error Status Register, bit 15/27 for details.</bit>
+ <bit pos="27">See RSB Error Status Register, bit 17/19 for details.</bit>
+ <bit pos="28">See RSB Error Status Register, bit 16/18 for details.</bit>
+ <bit pos="29">See RSB Error Status Register, bit 30/31 for details.</bit>
+ <bit pos="30">See RSB Error Status Register, bit 28/29 for details.</bit>
+ <bit pos="31">See RSB Error Status Register, bit 24/25/26 for details.</bit>
+ <bit pos="32">See ARB Error Status Register, bit 33 for details.</bit>
+ <bit pos="33">See ARB Error Status Register, bit 27 for details.</bit>
+ <bit pos="34">See ARB Error Status Register, bit 02/03 for details.</bit>
+ <bit pos="35">See ARB Error Status Register, bit 26/28 for details.</bit>
+ <bit pos="36">See ARB Error Status Register, bit 57 for details.</bit>
+ <bit pos="37">See ARB Error Status Register, bit 58 for details.</bit>
+ <bit pos="38">See ARB Error Status Register, bit 59 for details.</bit>
+ <bit pos="39">See Outbound Error Status Register, bit 39 for details.</bit>
+ <bit pos="40">See ARB Error Status Register, bit 4/7/8/9/10/11/12/13/14/15/16/17/18/22/23/36/37/38/42/43/44/45/46/47/48/59/55/56 for details.</bit>
+ <bit pos="41">See ARB Error Status Register, bit 32/41 for details.</bit>
+ <bit pos="42">See ARB Error Status Register, bit 00/01/19 for details.</bit>
+ <bit pos="43">See ARB Error Status Register, bit 34/35 for details.</bit>
+ <bit pos="44">See ARB Error Status Register, bit 5/20/25/29 for details.</bit>
+ <bit pos="45">See ARB Error Status Register, bit 6/26/30/31 for details.</bit>
+ <bit pos="46">See ARB Error Status Register, bit 24 for details.</bit>
+ <bit pos="47">See ARB Error Status Register, bit 40 for details.</bit>
+ <bit pos="48">See MRG Error Status Register, bit 08-16/22/23/26/28/30-37/40-50 for details.</bit>
+ <bit pos="49">See MRG Error Status Register, bit 51 for details.</bit>
+ <bit pos="50">See MRG Error Status Register, bit 40/56/58/60 for details.</bit>
+ <bit pos="51">See MRG Error Status Register, bit 41/57/59/61 for details.</bit>
+ <bit pos="52">See MRG Error Status Register, bit 24 for details.</bit>
+ <bit pos="53">See MRG Error Status Register, bit 17/18 for details.</bit>
+ <bit pos="54">ETU FIR Register</bit>
+ <bit pos="55">ETU FIR Register</bit>
+ <bit pos="56">See TCE Error Status Register, bit 01/02 for details.</bit>
+ <bit pos="57">See TCE Error Status Register, bit 08 for details.</bit>
+ <bit pos="58">See TCE Error Status Register, bit 13 for details.</bit>
+ <bit pos="59">See TCE Error Status Register for details.</bit>
+ <bit pos="60">See TCE Error Status Register, bit 09/11/25/27 for details.</bit>
+ <bit pos="61">See TCE Error Status Register, bit 10/12/26/28 for details.</bit>
+ <bit pos="62">ETU FIR Register</bit>
+ <bit pos="63">FIR Internal Parity Error.</bit>
+</attn_node>