| <?xml version="1.0" encoding="UTF-8"?> |
| <attn_node model_ec="P10_10" name="CFIR_MC_CS_RE_SPA" reg_type="SCOM"> |
| <register name="CFIR_MC_XSTOP"> |
| <instance addr="0x0C040000" reg_inst="0"/> |
| <instance addr="0x0D040000" reg_inst="1"/> |
| <instance addr="0x0E040000" reg_inst="2"/> |
| <instance addr="0x0F040000" reg_inst="3"/> |
| </register> |
| <register name="CFIR_MC_XSTOP_MASK"> |
| <instance addr="0x0C040040" reg_inst="0"/> |
| <instance addr="0x0D040040" reg_inst="1"/> |
| <instance addr="0x0E040040" reg_inst="2"/> |
| <instance addr="0x0F040040" reg_inst="3"/> |
| </register> |
| <register name="CFIR_MC_RECOV"> |
| <instance addr="0x0C040001" reg_inst="0"/> |
| <instance addr="0x0D040001" reg_inst="1"/> |
| <instance addr="0x0E040001" reg_inst="2"/> |
| <instance addr="0x0F040001" reg_inst="3"/> |
| </register> |
| <register name="CFIR_MC_RECOV_MASK"> |
| <instance addr="0x0C040041" reg_inst="0"/> |
| <instance addr="0x0D040041" reg_inst="1"/> |
| <instance addr="0x0E040041" reg_inst="2"/> |
| <instance addr="0x0F040041" reg_inst="3"/> |
| </register> |
| <register name="CFIR_MC_SPATTN"> |
| <instance addr="0x0C040002" reg_inst="0"/> |
| <instance addr="0x0D040002" reg_inst="1"/> |
| <instance addr="0x0E040002" reg_inst="2"/> |
| <instance addr="0x0F040002" reg_inst="3"/> |
| </register> |
| <register name="CFIR_MC_SPATTN_MASK"> |
| <instance addr="0x0C040042" reg_inst="0"/> |
| <instance addr="0x0D040042" reg_inst="1"/> |
| <instance addr="0x0E040042" reg_inst="2"/> |
| <instance addr="0x0F040042" reg_inst="3"/> |
| </register> |
| <rule attn_type="CS" node_inst="0:3"> |
| <expr type="and"> |
| <expr type="reg" value1="CFIR_MC_XSTOP"/> |
| <expr type="not"> |
| <expr type="reg" value1="CFIR_MC_XSTOP_MASK"/> |
| </expr> |
| <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/> |
| </expr> |
| </rule> |
| <rule attn_type="RE" node_inst="0:3"> |
| <expr type="and"> |
| <expr type="reg" value1="CFIR_MC_RECOV"/> |
| <expr type="not"> |
| <expr type="reg" value1="CFIR_MC_RECOV_MASK"/> |
| </expr> |
| <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/> |
| </expr> |
| </rule> |
| <rule attn_type="SPA" node_inst="0:3"> |
| <expr type="and"> |
| <expr type="reg" value1="CFIR_MC_SPATTN"/> |
| <expr type="not"> |
| <expr type="reg" value1="CFIR_MC_SPATTN_MASK"/> |
| </expr> |
| <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/> |
| </expr> |
| </rule> |
| <bit child_node="MC_LOCAL_FIR" node_inst="0,1,2,3" pos="4">Local FIR</bit> |
| <bit child_node="MC_DSTL_FIR" node_inst="0,2,4,6" pos="5">MC Fault Isolation Register (DSTLFIR)</bit> |
| <bit child_node="MC_USTL_FIR" node_inst="0,2,4,6" pos="6">MC Fault Isolation Register (USTLFIR)</bit> |
| <bit child_node="MC_DSTL_FIR" node_inst="1,3,5,7" pos="7">MC Fault Isolation Register (DSTLFIR)</bit> |
| <bit child_node="MC_USTL_FIR" node_inst="1,3,5,7" pos="8">MC Fault Isolation Register (USTLFIR)</bit> |
| <bit child_node="MC_FIR" node_inst="0,1,2,3" pos="9">MC Fault Isolation Register (MCFIR)</bit> |
| <bit child_node="MC_MISC_FIR" node_inst="0,1,2,3" pos="10">MISC Fault Isolation Register</bit> |
| <bit child_node="MC_OMI_DL_FIR" node_inst="0,2,4,6" pos="13">OMI-DL common FIR Register</bit> |
| <bit child_node="MC_OMI_DL_FIR" node_inst="1,3,5,7" pos="14">OMI-DL common FIR Register</bit> |
| </attn_node> |