Chip Data file updates for PAU, NMMU, and PCI FIRs
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I3da92a838eb04532e6f78a1f1ad2d40b52ff01d3
diff --git a/xml/p10/node_pci_etu_fir.xml b/xml/p10/node_pci_etu_fir.xml
index d64ba50..2a49a08 100644
--- a/xml/p10/node_pci_etu_fir.xml
+++ b/xml/p10/node_pci_etu_fir.xml
@@ -10,68 +10,68 @@
<action attn_type="CS" config="00"/>
<action attn_type="RE" config="01"/>
</local_fir>
- <bit pos="0">See Outbound Error Status Register, bit 0 for details.</bit>
- <bit pos="1">See Outbound Error Status Register, bit 1/2 for details.</bit>
- <bit pos="2">See Outbound Error Status Register, bit 3/8 for details.</bit>
- <bit pos="3">See Outbound Error Status Register, bit 28 for details.</bit>
- <bit pos="4">See Outbound Error Status Register, bit 4/5/9/10/11/14/15 for details.</bit>
- <bit pos="5">ETU FIR Register</bit>
- <bit pos="6">See Outbound Error Status Register, bit 6 for details.</bit>
- <bit pos="7">See Outbound Error Status Register, bit 13/22 for details.</bit>
- <bit pos="8">See Outbound Error Status Register, bit 23/37/38/40/43/44/45/47/48/49 for details.</bit>
- <bit pos="9">See Outbound Error Status Register, bit 50/51/52 for details.</bit>
- <bit pos="10">See Outbound Error Status Register, bit 19/20/21/53/54/55 for details.</bit>
- <bit pos="11">See Outbound Error Status Register, bit 16 for details.</bit>
- <bit pos="12">See Outbound Error Status Register, bit 17 for details.</bit>
- <bit pos="13">See Outbound Error Status Register, bit 18 for details.</bit>
- <bit pos="14">See Outbound Error Status Register, bit 56/57 for details.</bit>
- <bit pos="15">See Outbound Error Status Register, bit 17 for details.</bit>
- <bit pos="16">See RSB Error Status Register, bit 00 for details.</bit>
- <bit pos="17">See RSB Error Status Register, bit 2/3/5 for details.</bit>
- <bit pos="18">See RSB Error Status Register, bit 1/4 for details.</bit>
- <bit pos="19">See RSB Error Status Register, bit 9/10 for details.</bit>
- <bit pos="20">See RSB Error Status Register, bit 8 for details.</bit>
- <bit pos="21">See RSB Error Status Register, bit 7 for details.</bit>
- <bit pos="22">See RSB Error Status Register, bit 6 for details.</bit>
- <bit pos="23">See RSB Error Status Register, bit 13/14 for details.</bit>
- <bit pos="24">See RSB Error Status Register, bit 12 for details.</bit>
- <bit pos="25">See Outbound Error Status Register, bit 11 for details.</bit>
- <bit pos="26">See Outbound Error Status Register, bit 15/27 for details.</bit>
- <bit pos="27">See RSB Error Status Register, bit 17/19 for details.</bit>
- <bit pos="28">See RSB Error Status Register, bit 16/18 for details.</bit>
- <bit pos="29">See RSB Error Status Register, bit 30/31 for details.</bit>
- <bit pos="30">See RSB Error Status Register, bit 28/29 for details.</bit>
- <bit pos="31">See RSB Error Status Register, bit 24/25/26 for details.</bit>
- <bit pos="32">See ARB Error Status Register, bit 33 for details.</bit>
- <bit pos="33">See ARB Error Status Register, bit 27 for details.</bit>
- <bit pos="34">See ARB Error Status Register, bit 02/03 for details.</bit>
- <bit pos="35">See ARB Error Status Register, bit 26/28 for details.</bit>
- <bit pos="36">See ARB Error Status Register, bit 57 for details.</bit>
- <bit pos="37">See ARB Error Status Register, bit 58 for details.</bit>
- <bit pos="38">See ARB Error Status Register, bit 59 for details.</bit>
- <bit pos="39">See Outbound Error Status Register, bit 39 for details.</bit>
- <bit pos="40">See ARB Error Status Register, bit 4/7/8/9/10/11/12/13/14/15/16/17/18/22/23/36/37/38/42/43/44/45/46/47/48/59/55/56 for details.</bit>
- <bit pos="41">See ARB Error Status Register, bit 32/41 for details.</bit>
- <bit pos="42">See ARB Error Status Register, bit 00/01/19 for details.</bit>
- <bit pos="43">See ARB Error Status Register, bit 34/35 for details.</bit>
- <bit pos="44">See ARB Error Status Register, bit 5/20/25/29 for details.</bit>
- <bit pos="45">See ARB Error Status Register, bit 6/26/30/31 for details.</bit>
- <bit pos="46">See ARB Error Status Register, bit 24 for details.</bit>
- <bit pos="47">See ARB Error Status Register, bit 40 for details.</bit>
- <bit pos="48">See MRG Error Status Register, bit 08-16/22/23/26/28/30-37/40-50 for details.</bit>
- <bit pos="49">See MRG Error Status Register, bit 51 for details.</bit>
- <bit pos="50">See MRG Error Status Register, bit 40/56/58/60 for details.</bit>
- <bit pos="51">See MRG Error Status Register, bit 41/57/59/61 for details.</bit>
- <bit pos="52">See MRG Error Status Register, bit 24 for details.</bit>
- <bit pos="53">See MRG Error Status Register, bit 17/18 for details.</bit>
- <bit pos="54">ETU FIR Register</bit>
- <bit pos="55">ETU FIR Register</bit>
- <bit pos="56">See TCE Error Status Register, bit 01/02 for details.</bit>
- <bit pos="57">See TCE Error Status Register, bit 08 for details.</bit>
- <bit pos="58">See TCE Error Status Register, bit 13 for details.</bit>
- <bit pos="59">See TCE Error Status Register for details.</bit>
- <bit pos="60">See TCE Error Status Register, bit 09/11/25/27 for details.</bit>
- <bit pos="61">See TCE Error Status Register, bit 10/12/26/28 for details.</bit>
- <bit pos="62">ETU FIR Register</bit>
- <bit pos="63">FIR Internal Parity Error.</bit>
+ <bit pos="0">AIB_COMMAND_INVALID</bit>
+ <bit pos="1">AIB_ADDRESS_INVALID</bit>
+ <bit pos="2">AIB_ACCESS_ERROR</bit>
+ <bit pos="3">PAPR_OUTBOUND_INJECT_ERROR</bit>
+ <bit pos="4">AIB_FATAL_CLASS_ERROR</bit>
+ <bit pos="5">AIB_INF_CLASS_ERROR</bit>
+ <bit pos="6">spare</bit>
+ <bit pos="7">PE_STOP_STATE_SIGNALED</bit>
+ <bit pos="8">OUT_COMMON_ARRAY_FATAL_ERROR</bit>
+ <bit pos="9">OUT_COMMON_LATCH_FATAL_ERROR</bit>
+ <bit pos="10">OUT_COMMON_LOGIC_FATAL_ERROR</bit>
+ <bit pos="11">BLIF_OUT_INTERFACE_PARITY_ERROR</bit>
+ <bit pos="12">CFG_WRITE_CA_OR_UR_RESPONSE</bit>
+ <bit pos="13">MMIO_REQUEST_TIMEOUT</bit>
+ <bit pos="14">OUT_RRB_SOURCED_ERROR</bit>
+ <bit pos="15">CFG_LOGIC_SIGNALED_ERROR</bit>
+ <bit pos="16">RSB_REG_REQUEST_ADDRESS_ERROR</bit>
+ <bit pos="17">RSB_FDA_FATAL_ERROR</bit>
+ <bit pos="18">RSB_FDA_INF_ERROR</bit>
+ <bit pos="19">RSB_FDB_FATAL_ERROR</bit>
+ <bit pos="20">RSB_FDB_INF_ERROR</bit>
+ <bit pos="21">RSB_ERR_FATAL_ERROR</bit>
+ <bit pos="22">RSB_ERR_INF_ERROR</bit>
+ <bit pos="23">RSB_DBG_FATAL_ERROR</bit>
+ <bit pos="24">RSB_DBG_INF_ERROR</bit>
+ <bit pos="25">PCIE_REQUEST_ACCESS_ERROR</bit>
+ <bit pos="26">RSB_BUS_LOGIC_ERROR</bit>
+ <bit pos="27">RSB_UVI_FATAL_ERROR</bit>
+ <bit pos="28">RSB_UVI_INF_ERROR</bit>
+ <bit pos="29">SCOM_FATAL_ERROR</bit>
+ <bit pos="30">SCOM_INF_ERROR</bit>
+ <bit pos="31">PCIE_MACRO_ERROR_ACTIVE_STATUS</bit>
+ <bit pos="32">ARB_IODA_FATAL_ERROR</bit>
+ <bit pos="33">ARB_MSI_PE_MATCH_ERROR</bit>
+ <bit pos="34">ARB_MSI_ADDRESS_ERROR</bit>
+ <bit pos="35">ARB_TVT_ERROR</bit>
+ <bit pos="36">ARB_RCVD_FATAL_ERROR_MSG</bit>
+ <bit pos="37">ARB_RCVD_NONFATAL_ERROR_MSG</bit>
+ <bit pos="38">ARB_RCVD_CORRECTIBLE_ERROR_MSG</bit>
+ <bit pos="39">PAPR_INBOUND_INJECT_ERROR</bit>
+ <bit pos="40">ARB_COMMON_FATAL_ERROR</bit>
+ <bit pos="41">ARB_TABLE_BAR_DISABLED_ERROR</bit>
+ <bit pos="42">ARB_BLIF_COMPLETION_ERROR</bit>
+ <bit pos="43">ARB_PCT_TIMEOUT_ERROR</bit>
+ <bit pos="44">ARB_ECC_CORRECTABLE_ERROR</bit>
+ <bit pos="45">ARB_ECC_UNCORRECTABLE_ERROR</bit>
+ <bit pos="46">ARB_TLP_POISON_SIGNALED</bit>
+ <bit pos="47">ARB_RTT_PENUM_INVALID_ERROR</bit>
+ <bit pos="48">MRG_COMMON_FATAL_ERROR</bit>
+ <bit pos="49">MRG_TABLE_BAR_DISABLED_ERROR</bit>
+ <bit pos="50">MRG_ECC_CORRECTABLE_ERROR</bit>
+ <bit pos="51">MRG_ECC_UNCORRECTABLE_ERROR</bit>
+ <bit pos="52">MRG_AIB2_TX_TIMEOUT_ERROR</bit>
+ <bit pos="53">MRG_MRT_ERROR</bit>
+ <bit pos="54">spare</bit>
+ <bit pos="55">spare</bit>
+ <bit pos="56">TCE_IODA_PAGE_ACCESS_ERROR</bit>
+ <bit pos="57">TCE_REQUEST_TIMEOUT_ERROR</bit>
+ <bit pos="58">TCE_UNEXPECTED_RESPONSE_ERROR</bit>
+ <bit pos="59">TCE_COMMON_FATAL_ERROR</bit>
+ <bit pos="60">TCE_ECC_CORRECTABLE_ERROR</bit>
+ <bit pos="61">TCE_ECC_UNCORRECTABLE_ERROR</bit>
+ <bit pos="62">spare</bit>
+ <bit pos="63">FIR_INTERNAL_PARITY_ERROR</bit>
</attn_node>