xml/p10/node_eq_core_fir.xml

<?xml version="1.0" encoding="UTF-8"?>
<attn_node model_ec="P10_20" name="EQ_CORE_FIR" reg_type="SCOM">
    <register name="EQ_CORE_FIR">
        <instance addr="0x20028440" reg_inst="0"/>
        <instance addr="0x20024440" reg_inst="1"/>
        <instance addr="0x20022440" reg_inst="2"/>
        <instance addr="0x20021440" reg_inst="3"/>
        <instance addr="0x21028440" reg_inst="4"/>
        <instance addr="0x21024440" reg_inst="5"/>
        <instance addr="0x21022440" reg_inst="6"/>
        <instance addr="0x21021440" reg_inst="7"/>
        <instance addr="0x22028440" reg_inst="8"/>
        <instance addr="0x22024440" reg_inst="9"/>
        <instance addr="0x22022440" reg_inst="10"/>
        <instance addr="0x22021440" reg_inst="11"/>
        <instance addr="0x23028440" reg_inst="12"/>
        <instance addr="0x23024440" reg_inst="13"/>
        <instance addr="0x23022440" reg_inst="14"/>
        <instance addr="0x23021440" reg_inst="15"/>
        <instance addr="0x24028440" reg_inst="16"/>
        <instance addr="0x24024440" reg_inst="17"/>
        <instance addr="0x24022440" reg_inst="18"/>
        <instance addr="0x24021440" reg_inst="19"/>
        <instance addr="0x25028440" reg_inst="20"/>
        <instance addr="0x25024440" reg_inst="21"/>
        <instance addr="0x25022440" reg_inst="22"/>
        <instance addr="0x25021440" reg_inst="23"/>
        <instance addr="0x26028440" reg_inst="24"/>
        <instance addr="0x26024440" reg_inst="25"/>
        <instance addr="0x26022440" reg_inst="26"/>
        <instance addr="0x26021440" reg_inst="27"/>
        <instance addr="0x27028440" reg_inst="28"/>
        <instance addr="0x27024440" reg_inst="29"/>
        <instance addr="0x27022440" reg_inst="30"/>
        <instance addr="0x27021440" reg_inst="31"/>
    </register>
    <register name="EQ_CORE_FIR_MASK">
        <instance addr="0x20028443" reg_inst="0"/>
        <instance addr="0x20024443" reg_inst="1"/>
        <instance addr="0x20022443" reg_inst="2"/>
        <instance addr="0x20021443" reg_inst="3"/>
        <instance addr="0x21028443" reg_inst="4"/>
        <instance addr="0x21024443" reg_inst="5"/>
        <instance addr="0x21022443" reg_inst="6"/>
        <instance addr="0x21021443" reg_inst="7"/>
        <instance addr="0x22028443" reg_inst="8"/>
        <instance addr="0x22024443" reg_inst="9"/>
        <instance addr="0x22022443" reg_inst="10"/>
        <instance addr="0x22021443" reg_inst="11"/>
        <instance addr="0x23028443" reg_inst="12"/>
        <instance addr="0x23024443" reg_inst="13"/>
        <instance addr="0x23022443" reg_inst="14"/>
        <instance addr="0x23021443" reg_inst="15"/>
        <instance addr="0x24028443" reg_inst="16"/>
        <instance addr="0x24024443" reg_inst="17"/>
        <instance addr="0x24022443" reg_inst="18"/>
        <instance addr="0x24021443" reg_inst="19"/>
        <instance addr="0x25028443" reg_inst="20"/>
        <instance addr="0x25024443" reg_inst="21"/>
        <instance addr="0x25022443" reg_inst="22"/>
        <instance addr="0x25021443" reg_inst="23"/>
        <instance addr="0x26028443" reg_inst="24"/>
        <instance addr="0x26024443" reg_inst="25"/>
        <instance addr="0x26022443" reg_inst="26"/>
        <instance addr="0x26021443" reg_inst="27"/>
        <instance addr="0x27028443" reg_inst="28"/>
        <instance addr="0x27024443" reg_inst="29"/>
        <instance addr="0x27022443" reg_inst="30"/>
        <instance addr="0x27021443" reg_inst="31"/>
    </register>
    <register name="EQ_CORE_FIR_ACT0">
        <instance addr="0x20028446" reg_inst="0"/>
        <instance addr="0x20024446" reg_inst="1"/>
        <instance addr="0x20022446" reg_inst="2"/>
        <instance addr="0x20021446" reg_inst="3"/>
        <instance addr="0x21028446" reg_inst="4"/>
        <instance addr="0x21024446" reg_inst="5"/>
        <instance addr="0x21022446" reg_inst="6"/>
        <instance addr="0x21021446" reg_inst="7"/>
        <instance addr="0x22028446" reg_inst="8"/>
        <instance addr="0x22024446" reg_inst="9"/>
        <instance addr="0x22022446" reg_inst="10"/>
        <instance addr="0x22021446" reg_inst="11"/>
        <instance addr="0x23028446" reg_inst="12"/>
        <instance addr="0x23024446" reg_inst="13"/>
        <instance addr="0x23022446" reg_inst="14"/>
        <instance addr="0x23021446" reg_inst="15"/>
        <instance addr="0x24028446" reg_inst="16"/>
        <instance addr="0x24024446" reg_inst="17"/>
        <instance addr="0x24022446" reg_inst="18"/>
        <instance addr="0x24021446" reg_inst="19"/>
        <instance addr="0x25028446" reg_inst="20"/>
        <instance addr="0x25024446" reg_inst="21"/>
        <instance addr="0x25022446" reg_inst="22"/>
        <instance addr="0x25021446" reg_inst="23"/>
        <instance addr="0x26028446" reg_inst="24"/>
        <instance addr="0x26024446" reg_inst="25"/>
        <instance addr="0x26022446" reg_inst="26"/>
        <instance addr="0x26021446" reg_inst="27"/>
        <instance addr="0x27028446" reg_inst="28"/>
        <instance addr="0x27024446" reg_inst="29"/>
        <instance addr="0x27022446" reg_inst="30"/>
        <instance addr="0x27021446" reg_inst="31"/>
    </register>
    <register name="EQ_CORE_FIR_ACT1">
        <instance addr="0x20028447" reg_inst="0"/>
        <instance addr="0x20024447" reg_inst="1"/>
        <instance addr="0x20022447" reg_inst="2"/>
        <instance addr="0x20021447" reg_inst="3"/>
        <instance addr="0x21028447" reg_inst="4"/>
        <instance addr="0x21024447" reg_inst="5"/>
        <instance addr="0x21022447" reg_inst="6"/>
        <instance addr="0x21021447" reg_inst="7"/>
        <instance addr="0x22028447" reg_inst="8"/>
        <instance addr="0x22024447" reg_inst="9"/>
        <instance addr="0x22022447" reg_inst="10"/>
        <instance addr="0x22021447" reg_inst="11"/>
        <instance addr="0x23028447" reg_inst="12"/>
        <instance addr="0x23024447" reg_inst="13"/>
        <instance addr="0x23022447" reg_inst="14"/>
        <instance addr="0x23021447" reg_inst="15"/>
        <instance addr="0x24028447" reg_inst="16"/>
        <instance addr="0x24024447" reg_inst="17"/>
        <instance addr="0x24022447" reg_inst="18"/>
        <instance addr="0x24021447" reg_inst="19"/>
        <instance addr="0x25028447" reg_inst="20"/>
        <instance addr="0x25024447" reg_inst="21"/>
        <instance addr="0x25022447" reg_inst="22"/>
        <instance addr="0x25021447" reg_inst="23"/>
        <instance addr="0x26028447" reg_inst="24"/>
        <instance addr="0x26024447" reg_inst="25"/>
        <instance addr="0x26022447" reg_inst="26"/>
        <instance addr="0x26021447" reg_inst="27"/>
        <instance addr="0x27028447" reg_inst="28"/>
        <instance addr="0x27024447" reg_inst="29"/>
        <instance addr="0x27022447" reg_inst="30"/>
        <instance addr="0x27021447" reg_inst="31"/>
    </register>
    <register name="EQ_CORE_FIR_WOF">
        <instance addr="0x20028448" reg_inst="0"/>
        <instance addr="0x20024448" reg_inst="1"/>
        <instance addr="0x20022448" reg_inst="2"/>
        <instance addr="0x20021448" reg_inst="3"/>
        <instance addr="0x21028448" reg_inst="4"/>
        <instance addr="0x21024448" reg_inst="5"/>
        <instance addr="0x21022448" reg_inst="6"/>
        <instance addr="0x21021448" reg_inst="7"/>
        <instance addr="0x22028448" reg_inst="8"/>
        <instance addr="0x22024448" reg_inst="9"/>
        <instance addr="0x22022448" reg_inst="10"/>
        <instance addr="0x22021448" reg_inst="11"/>
        <instance addr="0x23028448" reg_inst="12"/>
        <instance addr="0x23024448" reg_inst="13"/>
        <instance addr="0x23022448" reg_inst="14"/>
        <instance addr="0x23021448" reg_inst="15"/>
        <instance addr="0x24028448" reg_inst="16"/>
        <instance addr="0x24024448" reg_inst="17"/>
        <instance addr="0x24022448" reg_inst="18"/>
        <instance addr="0x24021448" reg_inst="19"/>
        <instance addr="0x25028448" reg_inst="20"/>
        <instance addr="0x25024448" reg_inst="21"/>
        <instance addr="0x25022448" reg_inst="22"/>
        <instance addr="0x25021448" reg_inst="23"/>
        <instance addr="0x26028448" reg_inst="24"/>
        <instance addr="0x26024448" reg_inst="25"/>
        <instance addr="0x26022448" reg_inst="26"/>
        <instance addr="0x26021448" reg_inst="27"/>
        <instance addr="0x27028448" reg_inst="28"/>
        <instance addr="0x27024448" reg_inst="29"/>
        <instance addr="0x27022448" reg_inst="30"/>
        <instance addr="0x27021448" reg_inst="31"/>
    </register>
    <rule attn_type="CS" node_inst="0:31">
        <!-- FIR & ~MASK & ~ACT0 & ~ACT1 -->
        <expr type="and">
            <expr type="reg" value1="EQ_CORE_FIR"/>
            <expr type="not">
                <expr type="reg" value1="EQ_CORE_FIR_MASK"/>
            </expr>
            <expr type="not">
                <expr type="reg" value1="EQ_CORE_FIR_ACT0"/>
            </expr>
            <expr type="not">
                <expr type="reg" value1="EQ_CORE_FIR_ACT1"/>
            </expr>
        </expr>
    </rule>
    <rule attn_type="RE" node_inst="0:31">
        <!-- WOF & ~MASK & ~ACT0 & ACT1 -->
        <expr type="and">
            <expr type="reg" value1="EQ_CORE_FIR_WOF"/>
            <expr type="not">
                <expr type="reg" value1="EQ_CORE_FIR_MASK"/>
            </expr>
            <expr type="not">
                <expr type="reg" value1="EQ_CORE_FIR_ACT0"/>
            </expr>
            <expr type="reg" value1="EQ_CORE_FIR_ACT1"/>
        </expr>
    </rule>
    <rule attn_type="UCS" node_inst="0:31">
        <!-- FIR & ~MASK & ACT0 & ACT1 -->
        <expr type="and">
            <expr type="reg" value1="EQ_CORE_FIR"/>
            <expr type="not">
                <expr type="reg" value1="EQ_CORE_FIR_MASK"/>
            </expr>
            <expr type="reg" value1="EQ_CORE_FIR_ACT0"/>
            <expr type="reg" value1="EQ_CORE_FIR_ACT1"/>
        </expr>
    </rule>
    <bit pos="0">IFU SRAM recoverable error (ICACHE parity error, etc)</bit>
    <bit pos="1">TC checkstop</bit>
    <bit pos="2">IFU RegFile recoverable error</bit>
    <bit pos="3">IFU RegFile core checkstop</bit>
    <bit pos="4">IFU logic recoverable error</bit>
    <bit pos="5">IFU logic core checkstop</bit>
    <bit pos="6">reserved</bit>
    <bit pos="7">VSU Inference Accumulator recoverable error</bit>
    <bit pos="8">Recovery core checkstop</bit>
    <bit pos="9">VSU Slice Targeted File (STF) recoverable error</bit>
    <bit pos="10">reserved</bit>
    <bit pos="11">ISU logic recoverable error</bit>
    <bit pos="12">ISU logic core checkstop</bit>
    <bit pos="13">reserved</bit>
    <bit pos="14">MCHK received while ME=0 - non recoverable</bit>
    <bit pos="15">UE from L2</bit>
    <bit pos="16">Number of UEs from L2 above threshold</bit>
    <bit pos="17">UE on CI load</bit>
    <bit pos="18">MMU TLB parity recoverable error</bit>
    <bit pos="19">MMU SLB parity recoverable error</bit>
    <bit pos="20">reserved</bit>
    <bit pos="21">MMU CXT recoverable error</bit>
    <bit pos="22">MMU logic core checkstop</bit>
    <bit pos="23">MMU system checkstop</bit>
    <bit pos="24">VSU logic recoverable error</bit>
    <bit pos="25">VSU logic core checkstop</bit>
    <bit pos="26">Thread in maintenance mode and receives recovery request</bit>
    <bit pos="27">reserved</bit>
    <bit pos="28">PC system checkstop - Recoverable error received when recovery disabled</bit>
    <bit pos="29">LSU SRAM recoverable error (DCACHE parity error, ERAT parity error, etc)</bit>
    <bit pos="30">LSU set deleted</bit>
    <bit pos="31">LSU RegFile recoverable error</bit>
    <bit pos="32">LSU RegFile core checkstop</bit>
    <bit pos="33">MMU TLB multi hit error occurred</bit>
    <bit pos="34">MMU SLB multi hit error occurred</bit>
    <bit pos="35">LSU ERAT multi hit error occurred</bit>
    <bit pos="36">PC forward progress error</bit>
    <bit pos="37">LSU logic recoverable error</bit>
    <bit pos="38">LSU logic core checkstop</bit>
    <bit pos="39">reserved</bit>
    <bit pos="40">reserved</bit>
    <bit pos="41">LSU system checkstop</bit>
    <bit pos="42">reserved</bit>
    <bit pos="43">PC thread hang recoverable error</bit>
    <bit pos="44">reserved</bit>
    <bit pos="45">PC logic checkstop</bit>
    <bit pos="46">PC TimeBase Facility checkstop</bit>
    <bit pos="47">PC TimeBase Facility checkstop</bit>
    <bit pos="48">reserved</bit>
    <bit pos="49">reserved</bit>
    <bit pos="50">reserved</bit>
    <bit pos="51">reserved</bit>
    <bit pos="52">Hang Recovery Failed</bit>
    <bit pos="53">Core Hang detected</bit>
    <bit pos="54">reserved</bit>
    <bit pos="55">Nest Hang detected</bit>
    <bit pos="56">Other Core Chiplet recoverable error</bit>
    <bit pos="57">Other Core Chiplet core checkstop</bit>
    <bit pos="58">Other Core Chiplet system checkstop</bit>
    <bit pos="59">SCOM satellite error detected</bit>
    <bit pos="60">Debug Trigger error inject</bit>
    <bit pos="61">SCOM or Firmware recoverable error inject</bit>
    <bit pos="62">Firmware checkstop error inject</bit>
    <bit pos="63">PHYP checkstop via SPRC/SPRD</bit>
</attn_node>