xml/p10/node_cfir_eq_cs.xml

<?xml version="1.0" encoding="UTF-8"?>
<attn_node model_ec="P10_10,P10_20" name="CFIR_EQ_CS" reg_type="SCOM">
    <register name="CFIR_EQ_XSTOP">
        <instance addr="0x20040000" reg_inst="0"/>
        <instance addr="0x21040000" reg_inst="1"/>
        <instance addr="0x22040000" reg_inst="2"/>
        <instance addr="0x23040000" reg_inst="3"/>
        <instance addr="0x24040000" reg_inst="4"/>
        <instance addr="0x25040000" reg_inst="5"/>
        <instance addr="0x26040000" reg_inst="6"/>
        <instance addr="0x27040000" reg_inst="7"/>
    </register>
    <register name="CFIR_EQ_XSTOP_MASK">
        <instance addr="0x20040040" reg_inst="0"/>
        <instance addr="0x21040040" reg_inst="1"/>
        <instance addr="0x22040040" reg_inst="2"/>
        <instance addr="0x23040040" reg_inst="3"/>
        <instance addr="0x24040040" reg_inst="4"/>
        <instance addr="0x25040040" reg_inst="5"/>
        <instance addr="0x26040040" reg_inst="6"/>
        <instance addr="0x27040040" reg_inst="7"/>
    </register>
    <rule attn_type="CS" node_inst="0:7">
        <expr type="and">
            <expr type="reg" value1="CFIR_EQ_XSTOP"/>
            <expr type="not">
                <expr type="reg" value1="CFIR_EQ_XSTOP_MASK"/>
            </expr>
            <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
        </expr>
    </rule>
    <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Local FIR</bit>
    <bit child_node="EQ_L2_FIR" node_inst="0,4,8,12,16,20,24,28" pos="9">L2 FIR Register</bit>
    <bit child_node="EQ_L2_FIR" node_inst="1,5,9,13,17,21,25,29" pos="10">L2 FIR Register</bit>
    <bit child_node="EQ_L2_FIR" node_inst="2,6,10,14,18,22,26,30" pos="11">L2 FIR Register</bit>
    <bit child_node="EQ_L2_FIR" node_inst="3,7,11,15,19,23,27,31" pos="12">L2 FIR Register</bit>
    <bit child_node="EQ_L3_FIR" node_inst="0,4,8,12,16,20,24,28" pos="13">L3 FIR Register</bit>
    <bit child_node="EQ_L3_FIR" node_inst="1,5,9,13,17,21,25,29" pos="14">L3 FIR Register</bit>
    <bit child_node="EQ_L3_FIR" node_inst="2,6,10,14,18,22,26,30" pos="15">L3 FIR Register</bit>
    <bit child_node="EQ_L3_FIR" node_inst="3,7,11,15,19,23,27,31" pos="16">L3 FIR Register</bit>
    <bit child_node="EQ_NCU_FIR" node_inst="0,4,8,12,16,20,24,28" pos="17">NCU FIR Register</bit>
    <bit child_node="EQ_NCU_FIR" node_inst="1,5,9,13,17,21,25,29" pos="18">NCU FIR Register</bit>
    <bit child_node="EQ_NCU_FIR" node_inst="2,6,10,14,18,22,26,30" pos="19">NCU FIR Register</bit>
    <bit child_node="EQ_NCU_FIR" node_inst="3,7,11,15,19,23,27,31" pos="20">NCU FIR Register</bit>
    <bit child_node="EQ_QME_FIR" node_inst="0,1,2,3,4,5,6,7" pos="21">QME Local Fault Isolation Register</bit>
    <bit child_node="EQ_CORE_FIR" node_inst="0,4,8,12,16,20,24,28" pos="5">Core Fault Isolation Register</bit>
    <bit child_node="EQ_CORE_FIR" node_inst="1,5,9,13,17,21,25,29" pos="6">Core Fault Isolation Register</bit>
    <bit child_node="EQ_CORE_FIR" node_inst="2,6,10,14,18,22,26,30" pos="7">Core Fault Isolation Register</bit>
    <bit child_node="EQ_CORE_FIR" node_inst="3,7,11,15,19,23,27,31" pos="8">Core Fault Isolation Register</bit>
</attn_node>