| <?xml version="1.0" encoding="UTF-8"?> |
| <attn_node model_ec="P10_10,P10_20" name="CFIR_N0_UCS" reg_type="SCOM"> |
| <register name="CFIR_N0_LOCAL_XSTOP"> |
| <instance addr="0x02040003" reg_inst="0"/> |
| </register> |
| <register name="CFIR_N0_LOCAL_XSTOP_MASK"> |
| <instance addr="0x02040043" reg_inst="0"/> |
| </register> |
| <rule attn_type="UCS" node_inst="0"> |
| <expr type="and"> |
| <expr type="reg" value1="CFIR_N0_LOCAL_XSTOP"/> |
| <expr type="not"> |
| <expr type="reg" value1="CFIR_N0_LOCAL_XSTOP_MASK"/> |
| </expr> |
| <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/> |
| </expr> |
| </rule> |
| <bit child_node="N0_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit> |
| <bit child_node="NMMU_CQ_FIR" node_inst="0" pos="5">PBI CQ FIR Register</bit> |
| <bit child_node="NMMU_FIR" node_inst="0" pos="6">NMMU FIR1 Register</bit> |
| <bit child_node="VAS_FIR" node_inst="0" pos="8">Local FIR register for the VAS unit logic</bit> |
| <bit child_node="NX_DMA_ENG_FIR" node_inst="0" pos="9">DMA and Engine Fault Isolation Register</bit> |
| <bit child_node="NX_CQ_FIR" node_inst="0" pos="10">PBI CQ FIR Register</bit> |
| </attn_node> |