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gerrit.openbmc.org / openbmc / openpower-libhei / 201d53a7826b7de4c369a69c5aca8c7262be529d / . / xml / p10 / node_pll_unlock.xml
blob: ae690f7cefe2a313fa3f83c4e7f1181e08f41c91 [file] [log] [blame]
Zane Shelleyc905d2b2021-07-28 17:38:56 -0500[diff] [blame]1<?xml version="1.0" encoding="UTF-8"?>
2<attn_node model_ec="P10_10,P10_20" name="PLL_UNLOCK" reg_type="SCOM">
3
4 <capture_group node_inst="0">
5 <capture_register reg_name="ROOT_CTRL0" reg_inst= "0" />
6 <capture_register reg_name="ROOT_CTRL3" reg_inst= "0" />
7 <capture_register reg_name="ROOT_CTRL4" reg_inst= "0" />
8 <capture_register reg_name="ROOT_CTRL5" reg_inst= "0" />
9 <capture_register reg_name="ROOT_CTRL6" reg_inst= "0" />
10 <capture_register reg_name="RCS_SENSE_1" reg_inst= "0" />
11 <capture_register reg_name="RCS_SENSE_2" reg_inst= "0" />
12 <capture_register reg_name="PCBSLV_CONFIG" reg_inst= "1" />
13 <capture_register reg_name="PCBSLV_CONFIG" reg_inst= "2" />
14 <capture_register reg_name="PCBSLV_CONFIG" reg_inst= "3" />
15 <capture_register reg_name="PCBSLV_CONFIG" reg_inst= "8" />
16 <capture_register reg_name="PCBSLV_CONFIG" reg_inst= "9" />
17 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="12" />
18 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="13" />
19 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="14" />
20 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="15" />
21 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="16" />
22 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="17" />
23 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="18" />
24 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="19" />
25 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="24" />
26 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="25" />
27 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="26" />
28 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="27" />
29 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="28" />
30 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="29" />
31 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="30" />
32 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="31" />
33 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="32" />
34 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="33" />
35 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="34" />
36 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="35" />
37 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="36" />
38 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="37" />
39 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="38" />
40 <capture_register reg_name="PCBSLV_CONFIG" reg_inst="39" />
41 <capture_register reg_name="BC_OR_PCBSLV_ERROR" reg_inst= "0" />
42 <capture_register reg_name="PCBSLV_ERROR" reg_inst= "1" />
43 <capture_register reg_name="PCBSLV_ERROR" reg_inst= "2" />
44 <capture_register reg_name="PCBSLV_ERROR" reg_inst= "3" />
45 <capture_register reg_name="PCBSLV_ERROR" reg_inst= "8" />
46 <capture_register reg_name="PCBSLV_ERROR" reg_inst= "9" />
47 <capture_register reg_name="PCBSLV_ERROR" reg_inst="12" />
48 <capture_register reg_name="PCBSLV_ERROR" reg_inst="13" />
49 <capture_register reg_name="PCBSLV_ERROR" reg_inst="14" />
50 <capture_register reg_name="PCBSLV_ERROR" reg_inst="15" />
51 <capture_register reg_name="PCBSLV_ERROR" reg_inst="16" />
52 <capture_register reg_name="PCBSLV_ERROR" reg_inst="17" />
53 <capture_register reg_name="PCBSLV_ERROR" reg_inst="18" />
54 <capture_register reg_name="PCBSLV_ERROR" reg_inst="19" />
55 <capture_register reg_name="PCBSLV_ERROR" reg_inst="24" />
56 <capture_register reg_name="PCBSLV_ERROR" reg_inst="25" />
57 <capture_register reg_name="PCBSLV_ERROR" reg_inst="26" />
58 <capture_register reg_name="PCBSLV_ERROR" reg_inst="27" />
59 <capture_register reg_name="PCBSLV_ERROR" reg_inst="28" />
60 <capture_register reg_name="PCBSLV_ERROR" reg_inst="29" />
61 <capture_register reg_name="PCBSLV_ERROR" reg_inst="30" />
62 <capture_register reg_name="PCBSLV_ERROR" reg_inst="31" />
63 <capture_register reg_name="PCBSLV_ERROR" reg_inst="32" />
64 <capture_register reg_name="PCBSLV_ERROR" reg_inst="33" />
65 <capture_register reg_name="PCBSLV_ERROR" reg_inst="34" />
66 <capture_register reg_name="PCBSLV_ERROR" reg_inst="35" />
67 <capture_register reg_name="PCBSLV_ERROR" reg_inst="36" />
68 <capture_register reg_name="PCBSLV_ERROR" reg_inst="37" />
69 <capture_register reg_name="PCBSLV_ERROR" reg_inst="38" />
70 <capture_register reg_name="PCBSLV_ERROR" reg_inst="39" />
71 </capture_group>
72
73 <rule attn_type="CS" node_inst="0">
74 <expr type="or">
75 <!-- PLL summary for clock 0 -->
76 <expr type="and">
77 <!-- Check for primary clock 0 (RCS_SENSE_1[12]) -->
78 <expr type="lshift" value1="12">
79 <expr type="reg" value1="RCS_SENSE_1" />
80 </expr>
81 <!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
82 <expr type="or">
83 <expr type="lshift" value1="24">
84 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
85 </expr>
86 <expr type="lshift" value1="25">
87 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
88 </expr>
89 <expr type="lshift" value1="26">
90 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
91 </expr>
92 <expr type="lshift" value1="27">
93 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
94 </expr>
95 <expr type="lshift" value1="28">
96 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
97 </expr>
98 <expr type="lshift" value1="29">
99 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
100 </expr>
101 <expr type="lshift" value1="30">
102 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
103 </expr>
104 <expr type="lshift" value1="31">
105 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
106 </expr>
107 </expr>
108 <!-- The summary has been shifted to the left most bit. -->
109 <expr type="int" value1="0x8000000000000000"/>
110 </expr>
111 <!-- PLL summary for clock 1 -->
112 <expr type="rshift" value1="1">
113 <expr type="and">
114 <!-- Check for primary clock 1 (RCS_SENSE_1[13]) -->
115 <expr type="lshift" value1="13">
116 <expr type="reg" value1="RCS_SENSE_1" />
117 </expr>
118 <!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
119 <expr type="or">
120 <expr type="lshift" value1="24">
121 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
122 </expr>
123 <expr type="lshift" value1="25">
124 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
125 </expr>
126 <expr type="lshift" value1="26">
127 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
128 </expr>
129 <expr type="lshift" value1="27">
130 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
131 </expr>
132 <expr type="lshift" value1="28">
133 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
134 </expr>
135 <expr type="lshift" value1="29">
136 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
137 </expr>
138 <expr type="lshift" value1="30">
139 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
140 </expr>
141 <expr type="lshift" value1="31">
142 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
143 </expr>
144 </expr>
145 <!-- The summary has been shifted to the left most bit. -->
146 <expr type="int" value1="0x8000000000000000"/>
147 </expr>
148 </expr>
149 </expr>
150 </rule>
151
152 <rule attn_type="RE" node_inst="0">
153 <expr type="or">
154 <!-- PLL summary for clock 0 -->
155 <expr type="and">
156 <!-- Check for primary clock 0 (RCS_SENSE_1[12]) -->
157 <expr type="lshift" value1="12">
158 <expr type="reg" value1="RCS_SENSE_1" />
159 </expr>
160 <!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
161 <expr type="or">
162 <expr type="lshift" value1="24">
163 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
164 </expr>
165 <expr type="lshift" value1="25">
166 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
167 </expr>
168 <expr type="lshift" value1="26">
169 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
170 </expr>
171 <expr type="lshift" value1="27">
172 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
173 </expr>
174 <expr type="lshift" value1="28">
175 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
176 </expr>
177 <expr type="lshift" value1="29">
178 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
179 </expr>
180 <expr type="lshift" value1="30">
181 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
182 </expr>
183 <expr type="lshift" value1="31">
184 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
185 </expr>
186 </expr>
187 <!-- The summary has been shifted to the left most bit. -->
188 <expr type="int" value1="0x8000000000000000"/>
189 </expr>
190 <!-- PLL summary for clock 1 -->
191 <expr type="rshift" value1="1">
192 <expr type="and">
193 <!-- Check for primary clock 1 (RCS_SENSE_1[13]) -->
194 <expr type="lshift" value1="13">
195 <expr type="reg" value1="RCS_SENSE_1" />
196 </expr>
197 <!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
198 <expr type="or">
199 <expr type="lshift" value1="24">
200 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
201 </expr>
202 <expr type="lshift" value1="25">
203 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
204 </expr>
205 <expr type="lshift" value1="26">
206 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
207 </expr>
208 <expr type="lshift" value1="27">
209 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
210 </expr>
211 <expr type="lshift" value1="28">
212 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
213 </expr>
214 <expr type="lshift" value1="29">
215 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
216 </expr>
217 <expr type="lshift" value1="30">
218 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
219 </expr>
220 <expr type="lshift" value1="31">
221 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
222 </expr>
223 </expr>
224 <!-- The summary has been shifted to the left most bit. -->
225 <expr type="int" value1="0x8000000000000000"/>
226 </expr>
227 </expr>
228 </expr>
229 </rule>
230
231 <rule attn_type="SPA" node_inst="0">
232 <expr type="or">
233 <!-- PLL summary for clock 0 -->
234 <expr type="and">
235 <!-- Check for primary clock 0 (RCS_SENSE_1[12]) -->
236 <expr type="lshift" value1="12">
237 <expr type="reg" value1="RCS_SENSE_1" />
238 </expr>
239 <!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
240 <expr type="or">
241 <expr type="lshift" value1="24">
242 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
243 </expr>
244 <expr type="lshift" value1="25">
245 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
246 </expr>
247 <expr type="lshift" value1="26">
248 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
249 </expr>
250 <expr type="lshift" value1="27">
251 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
252 </expr>
253 <expr type="lshift" value1="28">
254 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
255 </expr>
256 <expr type="lshift" value1="29">
257 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
258 </expr>
259 <expr type="lshift" value1="30">
260 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
261 </expr>
262 <expr type="lshift" value1="31">
263 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
264 </expr>
265 </expr>
266 <!-- The summary has been shifted to the left most bit. -->
267 <expr type="int" value1="0x8000000000000000"/>
268 </expr>
269 <!-- PLL summary for clock 1 -->
270 <expr type="rshift" value1="1">
271 <expr type="and">
272 <!-- Check for primary clock 1 (RCS_SENSE_1[13]) -->
273 <expr type="lshift" value1="13">
274 <expr type="reg" value1="RCS_SENSE_1" />
275 </expr>
276 <!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
277 <expr type="or">
278 <expr type="lshift" value1="24">
279 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
280 </expr>
281 <expr type="lshift" value1="25">
282 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
283 </expr>
284 <expr type="lshift" value1="26">
285 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
286 </expr>
287 <expr type="lshift" value1="27">
288 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
289 </expr>
290 <expr type="lshift" value1="28">
291 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
292 </expr>
293 <expr type="lshift" value1="29">
294 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
295 </expr>
296 <expr type="lshift" value1="30">
297 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
298 </expr>
299 <expr type="lshift" value1="31">
300 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
301 </expr>
302 </expr>
303 <!-- The summary has been shifted to the left most bit. -->
304 <expr type="int" value1="0x8000000000000000"/>
305 </expr>
306 </expr>
307 </expr>
308 </rule>
309
310 <rule attn_type="UCS" node_inst="0">
311 <expr type="or">
312 <!-- PLL summary for clock 0 -->
313 <expr type="and">
314 <!-- Check for primary clock 0 (RCS_SENSE_1[12]) -->
315 <expr type="lshift" value1="12">
316 <expr type="reg" value1="RCS_SENSE_1" />
317 </expr>
318 <!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
319 <expr type="or">
320 <expr type="lshift" value1="24">
321 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
322 </expr>
323 <expr type="lshift" value1="25">
324 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
325 </expr>
326 <expr type="lshift" value1="26">
327 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
328 </expr>
329 <expr type="lshift" value1="27">
330 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
331 </expr>
332 <expr type="lshift" value1="28">
333 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
334 </expr>
335 <expr type="lshift" value1="29">
336 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
337 </expr>
338 <expr type="lshift" value1="30">
339 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
340 </expr>
341 <expr type="lshift" value1="31">
342 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
343 </expr>
344 </expr>
345 <!-- The summary has been shifted to the left most bit. -->
346 <expr type="int" value1="0x8000000000000000"/>
347 </expr>
348 <!-- PLL summary for clock 1 -->
349 <expr type="rshift" value1="1">
350 <expr type="and">
351 <!-- Check for primary clock 1 (RCS_SENSE_1[13]) -->
352 <expr type="lshift" value1="13">
353 <expr type="reg" value1="RCS_SENSE_1" />
354 </expr>
355 <!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
356 <expr type="or">
357 <expr type="lshift" value1="24">
358 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
359 </expr>
360 <expr type="lshift" value1="25">
361 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
362 </expr>
363 <expr type="lshift" value1="26">
364 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
365 </expr>
366 <expr type="lshift" value1="27">
367 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
368 </expr>
369 <expr type="lshift" value1="28">
370 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
371 </expr>
372 <expr type="lshift" value1="29">
373 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
374 </expr>
375 <expr type="lshift" value1="30">
376 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
377 </expr>
378 <expr type="lshift" value1="31">
379 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
380 </expr>
381 </expr>
382 <!-- The summary has been shifted to the left most bit. -->
383 <expr type="int" value1="0x8000000000000000"/>
384 </expr>
385 </expr>
386 </expr>
387 </rule>
388
389 <rule attn_type="HA" node_inst="0">
390 <expr type="or">
391 <!-- PLL summary for clock 0 -->
392 <expr type="and">
393 <!-- Check for primary clock 0 (RCS_SENSE_1[12]) -->
394 <expr type="lshift" value1="12">
395 <expr type="reg" value1="RCS_SENSE_1" />
396 </expr>
397 <!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
398 <expr type="or">
399 <expr type="lshift" value1="24">
400 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
401 </expr>
402 <expr type="lshift" value1="25">
403 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
404 </expr>
405 <expr type="lshift" value1="26">
406 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
407 </expr>
408 <expr type="lshift" value1="27">
409 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
410 </expr>
411 <expr type="lshift" value1="28">
412 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
413 </expr>
414 <expr type="lshift" value1="29">
415 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
416 </expr>
417 <expr type="lshift" value1="30">
418 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
419 </expr>
420 <expr type="lshift" value1="31">
421 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
422 </expr>
423 </expr>
424 <!-- The summary has been shifted to the left most bit. -->
425 <expr type="int" value1="0x8000000000000000"/>
426 </expr>
427 <!-- PLL summary for clock 1 -->
428 <expr type="rshift" value1="1">
429 <expr type="and">
430 <!-- Check for primary clock 1 (RCS_SENSE_1[13]) -->
431 <expr type="lshift" value1="13">
432 <expr type="reg" value1="RCS_SENSE_1" />
433 </expr>
434 <!-- Summary of BC_OR_PCBSLV_ERROR[24:31] -->
435 <expr type="or">
436 <expr type="lshift" value1="24">
437 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
438 </expr>
439 <expr type="lshift" value1="25">
440 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
441 </expr>
442 <expr type="lshift" value1="26">
443 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
444 </expr>
445 <expr type="lshift" value1="27">
446 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
447 </expr>
448 <expr type="lshift" value1="28">
449 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
450 </expr>
451 <expr type="lshift" value1="29">
452 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
453 </expr>
454 <expr type="lshift" value1="30">
455 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
456 </expr>
457 <expr type="lshift" value1="31">
458 <expr type="reg" value1="BC_OR_PCBSLV_ERROR" />
459 </expr>
460 </expr>
461 <!-- The summary has been shifted to the left most bit. -->
462 <expr type="int" value1="0x8000000000000000"/>
463 </expr>
464 </expr>
465 </expr>
466 </rule>
467
468 <bit pos="0">PLL unlock on clk A</bit>
469 <bit pos="1">PLL unlock on clk B</bit>
470
471</attn_node>